X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSimpleRegisterCoalescing.cpp;h=bc833633ed24f05cb43fa5458e1605b02ee6e3b3;hb=b3db9c90d24682340f043a8151063128fe3b220b;hp=da8b39fb2d06ed624a52b337251de9072cb87fbc;hpb=84bc5427d6883f73cfeae3da640acd011d35c006;p=oota-llvm.git diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index da8b39fb2d0..bc833633ed2 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -17,7 +17,6 @@ #include "VirtRegMap.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/Value.h" -#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineLoopInfo.h" @@ -36,40 +35,42 @@ using namespace llvm; STATISTIC(numJoins , "Number of interval joins performed"); +STATISTIC(numSubJoins , "Number of subclass joins performed"); +STATISTIC(numCommutes , "Number of instruction commuting performed"); +STATISTIC(numExtends , "Number of copies extended"); STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); STATISTIC(numAborts , "Number of times interval joining aborted"); char SimpleRegisterCoalescing::ID = 0; -namespace { - static cl::opt - EnableJoining("join-liveintervals", - cl::desc("Coalesce copies (default=true)"), - cl::init(true)); - - static cl::opt - NewHeuristic("new-coalescer-heuristic", - cl::desc("Use new coalescer heuristic"), - cl::init(false)); - - static cl::opt - ReMatSpillWeight("tweak-remat-spill-weight", - cl::desc("Tweak spill weight of re-materializable intervals"), - cl::init(true)); - - RegisterPass - X("simple-register-coalescing", "Simple Register Coalescing"); - - // Declare that we implement the RegisterCoalescer interface - RegisterAnalysisGroup V(X); -} +static cl::opt +EnableJoining("join-liveintervals", + cl::desc("Coalesce copies (default=true)"), + cl::init(true)); + +static cl::opt +NewHeuristic("new-coalescer-heuristic", + cl::desc("Use new coalescer heuristic"), + cl::init(false), cl::Hidden); + +static cl::opt +CrossClassJoin("join-subclass-copies", + cl::desc("Coalesce copies to sub- register class"), + cl::init(false), cl::Hidden); + +static RegisterPass +X("simple-register-coalescing", "Simple Register Coalescing"); + +// Declare that we implement the RegisterCoalescer interface +static RegisterAnalysisGroup V(X); -const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo(); +const PassInfo *const llvm::SimpleRegisterCoalescingID = &X; void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); + AU.addPreserved(); + AU.addPreservedID(MachineDominatorsID); AU.addPreservedID(PHIEliminationID); AU.addPreservedID(TwoAddressInstructionPassID); - AU.addRequired(); AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); @@ -90,40 +91,45 @@ void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { /// /// This returns true if an interval was modified. /// -bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, - MachineInstr *CopyMI) { +bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, + LiveInterval &IntB, + MachineInstr *CopyMI) { unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); // BValNo is a value number in B that is defined by a copy from A. 'B3' in // the example above. LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); + if (BLR == IntB.end()) // Should never happen! + return false; VNInfo *BValNo = BLR->valno; // Get the location that B is defined at. Two options: either this value has // an unknown definition point or it is defined at CopyIdx. If unknown, we // can't process it. - if (!BValNo->reg) return false; - assert(BValNo->def == CopyIdx && - "Copy doesn't define the value?"); - - // AValNo is the value number in A that defines the copy, A0 in the example. - LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); - VNInfo *AValNo = AValLR->valno; + if (!BValNo->copy) return false; + assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); - // If AValNo is defined as a copy from IntB, we can potentially process this. + // AValNo is the value number in A that defines the copy, A3 in the example. + LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); + if (ALR == IntA.end()) // Should never happen! + return false; + VNInfo *AValNo = ALR->valno; + // If AValNo is defined as a copy from IntB, we can potentially process this. // Get the instruction that defines this value number. - unsigned SrcReg = AValNo->reg; + unsigned SrcReg = li_->getVNInfoSourceReg(AValNo); if (!SrcReg) return false; // Not defined by a copy. // If the value number is not defined by a copy instruction, ignore it. - + // If the source register comes from an interval other than IntB, we can't // handle this. - if (rep(SrcReg) != IntB.reg) return false; + if (SrcReg != IntB.reg) return false; // Get the LiveRange in IntB that this value number starts with. LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1); + if (ValLR == IntB.end()) // Should never happen! + return false; // Make sure that the end of the live range is inside the same block as // CopyMI. @@ -139,24 +145,24 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInte // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(IntB.reg) && - *mri_->getSubRegisters(IntB.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && + *tri_->getSubRegisters(IntB.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } - DOUT << "\nExtending: "; IntB.print(DOUT, mri_); + DOUT << "\nExtending: "; IntB.print(DOUT, tri_); unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; // We are about to delete CopyMI, so need to remove it as the 'instruction // that defines this value #'. Update the the valnum with the new defining // instruction #. - BValNo->def = FillerStart; - BValNo->reg = 0; + BValNo->def = FillerStart; + BValNo->copy = NULL; // Okay, we can merge them. We need to insert a new liverange: // [ValLR.end, BLR.begin) of either value number, then we merge the @@ -165,9 +171,9 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInte // If the IntB live range is assigned to a physical register, and if that // physreg has aliases, - if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) { + for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { LiveInterval &AliasLI = li_->getInterval(*AS); AliasLI.addRange(LiveRange(FillerStart, FillerEnd, AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); @@ -177,7 +183,7 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInte // Okay, merge "B1" into the same value number as "B0". if (BValNo != ValLR->valno) IntB.MergeValueNumberInto(BValNo, ValLR->valno); - DOUT << " result = "; IntB.print(DOUT, mri_); + DOUT << " result = "; IntB.print(DOUT, tri_); DOUT << "\n"; // If the source instruction was killing the source register before the @@ -185,26 +191,245 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInte int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); if (UIdx != -1) ValLREndInst->getOperand(UIdx).setIsKill(false); - - ++numPeep; + + ++numExtends; return true; } -/// AddSubRegIdxPairs - Recursively mark all the registers represented by the -/// specified register as sub-registers. The recursion level is expected to be -/// shallow. -void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx) { - std::vector &JoinedRegs = r2rRevMap_[Reg]; - for (unsigned i = 0, e = JoinedRegs.size(); i != e; ++i) { - SubRegIdxes.push_back(std::make_pair(JoinedRegs[i], SubIdx)); - AddSubRegIdxPairs(JoinedRegs[i], SubIdx); +/// HasOtherReachingDefs - Return true if there are definitions of IntB +/// other than BValNo val# that can reach uses of AValno val# of IntA. +bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA, + LiveInterval &IntB, + VNInfo *AValNo, + VNInfo *BValNo) { + for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); + AI != AE; ++AI) { + if (AI->valno != AValNo) continue; + LiveInterval::Ranges::iterator BI = + std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start); + if (BI != IntB.ranges.begin()) + --BI; + for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { + if (BI->valno == BValNo) + continue; + if (BI->start <= AI->start && BI->end > AI->start) + return true; + if (BI->start > AI->start && BI->start < AI->end) + return true; + } + } + return false; +} + +/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA +/// being the source and IntB being the dest, thus this defines a value number +/// in IntB. If the source value number (in IntA) is defined by a commutable +/// instruction and its other operand is coalesced to the copy dest register, +/// see if we can transform the copy into a noop by commuting the definition. For +/// example, +/// +/// A3 = op A2 B0 +/// ... +/// B1 = A3 <- this copy +/// ... +/// = op A3 <- more uses +/// +/// ==> +/// +/// B2 = op B0 A2 +/// ... +/// B1 = B2 <- now an identify copy +/// ... +/// = op B2 <- more uses +/// +/// This returns true if an interval was modified. +/// +bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, + LiveInterval &IntB, + MachineInstr *CopyMI) { + unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); + + // FIXME: For now, only eliminate the copy by commuting its def when the + // source register is a virtual register. We want to guard against cases + // where the copy is a back edge copy and commuting the def lengthen the + // live interval of the source register to the entire loop. + if (TargetRegisterInfo::isPhysicalRegister(IntA.reg)) + return false; + + // BValNo is a value number in B that is defined by a copy from A. 'B3' in + // the example above. + LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); + if (BLR == IntB.end()) // Should never happen! + return false; + VNInfo *BValNo = BLR->valno; + + // Get the location that B is defined at. Two options: either this value has + // an unknown definition point or it is defined at CopyIdx. If unknown, we + // can't process it. + if (!BValNo->copy) return false; + assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); + + // AValNo is the value number in A that defines the copy, A3 in the example. + LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); + if (ALR == IntA.end()) // Should never happen! + return false; + VNInfo *AValNo = ALR->valno; + // If other defs can reach uses of this def, then it's not safe to perform + // the optimization. + if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill) + return false; + MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); + const TargetInstrDesc &TID = DefMI->getDesc(); + unsigned NewDstIdx; + if (!TID.isCommutable() || + !tii_->CommuteChangesDestination(DefMI, NewDstIdx)) + return false; + + MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); + unsigned NewReg = NewDstMO.getReg(); + if (NewReg != IntB.reg || !NewDstMO.isKill()) + return false; + + // Make sure there are no other definitions of IntB that would reach the + // uses which the new definition can reach. + if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) + return false; + + // If some of the uses of IntA.reg is already coalesced away, return false. + // It's not possible to determine whether it's safe to perform the coalescing. + for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), + UE = mri_->use_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + unsigned UseIdx = li_->getInstructionIndex(UseMI); + LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); + if (ULR == IntA.end()) + continue; + if (ULR->valno == AValNo && JoinedCopies.count(UseMI)) + return false; + } + + // At this point we have decided that it is legal to do this + // transformation. Start by commuting the instruction. + MachineBasicBlock *MBB = DefMI->getParent(); + MachineInstr *NewMI = tii_->commuteInstruction(DefMI); + if (!NewMI) + return false; + if (NewMI != DefMI) { + li_->ReplaceMachineInstrInMaps(DefMI, NewMI); + MBB->insert(DefMI, NewMI); + MBB->erase(DefMI); } + unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); + NewMI->getOperand(OpIdx).setIsKill(); + + bool BHasPHIKill = BValNo->hasPHIKill; + SmallVector BDeadValNos; + SmallVector BKills; + std::map BExtend; + + // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. + // A = or A, B + // ... + // B = A + // ... + // C = A + // ... + // = B + // + // then do not add kills of A to the newly created B interval. + bool Extended = BLR->end > ALR->end && ALR->end != ALR->start; + if (Extended) + BExtend[ALR->end] = BLR->end; + + // Update uses of IntA of the specific Val# with IntB. + for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), + UE = mri_->use_end(); UI != UE;) { + MachineOperand &UseMO = UI.getOperand(); + MachineInstr *UseMI = &*UI; + ++UI; + if (JoinedCopies.count(UseMI)) + continue; + unsigned UseIdx = li_->getInstructionIndex(UseMI); + LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); + if (ULR == IntA.end() || ULR->valno != AValNo) + continue; + UseMO.setReg(NewReg); + if (UseMI == CopyMI) + continue; + if (UseMO.isKill()) { + if (Extended) + UseMO.setIsKill(false); + else + BKills.push_back(li_->getUseIndex(UseIdx)+1); + } + unsigned SrcReg, DstReg; + if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) + continue; + if (DstReg == IntB.reg) { + // This copy will become a noop. If it's defining a new val#, + // remove that val# as well. However this live range is being + // extended to the end of the existing live range defined by the copy. + unsigned DefIdx = li_->getDefIndex(UseIdx); + const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx); + BHasPHIKill |= DLR->valno->hasPHIKill; + assert(DLR->valno->def == DefIdx); + BDeadValNos.push_back(DLR->valno); + BExtend[DLR->start] = DLR->end; + JoinedCopies.insert(UseMI); + // If this is a kill but it's going to be removed, the last use + // of the same val# is the new kill. + if (UseMO.isKill()) + BKills.pop_back(); + } + } + + // We need to insert a new liverange: [ALR.start, LastUse). It may be we can + // simply extend BLR if CopyMI doesn't end the range. + DOUT << "\nExtending: "; IntB.print(DOUT, tri_); + + // Remove val#'s defined by copies that will be coalesced away. + for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) + IntB.removeValNo(BDeadValNos[i]); + + // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition + // is updated. Kills are also updated. + VNInfo *ValNo = BValNo; + ValNo->def = AValNo->def; + ValNo->copy = NULL; + for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) { + unsigned Kill = ValNo->kills[j]; + if (Kill != BLR->end) + BKills.push_back(Kill); + } + ValNo->kills.clear(); + for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); + AI != AE; ++AI) { + if (AI->valno != AValNo) continue; + unsigned End = AI->end; + std::map::iterator EI = BExtend.find(End); + if (EI != BExtend.end()) + End = EI->second; + IntB.addRange(LiveRange(AI->start, End, ValNo)); + } + IntB.addKills(ValNo, BKills); + ValNo->hasPHIKill = BHasPHIKill; + + DOUT << " result = "; IntB.print(DOUT, tri_); + DOUT << "\n"; + + DOUT << "\nShortening: "; IntA.print(DOUT, tri_); + IntA.removeValNo(AValNo); + DOUT << " result = "; IntA.print(DOUT, tri_); + DOUT << "\n"; + + ++numCommutes; + return true; } /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy. /// bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, - unsigned DstReg) { + unsigned DstReg) const { MachineBasicBlock *MBB = CopyMI->getParent(); const MachineLoop *L = loopInfo->getLoopFor(MBB); if (!L) @@ -212,25 +437,434 @@ bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, if (MBB != L->getLoopLatch()) return false; - DstReg = rep(DstReg); LiveInterval &LI = li_->getInterval(DstReg); unsigned DefIdx = li_->getInstructionIndex(CopyMI); LiveInterval::const_iterator DstLR = LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx)); if (DstLR == LI.end()) return false; - unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM-1; - if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0] == KillIdx) + unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1; + if (DstLR->valno->kills.size() == 1 && + DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill) + return true; + return false; +} + +/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and +/// update the subregister number if it is not zero. If DstReg is a +/// physical register and the existing subregister number of the def / use +/// being updated is not zero, make sure to set it to the correct physical +/// subregister. +void +SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, + unsigned SubIdx) { + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); + if (DstIsPhys && SubIdx) { + // Figure out the real physical register we are updating with. + DstReg = tri_->getSubReg(DstReg, SubIdx); + SubIdx = 0; + } + + for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), + E = mri_->reg_end(); I != E; ) { + MachineOperand &O = I.getOperand(); + MachineInstr *UseMI = &*I; + ++I; + unsigned OldSubIdx = O.getSubReg(); + if (DstIsPhys) { + unsigned UseDstReg = DstReg; + if (OldSubIdx) + UseDstReg = tri_->getSubReg(DstReg, OldSubIdx); + O.setReg(UseDstReg); + O.setSubReg(0); + } else { + // Sub-register indexes goes from small to large. e.g. + // RAX: 1 -> AL, 2 -> AX, 3 -> EAX + // EAX: 1 -> AL, 2 -> AX + // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose + // sub-register 2 is also AX. + if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) + assert(OldSubIdx < SubIdx && "Conflicting sub-register index!"); + else if (SubIdx) + O.setSubReg(SubIdx); + // Remove would-be duplicated kill marker. + if (O.isKill() && UseMI->killsRegister(DstReg)) + O.setIsKill(false); + O.setReg(DstReg); + } + } +} + +/// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining" +/// registers due to insert_subreg coalescing. e.g. +/// r1024 = op +/// r1025 = implicit_def +/// r1025 = insert_subreg r1025, r1024 +/// = op r1025 +/// => +/// r1025 = op +/// r1025 = implicit_def +/// r1025 = insert_subreg r1025, r1025 +/// = op r1025 +void +SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) { + for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg), + E = mri_->reg_end(); I != E; ) { + MachineOperand &O = I.getOperand(); + MachineInstr *DefMI = &*I; + ++I; + if (!O.isDef()) + continue; + if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) + continue; + if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI))) + continue; + li_->RemoveMachineInstrFromMaps(DefMI); + DefMI->eraseFromParent(); + } +} + +/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate +/// due to live range lengthening as the result of coalescing. +void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg, + LiveInterval &LI) { + for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), + UE = mri_->use_end(); UI != UE; ++UI) { + MachineOperand &UseMO = UI.getOperand(); + if (UseMO.isKill()) { + MachineInstr *UseMI = UseMO.getParent(); + unsigned SReg, DReg; + if (!tii_->isMoveInstr(*UseMI, SReg, DReg)) + continue; + unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); + if (JoinedCopies.count(UseMI)) + continue; + const LiveRange *UI = LI.getLiveRangeContaining(UseIdx); + if (!LI.isKill(UI->valno, UseIdx+1)) + UseMO.setIsKill(false); + } + } +} + +/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range +/// from a physical register live interval as well as from the live intervals +/// of its sub-registers. +static void removeRange(LiveInterval &li, unsigned Start, unsigned End, + LiveIntervals *li_, const TargetRegisterInfo *tri_) { + li.removeRange(Start, End, true); + if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { + if (!li_->hasInterval(*SR)) + continue; + LiveInterval &sli = li_->getInterval(*SR); + unsigned RemoveEnd = Start; + while (RemoveEnd != End) { + LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start); + if (LR == sli.end()) + break; + RemoveEnd = (LR->end < End) ? LR->end : End; + sli.removeRange(Start, RemoveEnd, true); + Start = RemoveEnd; + } + } + } +} + +/// removeIntervalIfEmpty - Check if the live interval of a physical register +/// is empty, if so remove it and also remove the empty intervals of its +/// sub-registers. Return true if live interval is removed. +static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_, + const TargetRegisterInfo *tri_) { + if (li.empty()) { + if (TargetRegisterInfo::isPhysicalRegister(li.reg)) + for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { + if (!li_->hasInterval(*SR)) + continue; + LiveInterval &sli = li_->getInterval(*SR); + if (sli.empty()) + li_->removeInterval(*SR); + } + li_->removeInterval(li.reg); return true; + } return false; } +/// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy. +/// Return true if live interval is removed. +bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li, + MachineInstr *CopyMI) { + unsigned CopyIdx = li_->getInstructionIndex(CopyMI); + LiveInterval::iterator MLR = + li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx)); + if (MLR == li.end()) + return false; // Already removed by ShortenDeadCopySrcLiveRange. + unsigned RemoveStart = MLR->start; + unsigned RemoveEnd = MLR->end; + // Remove the liverange that's defined by this. + if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) { + removeRange(li, RemoveStart, RemoveEnd, li_, tri_); + return removeIntervalIfEmpty(li, li_, tri_); + } + return false; +} + +/// PropagateDeadness - Propagate the dead marker to the instruction which +/// defines the val#. +static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI, + unsigned &LRStart, LiveIntervals *li_, + const TargetRegisterInfo* tri_) { + MachineInstr *DefMI = + li_->getInstructionFromIndex(li_->getDefIndex(LRStart)); + if (DefMI && DefMI != CopyMI) { + int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_); + if (DeadIdx != -1) { + DefMI->getOperand(DeadIdx).setIsDead(); + // A dead def should have a single cycle interval. + ++LRStart; + } + } +} + +/// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply +/// fallthoughs to SuccMBB. +static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, + MachineBasicBlock *SuccMBB, + const TargetInstrInfo *tii_) { + if (MBB == SuccMBB) + return true; + MachineBasicBlock *TBB = 0, *FBB = 0; + std::vector Cond; + return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && + MBB->isSuccessor(SuccMBB); +} + +/// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially +/// extended by a dead copy. Mark the last use (if any) of the val# as kill as +/// ends the live range there. If there isn't another use, then this live range +/// is dead. Return true if live interval is removed. +bool +SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, + MachineInstr *CopyMI) { + unsigned CopyIdx = li_->getInstructionIndex(CopyMI); + if (CopyIdx == 0) { + // FIXME: special case: function live in. It can be a general case if the + // first instruction index starts at > 0 value. + assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); + // Live-in to the function but dead. Remove it from entry live-in set. + if (mf_->begin()->isLiveIn(li.reg)) + mf_->begin()->removeLiveIn(li.reg); + const LiveRange *LR = li.getLiveRangeContaining(CopyIdx); + removeRange(li, LR->start, LR->end, li_, tri_); + return removeIntervalIfEmpty(li, li_, tri_); + } + + LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1); + if (LR == li.end()) + // Livein but defined by a phi. + return false; + + unsigned RemoveStart = LR->start; + unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1; + if (LR->end > RemoveEnd) + // More uses past this copy? Nothing to do. + return false; + + MachineBasicBlock *CopyMBB = CopyMI->getParent(); + unsigned MBBStart = li_->getMBBStartIdx(CopyMBB); + unsigned LastUseIdx; + MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg, + LastUseIdx); + if (LastUse) { + MachineInstr *LastUseMI = LastUse->getParent(); + if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) { + // r1024 = op + // ... + // BB1: + // = r1024 + // + // BB2: + // r1025 = r1024 + if (MBBStart < LR->end) + removeRange(li, MBBStart, LR->end, li_, tri_); + return false; + } + + // There are uses before the copy, just shorten the live range to the end + // of last use. + LastUse->setIsKill(); + removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); + unsigned SrcReg, DstReg; + if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) && + DstReg == li.reg) { + // Last use is itself an identity code. + int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); + LastUseMI->getOperand(DeadIdx).setIsDead(); + } + return false; + } + + // Is it livein? + if (LR->start <= MBBStart && LR->end > MBBStart) { + if (LR->start == 0) { + assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); + // Live-in to the function but dead. Remove it from entry live-in set. + mf_->begin()->removeLiveIn(li.reg); + } + // FIXME: Shorten intervals in BBs that reaches this BB. + } + + if (LR->valno->def == RemoveStart) + // If the def MI defines the val#, propagate the dead marker. + PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); + + removeRange(li, RemoveStart, LR->end, li_, tri_); + return removeIntervalIfEmpty(li, li_, tri_); +} + +/// CanCoalesceWithImpDef - Returns true if the specified copy instruction +/// from an implicit def to another register can be coalesced away. +bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI, + LiveInterval &li, + LiveInterval &ImpLi) const{ + if (!CopyMI->killsRegister(ImpLi.reg)) + return false; + unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); + LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx); + if (LR == li.end()) + return false; + if (LR->valno->hasPHIKill) + return false; + if (LR->valno->def != CopyIdx) + return false; + // Make sure all of val# uses are copies. + for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg), + UE = mri_->use_end(); UI != UE;) { + MachineInstr *UseMI = &*UI; + ++UI; + if (JoinedCopies.count(UseMI)) + continue; + unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); + LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx); + if (ULR == li.end() || ULR->valno != LR->valno) + continue; + // If the use is not a use, then it's not safe to coalesce the move. + unsigned SrcReg, DstReg; + if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) { + if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG && + UseMI->getOperand(1).getReg() == li.reg) + continue; + return false; + } + } + return true; +} + + +/// RemoveCopiesFromValNo - The specified value# is defined by an implicit +/// def and it is being removed. Turn all copies from this value# into +/// identity copies so they will be removed. +void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li, + VNInfo *VNI) { + SmallVector ImpDefs; + MachineOperand *LastUse = NULL; + unsigned LastUseIdx = li_->getUseIndex(VNI->def); + for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg), + RE = mri_->reg_end(); RI != RE;) { + MachineOperand *MO = &RI.getOperand(); + MachineInstr *MI = &*RI; + ++RI; + if (MO->isDef()) { + if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { + ImpDefs.push_back(MI); + } + continue; + } + if (JoinedCopies.count(MI)) + continue; + unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI)); + LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx); + if (ULR == li.end() || ULR->valno != VNI) + continue; + // If the use is a copy, turn it into an identity copy. + unsigned SrcReg, DstReg; + if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) { + // Each use MI may have multiple uses of this register. Change them all. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg() && MO.getReg() == li.reg) + MO.setReg(DstReg); + } + JoinedCopies.insert(MI); + } else if (UseIdx > LastUseIdx) { + LastUseIdx = UseIdx; + LastUse = MO; + } + } + if (LastUse) + LastUse->setIsKill(); + else { + // Remove dead implicit_def's. + while (!ImpDefs.empty()) { + MachineInstr *ImpDef = ImpDefs.back(); + ImpDefs.pop_back(); + li_->RemoveMachineInstrFromMaps(ImpDef); + ImpDef->eraseFromParent(); + } + } +} + +static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo* TRI) { + for (const unsigned *SRs = TRI->getSuperRegisters(Reg); + unsigned SR = *SRs; ++SRs) + if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR)) + return SR; + return 0; +} + +/// isProfitableToCoalesceToSubRC - Given that register class of DstReg is +/// a subset of the register class of SrcReg, return true if it's profitable +/// to coalesce the two registers. +bool +SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg, + unsigned DstReg, + MachineBasicBlock *MBB){ + if (!CrossClassJoin) + return false; + + // First let's make sure all uses are in the same MBB. + for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg), + RE = mri_->reg_end(); RI != RE; ++RI) { + MachineInstr &MI = *RI; + if (MI.getParent() != MBB) + return false; + } + for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg), + RE = mri_->reg_end(); RI != RE; ++RI) { + MachineInstr &MI = *RI; + if (MI.getParent() != MBB) + return false; + } + + // Then make sure the intervals are *short*. + LiveInterval &SrcInt = li_->getInterval(SrcReg); + LiveInterval &DstInt = li_->getInterval(DstReg); + unsigned SrcSize = SrcInt.getSize() / InstrSlots::NUM; + unsigned DstSize = DstInt.getSize() / InstrSlots::NUM; + const TargetRegisterClass *RC = mri_->getRegClass(DstReg); + unsigned Threshold = allocatableRCRegs_[RC].count() * 2; + return (SrcSize + DstSize) <= Threshold; +} + + /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, /// which are the src/dst of the copy instruction CopyMI. This returns true /// if the copy was successfully coalesced away. If it is not currently /// possible to coalesce this interval, but it may be possible if other /// things get coalesced, then it returns true by reference in 'Again'. -bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { +bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { MachineInstr *CopyMI = TheCopy.MI; Again = false; @@ -239,20 +873,35 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI; - // Get representative registers. - unsigned SrcReg = TheCopy.SrcReg; - unsigned DstReg = TheCopy.DstReg; - unsigned repSrcReg = rep(SrcReg); - unsigned repDstReg = rep(DstReg); - + unsigned SrcReg; + unsigned DstReg; + bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; + bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG; + unsigned SubIdx = 0; + if (isExtSubReg) { + DstReg = CopyMI->getOperand(0).getReg(); + SrcReg = CopyMI->getOperand(1).getReg(); + } else if (isInsSubReg) { + if (CopyMI->getOperand(2).getSubReg()) { + DOUT << "\tSource of insert_subreg is already coalesced " + << "to another register.\n"; + return false; // Not coalescable. + } + DstReg = CopyMI->getOperand(0).getReg(); + SrcReg = CopyMI->getOperand(2).getReg(); + } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { + assert(0 && "Unrecognized copy instruction!"); + return false; + } + // If they are already joined we continue. - if (repSrcReg == repDstReg) { + if (SrcReg == DstReg) { DOUT << "\tCopy already coalesced.\n"; return false; // Not coalescable. } - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); // If they are both physical registers, we cannot join them. if (SrcIsPhys && DstIsPhys) { @@ -261,197 +910,216 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { } // We only join virtual registers with allocatable physical registers. - if (SrcIsPhys && !allocatableRegs_[repSrcReg]) { + if (SrcIsPhys && !allocatableRegs_[SrcReg]) { DOUT << "\tSrc reg is unallocatable physreg.\n"; return false; // Not coalescable. } - if (DstIsPhys && !allocatableRegs_[repDstReg]) { + if (DstIsPhys && !allocatableRegs_[DstReg]) { DOUT << "\tDst reg is unallocatable physreg.\n"; return false; // Not coalescable. } - bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; + // Should be non-null only when coalescing to a sub-register class. + const TargetRegisterClass *SubRC = NULL; + MachineBasicBlock *CopyMBB = CopyMI->getParent(); unsigned RealDstReg = 0; - if (isExtSubReg) { - unsigned SubIdx = CopyMI->getOperand(2).getImm(); - if (SrcIsPhys) + unsigned RealSrcReg = 0; + if (isExtSubReg || isInsSubReg) { + SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm(); + if (SrcIsPhys && isExtSubReg) { // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be // coalesced with AX. - repSrcReg = mri_->getSubReg(repSrcReg, SubIdx); - else if (DstIsPhys) { + unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg(); + if (DstSubIdx) { + // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been + // coalesced to a larger register so the subreg indices cancel out. + if (DstSubIdx != SubIdx) { + DOUT << "\t Sub-register indices mismatch.\n"; + return false; // Not coalescable. + } + } else + SrcReg = tri_->getSubReg(SrcReg, SubIdx); + SubIdx = 0; + } else if (DstIsPhys && isInsSubReg) { + // EAX = INSERT_SUBREG EAX, r1024, 0 + unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg(); + if (SrcSubIdx) { + // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been + // coalesced to a larger register so the subreg indices cancel out. + if (SrcSubIdx != SubIdx) { + DOUT << "\t Sub-register indices mismatch.\n"; + return false; // Not coalescable. + } + } else + DstReg = tri_->getSubReg(DstReg, SubIdx); + SubIdx = 0; + } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) { // If this is a extract_subreg where dst is a physical register, e.g. // cl = EXTRACT_SUBREG reg1024, 1 // then create and update the actual physical register allocated to RHS. - const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg); - for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg); - unsigned SR = *SRs; ++SRs) { - if (repDstReg == mri_->getSubReg(SR, SubIdx) && - RC->contains(SR)) { - RealDstReg = SR; - break; - } + // Ditto for + // reg1024 = INSERT_SUBREG r1024, cl, 1 + if (CopyMI->getOperand(1).getSubReg()) { + DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg" + << " of a super-class.\n"; + return false; // Not coalescable. + } + const TargetRegisterClass *RC = + mri_->getRegClass(isExtSubReg ? SrcReg : DstReg); + if (isExtSubReg) { + RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_); + assert(RealDstReg && "Invalid extra_subreg instruction!"); + } else { + RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_); + assert(RealSrcReg && "Invalid extra_subreg instruction!"); } - assert(RealDstReg && "Invalid extra_subreg instruction!"); // For this type of EXTRACT_SUBREG, conservatively // check if the live interval of the source register interfere with the // actual super physical register we are trying to coalesce with. - LiveInterval &RHS = li_->getInterval(repSrcReg); - if (li_->hasInterval(RealDstReg) && - RHS.overlaps(li_->getInterval(RealDstReg))) { + unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg; + LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg); + if (li_->hasInterval(PhysReg) && + RHS.overlaps(li_->getInterval(PhysReg))) { DOUT << "Interfere with register "; - DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_)); + DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_)); return false; // Not coalescable } - for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR) + for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; // Not coalescable } + SubIdx = 0; } else { - unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM; - unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM; - const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repDstReg); - unsigned Threshold = allocatableRCRegs_[RC].count(); - // Be conservative. If both sides are virtual registers, do not coalesce - // if this will cause a high use density interval to target a smaller set - // of registers. - if (DstSize > Threshold || SrcSize > Threshold) { - LiveVariables::VarInfo &svi = lv_->getVarInfo(repSrcReg); - LiveVariables::VarInfo &dvi = lv_->getVarInfo(repDstReg); - if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) { - Again = true; // May be possible to coalesce later. - return false; + unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg() + : CopyMI->getOperand(2).getSubReg(); + if (OldSubIdx) { + if (OldSubIdx == SubIdx && + !differingRegisterClasses(SrcReg, DstReg, SubRC)) + // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been + // coalesced to a larger register so the subreg indices cancel out. + // Also check if the other larger register is of the same register + // class as the would be resulting register. + SubIdx = 0; + else { + DOUT << "\t Sub-register indices mismatch.\n"; + return false; // Not coalescable. + } + } + if (SubIdx) { + unsigned LargeReg = isExtSubReg ? SrcReg : DstReg; + unsigned SmallReg = isExtSubReg ? DstReg : SrcReg; + unsigned LargeRegSize = + li_->getInterval(LargeReg).getSize() / InstrSlots::NUM; + unsigned SmallRegSize = + li_->getInterval(SmallReg).getSize() / InstrSlots::NUM; + const TargetRegisterClass *RC = mri_->getRegClass(SmallReg); + unsigned Threshold = allocatableRCRegs_[RC].count(); + // Be conservative. If both sides are virtual registers, do not coalesce + // if this will cause a high use density interval to target a smaller + // set of registers. + if (SmallRegSize > Threshold || LargeRegSize > Threshold) { + if ((float)std::distance(mri_->use_begin(SmallReg), + mri_->use_end()) / SmallRegSize < + (float)std::distance(mri_->use_begin(LargeReg), + mri_->use_end()) / LargeRegSize) { + Again = true; // May be possible to coalesce later. + return false; + } } } } - } else if (differingRegisterClasses(repSrcReg, repDstReg)) { - // If they are not of the same register class, we cannot join them. - DOUT << "\tSrc/Dest are different register classes.\n"; - // Allow the coalescer to try again in case either side gets coalesced to - // a physical register that's compatible with the other side. e.g. - // r1024 = MOV32to32_ r1025 - // but later r1024 is assigned EAX then r1025 may be coalesced with EAX. - Again = true; // May be possible to coalesce later. - return false; + } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) { + // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced + // with another? If it's the resulting destination register, then + // the subidx must be propagated to uses (but only those defined + // by the EXTRACT_SUBREG). If it's being coalesced into another + // register, it should be safe because register is assumed to have + // the register class of the super-register. + + if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) { + // If they are not of the same register class, we cannot join them. + DOUT << "\tSrc/Dest are different register classes.\n"; + // Allow the coalescer to try again in case either side gets coalesced to + // a physical register that's compatible with the other side. e.g. + // r1024 = MOV32to32_ r1025 + // but later r1024 is assigned EAX then r1025 may be coalesced with EAX. + Again = true; // May be possible to coalesce later. + return false; + } } - LiveInterval &SrcInt = li_->getInterval(repSrcReg); - LiveInterval &DstInt = li_->getInterval(repDstReg); - assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg && + LiveInterval &SrcInt = li_->getInterval(SrcReg); + LiveInterval &DstInt = li_->getInterval(DstReg); + assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg && "Register mapping is horribly broken!"); - DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); - DOUT << " and "; DstInt.print(DOUT, mri_); + DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); + DOUT << " and "; DstInt.print(DOUT, tri_); DOUT << ": "; - // Check if it is necessary to propagate "isDead" property before intervals - // are joined. - MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg); - bool isDead = mopd->isDead(); - bool isShorten = false; - unsigned SrcStart = 0, RemoveStart = 0; - unsigned SrcEnd = 0, RemoveEnd = 0; - if (isDead) { - unsigned CopyIdx = li_->getInstructionIndex(CopyMI); - LiveInterval::iterator SrcLR = - SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx)); - RemoveStart = SrcStart = SrcLR->start; - RemoveEnd = SrcEnd = SrcLR->end; - // The instruction which defines the src is only truly dead if there are - // no intermediate uses and there isn't a use beyond the copy. - // FIXME: find the last use, mark is kill and shorten the live range. - if (SrcEnd > li_->getDefIndex(CopyIdx)) { - isDead = false; - } else { - MachineOperand *MOU; - MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU); - if (LastUse) { - // Shorten the liveinterval to the end of last use. - MOU->setIsKill(); - isDead = false; - isShorten = true; - RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse)); - RemoveEnd = SrcEnd; - } else { - MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); - if (SrcMI) { - MachineOperand *mops = findDefOperand(SrcMI, repSrcReg); - if (mops) - // A dead def should have a single cycle interval. - ++RemoveStart; - } + // Check if it is necessary to propagate "isDead" property. + if (!isExtSubReg && !isInsSubReg) { + MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); + bool isDead = mopd->isDead(); + + // We need to be careful about coalescing a source physical register with a + // virtual register. Once the coalescing is done, it cannot be broken and + // these are not spillable! If the destination interval uses are far away, + // think twice about coalescing them! + if (!isDead && (SrcIsPhys || DstIsPhys)) { + LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; + unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg; + unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg; + const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg); + unsigned Threshold = allocatableRCRegs_[RC].count() * 2; + if (TheCopy.isBackEdge) + Threshold *= 2; // Favors back edge copies. + + // If the virtual register live interval is long but it has low use desity, + // do not join them, instead mark the physical register as its allocation + // preference. + unsigned Length = JoinVInt.getSize() / InstrSlots::NUM; + if (Length > Threshold && + (((float)std::distance(mri_->use_begin(JoinVReg), + mri_->use_end()) / Length) < (1.0 / Threshold))) { + JoinVInt.preference = JoinPReg; + ++numAborts; + DOUT << "\tMay tie down a physical register, abort!\n"; + Again = true; // May be possible to coalesce later. + return false; } } } - // We need to be careful about coalescing a source physical register with a - // virtual register. Once the coalescing is done, it cannot be broken and - // these are not spillable! If the destination interval uses are far away, - // think twice about coalescing them! - if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) { - LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; - unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg; - unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg; - const TargetRegisterClass *RC = mf_->getRegInfo().getRegClass(JoinVReg); - unsigned Threshold = allocatableRCRegs_[RC].count() * 2; - if (TheCopy.isBackEdge) - Threshold *= 2; // Favors back edge copies. - - // If the virtual register live interval is long but it has low use desity, - // do not join them, instead mark the physical register as its allocation - // preference. - unsigned Length = JoinVInt.getSize() / InstrSlots::NUM; - LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg); - if (Length > Threshold && - (((float)vi.NumUses / Length) < (1.0 / Threshold))) { - JoinVInt.preference = JoinPReg; - ++numAborts; - DOUT << "\tMay tie down a physical register, abort!\n"; - Again = true; // May be possible to coalesce later. - return false; - } - } - // Okay, attempt to join these two intervals. On failure, this returns false. // Otherwise, if one of the intervals being joined is a physreg, this method // always canonicalizes DstInt to be it. The output "SrcInt" will not have // been modified, so we can use this information below to update aliases. bool Swapped = false; - if (JoinIntervals(DstInt, SrcInt, Swapped)) { - if (isDead) { - // Result of the copy is dead. Propagate this property. - if (SrcStart == 0) { - assert(MRegisterInfo::isPhysicalRegister(repSrcReg) && - "Live-in must be a physical register!"); - // Live-in to the function but dead. Remove it from entry live-in set. - // JoinIntervals may end up swapping the two intervals. - mf_->begin()->removeLiveIn(repSrcReg); - } else { - MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); - if (SrcMI) { - MachineOperand *mops = findDefOperand(SrcMI, repSrcReg); - if (mops) - mops->setIsDead(); - } - } - } + // If SrcInt is implicitly defined, it's safe to coalesce. + bool isEmpty = SrcInt.empty(); + if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) { + // Only coalesce an empty interval (defined by implicit_def) with + // another interval which has a valno defined by the CopyMI and the CopyMI + // is a kill of the implicit def. + DOUT << "Not profitable!\n"; + return false; + } - if (isShorten || isDead) { - // Shorten the destination live interval. - if (Swapped) - SrcInt.removeRange(RemoveStart, RemoveEnd); - } - } else { + if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) { // Coalescing failed. // If we can eliminate the copy without merging the live ranges, do so now. - if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI)) { + if (!isExtSubReg && !isInsSubReg && + (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) || + RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) { JoinedCopies.insert(CopyMI); return true; } - + // Otherwise, we are unable to join the intervals. DOUT << "Interference!\n"; Again = true; // May be possible to coalesce later. @@ -461,103 +1129,129 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { LiveInterval *ResSrcInt = &SrcInt; LiveInterval *ResDstInt = &DstInt; if (Swapped) { - std::swap(repSrcReg, repDstReg); + std::swap(SrcReg, DstReg); std::swap(ResSrcInt, ResDstInt); } - assert(MRegisterInfo::isVirtualRegister(repSrcReg) && + assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && "LiveInterval::join didn't work right!"); // If we're about to merge live ranges into a physical register live range, // we have to update any aliased register's live ranges to indicate that they // have clobbered values for this range. - if (MRegisterInfo::isPhysicalRegister(repDstReg)) { - // Unset unnecessary kills. - if (!ResDstInt->containsOneValue()) { - for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(), - E = ResSrcInt->end(); I != E; ++I) - unsetRegisterKills(I->start, I->end, repDstReg); - } - + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { // If this is a extract_subreg where dst is a physical register, e.g. // cl = EXTRACT_SUBREG reg1024, 1 // then create and update the actual physical register allocated to RHS. - if (RealDstReg) { - LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg); + if (RealDstReg || RealSrcReg) { + LiveInterval &RealInt = + li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg); SmallSet CopiedValNos; for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(), E = ResSrcInt->ranges.end(); I != E; ++I) { - LiveInterval::const_iterator DstLR = - ResDstInt->FindLiveRangeContaining(I->start); - assert(DstLR != ResDstInt->end() && "Invalid joined interval!"); + const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start); + assert(DstLR && "Invalid joined interval!"); const VNInfo *DstValNo = DstLR->valno; if (CopiedValNos.insert(DstValNo)) { - VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg, - li_->getVNInfoAllocator()); + VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy, + li_->getVNInfoAllocator()); ValNo->hasPHIKill = DstValNo->hasPHIKill; - RealDstInt.addKills(ValNo, DstValNo->kills); - RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); + RealInt.addKills(ValNo, DstValNo->kills); + RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); } } - repDstReg = RealDstReg; + + DstReg = RealDstReg ? RealDstReg : RealSrcReg; } // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS) + for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, li_->getVNInfoAllocator()); - } else { - // Merge use info if the destination is a virtual register. - LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg); - LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg); - dVI.NumUses += sVI.NumUses; } - // Remember these liveintervals have been joined. - JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister); - if (MRegisterInfo::isVirtualRegister(repDstReg)) - JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister); - - if (isExtSubReg && !SrcIsPhys && !DstIsPhys) { - if (!Swapped) { - // Make sure we allocate the larger super-register. + // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the + // larger super-register. + if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) { + if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) { ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator()); - std::swap(repSrcReg, repDstReg); + std::swap(SrcReg, DstReg); std::swap(ResSrcInt, ResDstInt); } - unsigned SubIdx = CopyMI->getOperand(2).getImm(); - SubRegIdxes.push_back(std::make_pair(repSrcReg, SubIdx)); - AddSubRegIdxPairs(repSrcReg, SubIdx); + } + + // Coalescing to a virtual register that is of a sub-register class of the + // other. Make sure the resulting register is set to the right register class. + if (SubRC) { + mri_->setRegClass(DstReg, SubRC); + ++numSubJoins; } if (NewHeuristic) { + // Add all copies that define val# in the source interval into the queue. for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(), e = ResSrcInt->vni_end(); i != e; ++i) { const VNInfo *vni = *i; - if (vni->def && vni->def != ~1U && vni->def != ~0U) { - MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); - unsigned SrcReg, DstReg; - if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) && - JoinedCopies.count(CopyMI) == 0) { - unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent()); - JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth, - isBackEdgeCopy(CopyMI, DstReg))); - } + if (!vni->def || vni->def == ~1U || vni->def == ~0U) + continue; + MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); + unsigned NewSrcReg, NewDstReg; + if (CopyMI && + JoinedCopies.count(CopyMI) == 0 && + tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) { + unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB); + JoinQueue->push(CopyRec(CopyMI, LoopDepth, + isBackEdgeCopy(CopyMI, DstReg))); } } } - DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_); - DOUT << "\n"; + // Remember to delete the copy instruction. + JoinedCopies.insert(CopyMI); + + // Some live range has been lengthened due to colaescing, eliminate the + // unnecessary kills. + RemoveUnnecessaryKills(SrcReg, *ResDstInt); + if (TargetRegisterInfo::isVirtualRegister(DstReg)) + RemoveUnnecessaryKills(DstReg, *ResDstInt); - // repSrcReg is guarateed to be the register whose live interval that is + // SrcReg is guarateed to be the register whose live interval that is // being merged. - li_->removeInterval(repSrcReg); - r2rMap_[repSrcReg] = repDstReg; - r2rRevMap_[repDstReg].push_back(repSrcReg); + li_->removeInterval(SrcReg); + if (isInsSubReg) + // Avoid: + // r1024 = op + // r1024 = implicit_def + // ... + // = r1024 + RemoveDeadImpDef(DstReg, *ResDstInt); + UpdateRegDefsUses(SrcReg, DstReg, SubIdx); + + if (isEmpty) { + // Now the copy is being coalesced away, the val# previously defined + // by the copy is being defined by an IMPLICIT_DEF which defines a zero + // length interval. Remove the val#. + unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); + const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx); + VNInfo *ImpVal = LR->valno; + assert(ImpVal->def == CopyIdx); + unsigned NextDef = LR->end; + RemoveCopiesFromValNo(*ResDstInt, ImpVal); + ResDstInt->removeValNo(ImpVal); + LR = ResDstInt->FindLiveRangeContaining(NextDef); + if (LR != ResDstInt->end() && LR->valno->def == NextDef) { + // Special case: vr1024 = implicit_def + // vr1024 = insert_subreg vr1024, vr1025, c + // The insert_subreg becomes a "copy" that defines a val# which can itself + // be coalesced away. + MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef); + if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) + LR->valno->copy = DefMI; + } + } + + DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); + DOUT << "\n"; - // Finally, delete the copy instruction. - JoinedCopies.insert(CopyMI); - ++numPeep; ++numJoins; return true; } @@ -617,12 +1311,39 @@ static bool InVector(VNInfo *Val, const SmallVector &V) { return std::find(V.begin(), V.end(), Val) != V.end(); } +/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of +/// the specified live interval is defined by a copy from the specified +/// register. +bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li, + LiveRange *LR, + unsigned Reg) { + unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno); + if (SrcReg == Reg) + return true; + if (LR->valno->def == ~0U && + TargetRegisterInfo::isPhysicalRegister(li.reg) && + *tri_->getSuperRegisters(li.reg)) { + // It's a sub-register live interval, we may not have precise information. + // Re-compute it. + MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start); + unsigned SrcReg, DstReg; + if (tii_->isMoveInstr(*DefMI, SrcReg, DstReg) && + DstReg == li.reg && SrcReg == Reg) { + // Cache computed info. + LR->valno->def = LR->start; + LR->valno->copy = DefMI; + return true; + } + } + return false; +} + /// SimpleJoin - Attempt to joint the specified interval into this one. The /// caller of this method must guarantee that the RHS only contains a single /// value number and that the RHS is not defined by a copy from this /// interval. This returns false if the intervals are not joinable, or it /// joins them and returns true. -bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { +bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ assert(RHS.containsOneValue()); // Some number (potentially more than one) value numbers in the current @@ -660,10 +1381,22 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) // If we haven't already recorded that this value # is safe, check it. if (!InVector(LHSIt->valno, EliminatedLHSVals)) { // Copy from the RHS? - unsigned SrcReg = LHSIt->valno->reg; - if (rep(SrcReg) != RHS.reg) + if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) return false; // Nope, bail out. - + + if (LHSIt->contains(RHSIt->valno->def)) + // Here is an interesting situation: + // BB1: + // vr1025 = copy vr1024 + // .. + // BB2: + // vr1024 = op + // = vr1025 + // Even though vr1025 is copied from vr1024, it's not safe to + // coalesced them since live range of vr1025 intersects the + // def of vr1024. This happens because vr1025 is assigned the + // value of the previous iteration of vr1024. + return false; EliminatedLHSVals.push_back(LHSIt->valno); } @@ -688,7 +1421,20 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) } else { // Otherwise, if this is a copy from the RHS, mark it as being merged // in. - if (rep(LHSIt->valno->reg) == RHS.reg) { + if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) { + if (LHSIt->contains(RHSIt->valno->def)) + // Here is an interesting situation: + // BB1: + // vr1025 = copy vr1024 + // .. + // BB2: + // vr1024 = op + // = vr1025 + // Even though vr1025 is copied from vr1024, it's not safe to + // coalesced them since live range of vr1025 intersects the + // def of vr1024. This happens because vr1025 is assigned the + // value of the previous iteration of vr1024. + return false; EliminatedLHSVals.push_back(LHSIt->valno); // We know this entire LHS live range is okay, so skip it now. @@ -723,8 +1469,13 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) } } LHSValNo = Smallest; + } else if (EliminatedLHSVals.empty()) { + if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && + *tri_->getSuperRegisters(LHS.reg)) + // Imprecise sub-register information. Can't handle it. + return false; + assert(0 && "No copies from the RHS?"); } else { - assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); LHSValNo = EliminatedLHSVals[0]; } @@ -732,8 +1483,8 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) // RHS into, update the value number info for the LHS to indicate that the // value number is defined where the RHS value number was. const VNInfo *VNI = RHS.getValNumInfo(0); - LHSValNo->def = VNI->def; - LHSValNo->reg = VNI->reg; + LHSValNo->def = VNI->def; + LHSValNo->copy = VNI->copy; // Okay, the final step is to loop over the RHS live intervals, adding them to // the LHS. @@ -765,20 +1516,20 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(LHS.reg) && - *mri_->getSubRegisters(LHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && + *tri_->getSubRegisters(LHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } - } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) && - *mri_->getSubRegisters(RHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR) + } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && + *tri_->getSubRegisters(RHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } @@ -794,12 +1545,12 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, int RHSValID = -1; VNInfo *RHSValNoInfo = NULL; VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0); - unsigned RHSSrcReg = RHSValNoInfo0->reg; - if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { + unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0); + if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) { // If RHS is not defined as a copy from the LHS, we can use simpler and // faster checks to see if the live ranges are coalescable. This joiner // can't swap the LHS/RHS intervals though. - if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { + if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { return SimpleJoin(LHS, RHS); } else { RHSValNoInfo = RHSValNoInfo0; @@ -821,8 +1572,8 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, i != e; ++i) { VNInfo *VNI = *i; unsigned VN = VNI->id; - if (unsigned LHSSrcReg = VNI->reg) { - if (rep(LHSSrcReg) != RHS.reg) { + if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) { + if (LHSSrcReg != RHS.reg) { // If this is not a copy from the RHS, its value number will be // unmodified by the coalescing. NewVNInfo[VN] = VNI; @@ -860,17 +1611,16 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); i != e; ++i) { VNInfo *VNI = *i; - unsigned ValSrcReg = VNI->reg; - if (VNI->def == ~1U ||ValSrcReg == 0) // Src not defined by a copy? + if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? continue; // DstReg is known to be a register in the LHS interval. If the src is // from the RHS interval, we can use its value #. - if (rep(ValSrcReg) != RHS.reg) + if (li_->getVNInfoSourceReg(VNI) != RHS.reg) continue; // Figure out the value # from the RHS. - LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno; + LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno; } // Loop over the value numbers of the RHS, seeing if any are defined from @@ -878,17 +1628,16 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); i != e; ++i) { VNInfo *VNI = *i; - unsigned ValSrcReg = VNI->reg; - if (VNI->def == ~1U || ValSrcReg == 0) // Src not defined by a copy? + if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? continue; // DstReg is known to be a register in the RHS interval. If the src is // from the LHS interval, we can use its value #. - if (rep(ValSrcReg) != LHS.reg) + if (li_->getVNInfoSourceReg(VNI) != LHS.reg) continue; // Figure out the value # from the LHS. - RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno; + RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno; } LHSValNoAssignments.resize(LHS.getNumValNums(), -1); @@ -990,8 +1739,8 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, // If we get here, we know that we can coalesce the live ranges. Ask the // intervals to coalesce themselves now. if ((RHS.ranges.size() > LHS.ranges.size() && - MRegisterInfo::isVirtualRegister(LHS.reg)) || - MRegisterInfo::isPhysicalRegister(RHS.reg)) { + TargetRegisterInfo::isVirtualRegister(LHS.reg)) || + TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); Swapped = true; } else { @@ -1027,39 +1776,9 @@ bool CopyRecSort::operator()(CopyRec left, CopyRec right) const { // Inner loops first. if (left.LoopDepth > right.LoopDepth) return false; - else if (left.LoopDepth == right.LoopDepth) { + else if (left.LoopDepth == right.LoopDepth) if (left.isBackEdge && !right.isBackEdge) return false; - else if (left.isBackEdge == right.isBackEdge) { - // Join virtuals to physical registers first. - bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg); - bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg); - bool LIsPhys = LDstIsPhys || LSrcIsPhys; - bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg); - bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg); - bool RIsPhys = RDstIsPhys || RSrcIsPhys; - if (LIsPhys && !RIsPhys) - return false; - else if (LIsPhys == RIsPhys) { - // Join shorter intervals first. - unsigned LSize = 0; - unsigned RSize = 0; - if (LIsPhys) { - LSize = LDstIsPhys ? 0 : JPQ->getRepIntervalSize(left.DstReg); - LSize += LSrcIsPhys ? 0 : JPQ->getRepIntervalSize(left.SrcReg); - RSize = RDstIsPhys ? 0 : JPQ->getRepIntervalSize(right.DstReg); - RSize += RSrcIsPhys ? 0 : JPQ->getRepIntervalSize(right.SrcReg); - } else { - LSize = std::min(JPQ->getRepIntervalSize(left.DstReg), - JPQ->getRepIntervalSize(left.SrcReg)); - RSize = std::min(JPQ->getRepIntervalSize(right.DstReg), - JPQ->getRepIntervalSize(right.SrcReg)); - } - if (LSize < RSize) - return false; - } - } - } return true; } @@ -1069,6 +1788,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, std::vector VirtCopies; std::vector PhysCopies; + std::vector ImpDefCopies; unsigned LoopDepth = loopInfo->getLoopDepth(MBB); for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); MII != E;) { @@ -1079,28 +1799,39 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(1).getReg(); + } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { + DstReg = Inst->getOperand(0).getReg(); + SrcReg = Inst->getOperand(2).getReg(); } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; - unsigned repSrcReg = rep(SrcReg); - unsigned repDstReg = rep(DstReg); - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); if (NewHeuristic) { - JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth, - isBackEdgeCopy(Inst, DstReg))); + JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg))); } else { - if (SrcIsPhys || DstIsPhys) - PhysCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false)); + if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()) + ImpDefCopies.push_back(CopyRec(Inst, 0, false)); + else if (SrcIsPhys || DstIsPhys) + PhysCopies.push_back(CopyRec(Inst, 0, false)); else - VirtCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false)); + VirtCopies.push_back(CopyRec(Inst, 0, false)); } } if (NewHeuristic) return; - // Try coalescing physical register + virtual register first. + // Try coalescing implicit copies first, followed by copies to / from + // physical registers, then finally copies from virtual registers to + // virtual registers. + for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) { + CopyRec &TheCopy = ImpDefCopies[i]; + bool Again = false; + if (!JoinCopy(TheCopy, Again)) + if (Again) + TryAgain.push_back(TheCopy); + } for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) { CopyRec &TheCopy = PhysCopies[i]; bool Again = false; @@ -1123,9 +1854,6 @@ void SimpleRegisterCoalescing::joinIntervals() { if (NewHeuristic) JoinQueue = new JoinPriorityQueue(this); - JoinedLIs.resize(li_->getNumIntervals()); - JoinedLIs.reset(); - std::vector TryAgainList; if (loopInfo->begin() == loopInfo->end()) { // If there are no loops in the function, join intervals in function order. @@ -1196,120 +1924,63 @@ void SimpleRegisterCoalescing::joinIntervals() { } } - // Some live range has been lengthened due to colaescing, eliminate the - // unnecessary kills. - int RegNum = JoinedLIs.find_first(); - while (RegNum != -1) { - unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister; - unsigned repReg = rep(Reg); - LiveInterval &LI = li_->getInterval(repReg); - LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg); - for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) { - MachineInstr *Kill = svi.Kills[i]; - // Suppose vr1 = op vr2, x - // and vr1 and vr2 are coalesced. vr2 should still be marked kill - // unless it is a two-address operand. - if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg)) - continue; - if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM)) - unsetRegisterKill(Kill, repReg); - } - RegNum = JoinedLIs.find_next(RegNum); - } - if (NewHeuristic) - delete JoinQueue; - - DOUT << "*** Register mapping ***\n"; - for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i) - if (r2rMap_[i]) { - DOUT << " reg " << i << " -> "; - DEBUG(printRegName(r2rMap_[i])); - DOUT << "\n"; - } + delete JoinQueue; } /// Return true if the two specified registers belong to different register -/// classes. The registers may be either phys or virt regs. -bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, - unsigned RegB) const { +/// classes. The registers may be either phys or virt regs. In the +/// case where both registers are virtual registers, it would also returns +/// true by reference the RegB register class in SubRC if it is a subset of +/// RegA's register class. +bool +SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB, + const TargetRegisterClass *&SubRC) const { // Get the register classes for the first reg. - if (MRegisterInfo::isPhysicalRegister(RegA)) { - assert(MRegisterInfo::isVirtualRegister(RegB) && + if (TargetRegisterInfo::isPhysicalRegister(RegA)) { + assert(TargetRegisterInfo::isVirtualRegister(RegB) && "Shouldn't consider two physregs!"); - return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA); + return !mri_->getRegClass(RegB)->contains(RegA); } // Compare against the regclass for the second reg. - const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA); - if (MRegisterInfo::isVirtualRegister(RegB)) - return RegClass != mf_->getRegInfo().getRegClass(RegB); - else - return !RegClass->contains(RegB); + const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA); + if (TargetRegisterInfo::isVirtualRegister(RegB)) { + const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB); + if (RegClassA == RegClassB) + return false; + SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL; + return true; + } + return !RegClassA->contains(RegB); } /// lastRegisterUse - Returns the last use of the specific register between -/// cycles Start and End. It also returns the use operand by reference. It -/// returns NULL if there are no uses. -MachineInstr * +/// cycles Start and End or NULL if there are no uses. +MachineOperand * SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, - unsigned Reg, MachineOperand *&MOU) { - int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; - int s = Start; - while (e >= s) { - // Skip deleted instructions - MachineInstr *MI = li_->getInstructionFromIndex(e); - while ((e - InstrSlots::NUM) >= s && !MI) { - e -= InstrSlots::NUM; - MI = li_->getInstructionFromIndex(e); - } - if (e < s || MI == NULL) - return NULL; - - for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isUse() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { - MOU = &MO; - return MI; + unsigned Reg, unsigned &UseIdx) const{ + UseIdx = 0; + if (TargetRegisterInfo::isVirtualRegister(Reg)) { + MachineOperand *LastUse = NULL; + for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg), + E = mri_->use_end(); I != E; ++I) { + MachineOperand &Use = I.getOperand(); + MachineInstr *UseMI = Use.getParent(); + unsigned SrcReg, DstReg; + if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg) + // Ignore identity copies. + continue; + unsigned Idx = li_->getInstructionIndex(UseMI); + if (Idx >= Start && Idx < End && Idx >= UseIdx) { + LastUse = &Use; + UseIdx = Idx; } } - - e -= InstrSlots::NUM; + return LastUse; } - return NULL; -} - - -/// findDefOperand - Returns the MachineOperand that is a def of the specific -/// register. It returns NULL if the def is not found. -MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) - return &MO; - } - return NULL; -} - -/// unsetRegisterKill - Unset IsKill property of all uses of specific register -/// of the specific instruction. -void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) - MO.setIsKill(false); - } -} - -/// unsetRegisterKills - Unset IsKill property of all uses of specific register -/// between cycles Start and End. -void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End, - unsigned Reg) { int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; int s = Start; while (e >= s) { @@ -1320,46 +1991,35 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End, MI = li_->getInstructionFromIndex(e); } if (e < s || MI == NULL) - return; + return NULL; - for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { - MO.setIsKill(false); + // Ignore identity copies. + unsigned SrcReg, DstReg; + if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)) + for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { + MachineOperand &Use = MI->getOperand(i); + if (Use.isRegister() && Use.isUse() && Use.getReg() && + tri_->regsOverlap(Use.getReg(), Reg)) { + UseIdx = e; + return &Use; + } } - } e -= InstrSlots::NUM; } -} -/// hasRegisterDef - True if the instruction defines the specific register. -/// -bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) - return true; - } - return false; + return NULL; } + void SimpleRegisterCoalescing::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - cerr << mri_->getName(reg); + if (TargetRegisterInfo::isPhysicalRegister(reg)) + cerr << tri_->getName(reg); else cerr << "%reg" << reg; } void SimpleRegisterCoalescing::releaseMemory() { - for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i) - r2rRevMap_[i].clear(); - r2rRevMap_.clear(); - r2rMap_.clear(); - JoinedLIs.clear(); - SubRegIdxes.clear(); JoinedCopies.clear(); } @@ -1371,57 +2031,76 @@ static bool isZeroLengthInterval(LiveInterval *li) { return true; } +/// TurnCopyIntoImpDef - If source of the specified copy is an implicit def, +/// turn the copy into an implicit def. +bool +SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I, + MachineBasicBlock *MBB, + unsigned DstReg, unsigned SrcReg) { + MachineInstr *CopyMI = &*I; + unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); + if (!li_->hasInterval(SrcReg)) + return false; + LiveInterval &SrcInt = li_->getInterval(SrcReg); + if (!SrcInt.empty()) + return false; + if (!li_->hasInterval(DstReg)) + return false; + LiveInterval &DstInt = li_->getInterval(DstReg); + const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx); + DstInt.removeValNo(DstLR->valno); + CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF)); + for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i) + CopyMI->RemoveOperand(i); + bool NoUse = mri_->use_begin(SrcReg) == mri_->use_end(); + if (NoUse) { + for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), + E = mri_->reg_end(); I != E; ) { + assert(I.getOperand().isDef()); + MachineInstr *DefMI = &*I; + ++I; + // The implicit_def source has no other uses, delete it. + assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF); + li_->RemoveMachineInstrFromMaps(DefMI); + DefMI->eraseFromParent(); + } + } + ++I; + return true; +} + + bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; + mri_ = &fn.getRegInfo(); tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); li_ = &getAnalysis(); - lv_ = &getAnalysis(); loopInfo = &getAnalysis(); DOUT << "********** SIMPLE REGISTER COALESCING **********\n" << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'; - allocatableRegs_ = mri_->getAllocatableSet(fn); - for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(), - E = mri_->regclass_end(); I != E; ++I) - allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I))); - - MachineRegisterInfo &RegInfo = mf_->getRegInfo(); - r2rMap_.grow(RegInfo.getLastVirtReg()); - r2rRevMap_.grow(RegInfo.getLastVirtReg()); + allocatableRegs_ = tri_->getAllocatableSet(fn); + for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), + E = tri_->regclass_end(); I != E; ++I) + allocatableRCRegs_.insert(std::make_pair(*I, + tri_->getAllocatableSet(fn, *I))); // Join (coalesce) intervals if requested. - IndexedMap RegSubIdxMap; if (EnableJoining) { joinIntervals(); DOUT << "********** INTERVALS POST JOINING **********\n"; - for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { - I->second.print(DOUT, mri_); + for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ + I->second.print(DOUT, tri_); DOUT << "\n"; } - - // Delete all coalesced copies. - for (SmallPtrSet::iterator I = JoinedCopies.begin(), - E = JoinedCopies.end(); I != E; ++I) { - li_->RemoveMachineInstrFromMaps(*I); - (*I)->eraseFromParent(); - } - - // Transfer sub-registers info to SSARegMap now that coalescing information - // is complete. - RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1); - while (!SubRegIdxes.empty()) { - std::pair RI = SubRegIdxes.back(); - SubRegIdxes.pop_back(); - RegSubIdxMap[RI.first] = RI.second; - } } - // perform a final pass over the instructions and compute spill - // weights, coalesce virtual registers and remove identity moves. + // Perform a final pass over the instructions and compute spill weights + // and remove identity moves. for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { MachineBasicBlock* mbb = mbbi; @@ -1429,42 +2108,49 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); mii != mie; ) { - // if the move will be an identity move delete it - unsigned srcReg, dstReg, RegRep; - if (tii_->isMoveInstr(*mii, srcReg, dstReg) && - (RegRep = rep(srcReg)) == rep(dstReg)) { - // remove from def list - LiveInterval &RegInt = li_->getOrCreateInterval(RegRep); - MachineOperand *MO = mii->findRegisterDefOperand(dstReg); - // If def of this move instruction is dead, remove its live range from - // the dstination register's live interval. - if (MO->isDead()) { - unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii)); - LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx); - RegInt.removeRange(MLR->start, MoveIdx+1); - if (RegInt.empty()) - li_->removeInterval(RegRep); + MachineInstr *MI = mii; + unsigned SrcReg, DstReg; + if (JoinedCopies.count(MI)) { + // Delete all coalesced copies. + if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) { + assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || + MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) && + "Unrecognized copy instruction"); + DstReg = MI->getOperand(0).getReg(); + } + if (MI->registerDefIsDead(DstReg)) { + LiveInterval &li = li_->getInterval(DstReg); + if (!ShortenDeadCopySrcLiveRange(li, MI)) + ShortenDeadCopyLiveRange(li, MI); + } + li_->RemoveMachineInstrFromMaps(MI); + mii = mbbi->erase(mii); + ++numPeep; + continue; + } + + // If the move will be an identity move delete it + bool isMove = tii_->isMoveInstr(*mii, SrcReg, DstReg); + if (isMove && SrcReg == DstReg) { + if (li_->hasInterval(SrcReg)) { + LiveInterval &RegInt = li_->getInterval(SrcReg); + // If def of this move instruction is dead, remove its live range + // from the dstination register's live interval. + if (mii->registerDefIsDead(DstReg)) { + if (!ShortenDeadCopySrcLiveRange(RegInt, mii)) + ShortenDeadCopyLiveRange(RegInt, mii); + } } li_->RemoveMachineInstrFromMaps(mii); mii = mbbi->erase(mii); ++numPeep; - } else { + } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) { SmallSet UniqueUses; for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && - MRegisterInfo::isVirtualRegister(mop.getReg())) { - // replace register with representative register - unsigned OrigReg = mop.getReg(); - unsigned reg = rep(OrigReg); - unsigned SubIdx = RegSubIdxMap[OrigReg]; - if (SubIdx && MRegisterInfo::isPhysicalRegister(reg)) - mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx)); - else { - mii->getOperand(i).setReg(reg); - mii->getOperand(i).setSubReg(SubIdx); - } - + TargetRegisterInfo::isVirtualRegister(mop.getReg())) { + unsigned reg = mop.getReg(); // Multiple uses of reg by the same instruction. It should not // contribute to spill weight again. if (UniqueUses.count(reg) != 0) @@ -1482,7 +2168,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { LiveInterval &LI = I->second; - if (MRegisterInfo::isVirtualRegister(LI.reg)) { + if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { // If the live interval length is essentially zero, i.e. in every live // range the use follows def immediately, it doesn't make sense to spill // it and hope it will be easier to allocate for this li. @@ -1490,7 +2176,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { LI.weight = HUGE_VALF; else { bool isLoad = false; - if (ReMatSpillWeight && li_->isReMaterializable(LI, isLoad)) { + if (li_->isReMaterializable(LI, isLoad)) { // If all of the definitions of the interval are re-materializable, // it is a preferred candidate for spilling. If non of the defs are // loads, then it's potentially very cheap to re-materialize.