X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSimpleRegisterCoalescing.h;h=330c476dbf5a92bf1a301feac2718589706f15f3;hb=f9410141f703f4e8a6aba717617ef958249f6d13;hp=5b3d6b67a91b8291f3adb9eddaeadf30c3e009f4;hpb=9c1e06e18721206c736512f3448997b41145019c;p=oota-llvm.git diff --git a/lib/CodeGen/SimpleRegisterCoalescing.h b/lib/CodeGen/SimpleRegisterCoalescing.h index 5b3d6b67a91..330c476dbf5 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.h +++ b/lib/CodeGen/SimpleRegisterCoalescing.h @@ -83,7 +83,6 @@ namespace llvm { const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; LiveIntervals *li_; - LiveVariables *lv_; const MachineLoopInfo* loopInfo; BitVector allocatableRegs_; @@ -97,9 +96,17 @@ namespace llvm { /// SmallPtrSet JoinedCopies; + /// ReMatCopies - Keep track of copies eliminated due to remat. + /// + SmallPtrSet ReMatCopies; + + /// ReMatDefs - Keep track of definition instructions which have + /// been remat'ed. + SmallPtrSet ReMatDefs; + public: static char ID; // Pass identifcation, replacement for typeid - SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {} + SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {} struct InstrSlots { enum { @@ -127,7 +134,8 @@ namespace llvm { unsigned getRepIntervalSize(unsigned Reg) { if (!li_->hasInterval(Reg)) return 0; - return li_->getInterval(Reg).getSize(); + return li_->getApproximateInstructionCount(li_->getInterval(Reg)) * + LiveIntervals::InstrSlots::NUM; } /// print - Implement the dump method. @@ -166,9 +174,13 @@ namespace llvm { /// joins them and returns true. bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS); - /// Return true if the two specified registers belong to different - /// register classes. The registers may be either phys or virt regs. - bool differingRegisterClasses(unsigned RegA, unsigned RegB) const; + /// Return true if the two specified registers belong to different register + /// classes. The registers may be either phys or virt regs. In the + /// case where both registers are virtual registers, it would also returns + /// true by reference the RegB register class in SubRC if it is a subset of + /// RegA's register class. + bool differingRegisterClasses(unsigned RegA, unsigned RegB, + const TargetRegisterClass *&SubRC) const; /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If @@ -190,6 +202,9 @@ namespace llvm { bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB, MachineInstr *CopyMI); + bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg, + MachineInstr *CopyMI); + /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def, /// turn the copy into an implicit def. bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I, @@ -206,6 +221,19 @@ namespace llvm { /// identity copies so they will be removed. void RemoveCopiesFromValNo(LiveInterval &li, VNInfo *VNI); + /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is + /// a subset of the register class of SrcReg, return true if it's profitable + /// to coalesce the two registers. + bool isProfitableToCoalesceToSubRC(unsigned SrcReg, unsigned DstReg, + MachineBasicBlock *MBB); + + /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual + /// register with a physical register, check if any of the virtual register + /// operand is a sub-register use or def. If so, make sure it won't result + /// in an illegal extract_subreg or insert_subreg instruction. + bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI, + unsigned VirtReg, unsigned PhysReg); + /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of /// the specified live interval is defined by a copy from the specified /// register.