X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSpiller.cpp;h=af3da9e16b44ba7833794a441781c1c5f5c8648e;hb=285133714f0d995e0e14a77e23a0abe5dfc32d17;hp=919a0ce160f41390934171a005147a8c385be436;hpb=10382fb71d8306f320ecbeb7049d25354c0e5457;p=oota-llvm.git diff --git a/lib/CodeGen/Spiller.cpp b/lib/CodeGen/Spiller.cpp index 919a0ce160f..af3da9e16b4 100644 --- a/lib/CodeGen/Spiller.cpp +++ b/lib/CodeGen/Spiller.cpp @@ -7,21 +7,41 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "spiller" - #include "Spiller.h" -#include "VirtRegMap.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveRangeEdit.h" #include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/CodeGen/VirtRegMap.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; +#define DEBUG_TYPE "spiller" + +namespace { + enum SpillerName { trivial, inline_ }; +} + +static cl::opt +spillerOpt("spiller", + cl::desc("Spiller to use: (default: standard)"), + cl::Prefix, + cl::values(clEnumVal(trivial, "trivial spiller"), + clEnumValN(inline_, "inline", "inline spiller"), + clEnumValEnd), + cl::init(trivial)); + +// Spiller virtual destructor implementation. Spiller::~Spiller() {} namespace { @@ -29,267 +49,136 @@ namespace { /// Utility class for spillers. class SpillerBase : public Spiller { protected: - + MachineFunctionPass *pass; MachineFunction *mf; + VirtRegMap *vrm; LiveIntervals *lis; - LiveStacks *ls; MachineFrameInfo *mfi; MachineRegisterInfo *mri; const TargetInstrInfo *tii; - VirtRegMap *vrm; - - /// Construct a spiller base. - SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, - VirtRegMap *vrm) : - mf(mf), lis(lis), ls(ls), vrm(vrm) - { - mfi = mf->getFrameInfo(); - mri = &mf->getRegInfo(); - tii = mf->getTarget().getInstrInfo(); - } - - /// Ensures there is space before the given machine instruction, returns the - /// instruction's new number. - unsigned makeSpaceBefore(MachineInstr *mi) { - if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) { - lis->scaleNumbering(2); - ls->scaleNumbering(2); - } - - unsigned miIdx = lis->getInstructionIndex(mi); - - assert(lis->hasGapBeforeInstr(miIdx)); - - return miIdx; - } - - /// Ensure there is space after the given machine instruction, returns the - /// instruction's new number. - unsigned makeSpaceAfter(MachineInstr *mi) { - if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) { - lis->scaleNumbering(2); - ls->scaleNumbering(2); - } - - unsigned miIdx = lis->getInstructionIndex(mi); - - assert(lis->hasGapAfterInstr(miIdx)); - - return miIdx; - } - - - /// Insert a store of the given vreg to the given stack slot immediately - /// after the given instruction. Returns the base index of the inserted - /// instruction. The caller is responsible for adding an appropriate - /// LiveInterval to the LiveIntervals analysis. - unsigned insertStoreFor(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - MachineBasicBlock::iterator nextInstItr(mi); - ++nextInstItr; - - unsigned miIdx = makeSpaceAfter(mi); - - tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg, - true, ss, trc); - MachineBasicBlock::iterator storeInstItr(mi); - ++storeInstItr; - MachineInstr *storeInst = &*storeInstItr; - unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM; - - assert(lis->getInstructionFromIndex(storeInstIdx) == 0 && - "Store inst index already in use."); - - lis->InsertMachineInstrInMaps(storeInst, storeInstIdx); + const TargetRegisterInfo *tri; - return storeInstIdx; - } - - void insertStoreOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - unsigned storeInstIdx = insertStoreFor(mi, ss, vreg, trc); - unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)), - end = lis->getUseIndex(storeInstIdx); - - VNInfo *vni = - li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator()); - vni->kills.push_back(storeInstIdx); - LiveRange lr(start, end, vni); - - li->addRange(lr); - } - - /// Insert a load of the given veg from the given stack slot immediately - /// before the given instruction. Returns the base index of the inserted - /// instruction. The caller is responsible for adding an appropriate - /// LiveInterval to the LiveIntervals analysis. - unsigned insertLoadFor(MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - MachineBasicBlock::iterator useInstItr(mi); - - unsigned miIdx = makeSpaceBefore(mi); - - tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, vreg, ss, trc); - MachineBasicBlock::iterator loadInstItr(mi); - --loadInstItr; - MachineInstr *loadInst = &*loadInstItr; - unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM; - - assert(lis->getInstructionFromIndex(loadInstIdx) == 0 && - "Load inst index already in use."); - - lis->InsertMachineInstrInMaps(loadInst, loadInstIdx); - - return loadInstIdx; - } - - void insertLoadOnInterval(LiveInterval *li, - MachineInstr *mi, unsigned ss, - unsigned vreg, - const TargetRegisterClass *trc) { - - unsigned loadInstIdx = insertLoadFor(mi, ss, vreg, trc); - unsigned start = lis->getDefIndex(loadInstIdx), - end = lis->getUseIndex(lis->getInstructionIndex(mi)); - - VNInfo *vni = - li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator()); - vni->kills.push_back(lis->getInstructionIndex(mi)); - LiveRange lr(start, end, vni); - - li->addRange(lr); + /// Construct a spiller base. + SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm) + : pass(&pass), mf(&mf), vrm(&vrm) + { + lis = &pass.getAnalysis(); + mfi = mf.getFrameInfo(); + mri = &mf.getRegInfo(); + tii = mf.getSubtarget().getInstrInfo(); + tri = mf.getSubtarget().getRegisterInfo(); } - - /// Add spill ranges for every use/def of the live interval, inserting loads - /// immediately before each use, and stores after each def. No folding is - /// attempted. - std::vector trivialSpillEverywhere(LiveInterval *li) { - DOUT << "Spilling everywhere " << *li << "\n"; + /// immediately before each use, and stores after each def. No folding or + /// remat is attempted. + void trivialSpillEverywhere(LiveRangeEdit& LRE) { + LiveInterval* li = &LRE.getParent(); - assert(li->weight != HUGE_VALF && + DEBUG(dbgs() << "Spilling everywhere " << *li << "\n"); + + assert(li->weight != llvm::huge_valf && "Attempting to spill already spilled value."); - assert(!li->isStackSlot() && + assert(!TargetRegisterInfo::isStackSlot(li->reg) && "Trying to spill a stack slot."); - std::vector added; - + DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n"); + const TargetRegisterClass *trc = mri->getRegClass(li->reg); unsigned ss = vrm->assignVirt2StackSlot(li->reg); - for (MachineRegisterInfo::reg_iterator - regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { + // Iterate over reg uses/defs. + for (MachineRegisterInfo::reg_instr_iterator + regItr = mri->reg_instr_begin(li->reg); + regItr != mri->reg_instr_end();) { + // Grab the use/def instr. MachineInstr *mi = &*regItr; - do { - ++regItr; - } while (regItr != mri->reg_end() && (&*regItr == mi)); - + + DEBUG(dbgs() << " Processing " << *mi); + + // Step regItr to the next use/def instr. + ++regItr; + + // Collect uses & defs for this instr. SmallVector indices; bool hasUse = false; bool hasDef = false; - for (unsigned i = 0; i != mi->getNumOperands(); ++i) { MachineOperand &op = mi->getOperand(i); - if (!op.isReg() || op.getReg() != li->reg) continue; - hasUse |= mi->getOperand(i).isUse(); hasDef |= mi->getOperand(i).isDef(); - indices.push_back(i); } - unsigned newVReg = mri->createVirtualRegister(trc); - vrm->grow(); - vrm->assignVirt2StackSlot(newVReg, ss); + // Create a new virtual register for the load and/or store. + unsigned NewVReg = LRE.create(); - LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); - newLI->weight = HUGE_VALF; - + // Update the reg operands & kill flags. for (unsigned i = 0; i < indices.size(); ++i) { - mi->getOperand(indices[i]).setReg(newVReg); - - if (mi->getOperand(indices[i]).isUse()) { - mi->getOperand(indices[i]).setIsKill(true); + unsigned mopIdx = indices[i]; + MachineOperand &mop = mi->getOperand(mopIdx); + mop.setReg(NewVReg); + if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { + mop.setIsKill(true); } } - assert(hasUse || hasDef); + // Insert reload if necessary. + MachineBasicBlock::iterator miItr(mi); if (hasUse) { - insertLoadOnInterval(newLI, mi, ss, newVReg, trc); + MachineInstrSpan MIS(miItr); + + tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc, + tri); + lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr); } + // Insert store if necessary. if (hasDef) { - insertStoreOnInterval(newLI, mi, ss, newVReg, trc); - } + MachineInstrSpan MIS(miItr); - added.push_back(newLI); + tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg, + true, ss, trc, tri); + lis->InsertMachineInstrRangeInMaps(std::next(miItr), MIS.end()); + } } - - return added; } - }; +} // end anonymous namespace + +namespace { /// Spills any live range using the spill-everywhere method with no attempt at /// folding. class TrivialSpiller : public SpillerBase { public: - TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, - VirtRegMap *vrm) : - SpillerBase(mf, lis, ls, vrm) {} + TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf, + VirtRegMap &vrm) + : SpillerBase(pass, mf, vrm) {} - std::vector spill(LiveInterval *li) { - return trivialSpillEverywhere(li); + void spill(LiveRangeEdit &LRE) override { + // Ignore spillIs - we don't use it. + trivialSpillEverywhere(LRE); } +}; - std::vector intraBlockSplit(LiveInterval *li, VNInfo *valno) { - std::vector spillIntervals; - MachineBasicBlock::iterator storeInsertPoint; - - if (valno->isDefAccurate()) { - // If we have an accurate def we can just grab an iterator to the instr - // after the def. - storeInsertPoint = - next(MachineBasicBlock::iterator(lis->getInstructionFromIndex(valno->def))); - } else { - // If the def info isn't accurate we check if this is a PHI def. - // If it is then def holds the index of the defining Basic Block, and we - // can use that to get an insertion point. - if (valno->isPHIDef()) { - - } else { - // We have no usable def info. We can't split this value sensibly. - // FIXME: Need sensible feedback for "failure to split", an empty - // set of spill intervals could be reasonably returned from a - // split where both the store and load are folded. - return spillIntervals; - } - } +} // end anonymous namespace - +void Spiller::anchor() { } - return spillIntervals; +llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass, + MachineFunction &mf, + VirtRegMap &vrm) { + switch (spillerOpt) { + case trivial: return new TrivialSpiller(pass, mf, vrm); + case inline_: return createInlineSpiller(pass, mf, vrm); } - -}; - -} - -llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis, - LiveStacks *ls, VirtRegMap *vrm) { - return new TrivialSpiller(mf, lis, ls, vrm); + llvm_unreachable("Invalid spiller optimization"); }