X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FStackMaps.cpp;h=f347e96971817ff5122540e8d481116bf0e6614f;hb=3bfc4d8e13edd83534b733f0f1de5b1d5f6bf828;hp=892e4573b0d4056d4ccbe2ce1473e95cdf2ba0c8;hpb=539e93120cdbb66f651fc55a810416f3175adc8f;p=oota-llvm.git diff --git a/lib/CodeGen/StackMaps.cpp b/lib/CodeGen/StackMaps.cpp index 892e4573b0d..f347e969718 100644 --- a/lib/CodeGen/StackMaps.cpp +++ b/lib/CodeGen/StackMaps.cpp @@ -10,8 +10,9 @@ #define DEBUG_TYPE "stackmaps" #include "llvm/CodeGen/StackMaps.h" - #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCContext.h" @@ -21,22 +22,20 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" - #include using namespace llvm; -PatchPointOpers::PatchPointOpers(const MachineInstr *MI): - MI(MI), - HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && - !MI->getOperand(0).isImplicit()), - IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg) { - +PatchPointOpers::PatchPointOpers(const MachineInstr *MI) + : MI(MI), + HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && + !MI->getOperand(0).isImplicit()), + IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg) +{ #ifndef NDEBUG - { unsigned CheckStartIdx = 0, e = MI->getNumOperands(); while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() && MI->getOperand(CheckStartIdx).isDef() && @@ -44,8 +43,7 @@ PatchPointOpers::PatchPointOpers(const MachineInstr *MI): ++CheckStartIdx; assert(getMetaIdx() == CheckStartIdx && - "Unexpected additonal definition in Patchpoint intrinsic."); - } + "Unexpected additional definition in Patchpoint intrinsic."); #endif } @@ -66,88 +64,82 @@ unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const { return ScratchIdx; } -std::pair +MachineInstr::const_mop_iterator StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, - MachineInstr::const_mop_iterator MOE) const { - const MachineOperand &MOP = *MOI; - assert((!MOP.isReg() || !MOP.isImplicit()) && - "Implicit operands should not be processed."); - - if (MOP.isImm()) { - // Verify anyregcc - // [], , , , , , ... - - switch (MOP.getImm()) { - default: llvm_unreachable("Unrecognized operand type."); - case StackMaps::DirectMemRefOp: { - unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits(); - assert((Size % 8) == 0 && "Need pointer size in bytes."); - Size /= 8; - unsigned Reg = (++MOI)->getReg(); - int64_t Imm = (++MOI)->getImm(); - return std::make_pair( - Location(StackMaps::Location::Direct, Size, Reg, Imm), ++MOI); - } - case StackMaps::IndirectMemRefOp: { - int64_t Size = (++MOI)->getImm(); - assert(Size > 0 && "Need a valid size for indirect memory locations."); - unsigned Reg = (++MOI)->getReg(); - int64_t Imm = (++MOI)->getImm(); - return std::make_pair( - Location(StackMaps::Location::Indirect, Size, Reg, Imm), ++MOI); - } - case StackMaps::ConstantOp: { - ++MOI; - assert(MOI->isImm() && "Expected constant operand."); - int64_t Imm = MOI->getImm(); - return std::make_pair( - Location(Location::Constant, sizeof(int64_t), 0, Imm), ++MOI); - } + MachineInstr::const_mop_iterator MOE, + LocationVec &Locs, LiveOutVec &LiveOuts) const { + if (MOI->isImm()) { + switch (MOI->getImm()) { + default: llvm_unreachable("Unrecognized operand type."); + case StackMaps::DirectMemRefOp: { + unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits(); + assert((Size % 8) == 0 && "Need pointer size in bytes."); + Size /= 8; + unsigned Reg = (++MOI)->getReg(); + int64_t Imm = (++MOI)->getImm(); + Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm)); + break; } + case StackMaps::IndirectMemRefOp: { + int64_t Size = (++MOI)->getImm(); + assert(Size > 0 && "Need a valid size for indirect memory locations."); + unsigned Reg = (++MOI)->getReg(); + int64_t Imm = (++MOI)->getImm(); + Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm)); + break; + } + case StackMaps::ConstantOp: { + ++MOI; + assert(MOI->isImm() && "Expected constant operand."); + int64_t Imm = MOI->getImm(); + Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm)); + break; + } + } + return ++MOI; + } + + // The physical register number will ultimately be encoded as a DWARF regno. + // The stack map also records the size of a spill slot that can hold the + // register content. (The runtime can track the actual size of the data type + // if it needs to.) + if (MOI->isReg()) { + // Skip implicit registers (this includes our scratch registers) + if (MOI->isImplicit()) + return ++MOI; + + assert(TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) && + "Virtreg operands should have been rewritten before now."); + const TargetRegisterClass *RC = + AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOI->getReg()); + assert(!MOI->getSubReg() && "Physical subreg still around."); + Locs.push_back( + Location(Location::Register, RC->getSize(), MOI->getReg(), 0)); + return ++MOI; } - if (MOP.isRegMask() || MOP.isRegLiveOut()) - return std::make_pair(Location(), ++MOI); - - // Otherwise this is a reg operand. The physical register number will - // ultimately be encoded as a DWARF regno. The stack map also records the size - // of a spill slot that can hold the register content. (The runtime can - // track the actual size of the data type if it needs to.) - assert(MOP.isReg() && "Expected register operand here."); - assert(TargetRegisterInfo::isPhysicalRegister(MOP.getReg()) && - "Virtreg operands should have been rewritten before now."); - const TargetRegisterClass *RC = - AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOP.getReg()); - assert(!MOP.getSubReg() && "Physical subreg still around."); - return std::make_pair( - Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI); + if (MOI->isRegLiveOut()) + LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut()); + + return ++MOI; } /// Go up the super-register chain until we hit a valid dwarf register number. -static short getDwarfRegNum(unsigned Reg, const MCRegisterInfo &MCRI, - const TargetRegisterInfo *TRI) { - int RegNo = MCRI.getDwarfRegNum(Reg, false); - for (MCSuperRegIterator SR(Reg, TRI); - SR.isValid() && RegNo < 0; ++SR) +static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { + int RegNo = TRI->getDwarfRegNum(Reg, false); + for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR) RegNo = TRI->getDwarfRegNum(*SR, false); assert(RegNo >= 0 && "Invalid Dwarf register number."); - return (unsigned short) RegNo; + return (unsigned) RegNo; } /// Create a live-out register record for the given register Reg. StackMaps::LiveOutReg -StackMaps::createLiveOutReg(unsigned Reg, const MCRegisterInfo &MCRI, - const TargetRegisterInfo *TRI) const { - unsigned RegNo = getDwarfRegNum(Reg, MCRI, TRI); +StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const { + unsigned RegNo = getDwarfRegNum(Reg, TRI); unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); - unsigned LLVMRegNo = MCRI.getLLVMRegNum(RegNo, false); - unsigned SubRegIdx = MCRI.getSubRegIndex(LLVMRegNo, Reg); - unsigned Offset = 0; - if (SubRegIdx) - Offset = MCRI.getSubRegIdxOffset(SubRegIdx) / 8; - - return LiveOutReg(Reg, RegNo, Offset + Size); + return LiveOutReg(Reg, RegNo, Size); } /// Parse the register live-out mask and return a vector of live-out registers @@ -156,34 +148,37 @@ StackMaps::LiveOutVec StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const { assert(Mask && "No register mask specified"); const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo(); - MCContext &OutContext = AP.OutStreamer.getContext(); - const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo(); LiveOutVec LiveOuts; + // Create a LiveOutReg for each bit that is set in the register mask. for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) if ((Mask[Reg / 32] >> Reg % 32) & 1) - LiveOuts.push_back(createLiveOutReg(Reg, MCRI, TRI)); + LiveOuts.push_back(createLiveOutReg(Reg, TRI)); + // We don't need to keep track of a register if its super-register is already + // in the list. Merge entries that refer to the same dwarf register and use + // the maximum size that needs to be spilled. std::sort(LiveOuts.begin(), LiveOuts.end()); for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end(); I != E; ++I) { - if (!I->Reg) - continue; - for (LiveOutVec::iterator II = next(I); II != E; ++II) { - if (I->RegNo != II->RegNo) + for (LiveOutVec::iterator II = std::next(I); II != E; ++II) { + if (I->RegNo != II->RegNo) { + // Skip all the now invalid entries. + I = --II; break; + } I->Size = std::max(I->Size, II->Size); if (TRI->isSuperRegister(I->Reg, II->Reg)) I->Reg = II->Reg; - II->Reg = 0; + II->MarkInvalid(); } } LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(), - LiveOutReg::isInvalid), LiveOuts.end()); + LiveOutReg::IsInvalid), LiveOuts.end()); return LiveOuts; } -void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint32_t ID, +void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID, MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, bool recordResult) { @@ -196,58 +191,49 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint32_t ID, LiveOutVec LiveOuts; if (recordResult) { - std::pair ParseResult = - parseOperand(MI.operands_begin(), llvm::next(MI.operands_begin())); - - Location &Loc = ParseResult.first; - assert(Loc.LocType == Location::Register && - "Stackmap return location must be a register."); - Locations.push_back(Loc); + assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value."); + parseOperand(MI.operands_begin(), std::next(MI.operands_begin()), + Locations, LiveOuts); } + // Parse operands. while (MOI != MOE) { - Location Loc; - tie(Loc, MOI) = parseOperand(MOI, MOE); + MOI = parseOperand(MOI, MOE, Locations, LiveOuts); + } - // Move large constants into the constant pool. - if (Loc.LocType == Location::Constant && (Loc.Offset & ~0xFFFFFFFFULL)) { - Loc.LocType = Location::ConstantIndex; - Loc.Offset = ConstPool.getConstantIndex(Loc.Offset); + // Move large constants into the constant pool. + for (LocationVec::iterator I = Locations.begin(), E = Locations.end(); + I != E; ++I) { + // Constants are encoded as sign-extended integers. + // -1 is directly encoded as .long 0xFFFFFFFF with no constant pool. + if (I->LocType == Location::Constant && + ((I->Offset + (int64_t(1)<<31)) >> 32) != 0) { + I->LocType = Location::ConstantIndex; + I->Offset = ConstPool.getConstantIndex(I->Offset); } - - // Skip the register mask and register live-out mask - if (Loc.LocType != Location::Unprocessed) - Locations.push_back(Loc); } + // Create an expression to calculate the offset of the callsite from function + // entry. const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub( MCSymbolRefExpr::Create(MILabel, OutContext), MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext), OutContext); - if (MOI->isRegLiveOut()) - LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut()); - CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, Locations, LiveOuts)); -} -static MachineInstr::const_mop_iterator -getStackMapEndMOP(MachineInstr::const_mop_iterator MOI, - MachineInstr::const_mop_iterator MOE) { - for (; MOI != MOE; ++MOI) - if (MOI->isRegLiveOut() || (MOI->isReg() && MOI->isImplicit())) - break; - return MOI; + // Record the stack size of the current function. + const MachineFrameInfo *MFI = AP.MF->getFrameInfo(); + FnStackSize[AP.CurrentFnSym] = + MFI->hasVarSizedObjects() ? ~0U : MFI->getStackSize(); } void StackMaps::recordStackMap(const MachineInstr &MI) { assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap"); int64_t ID = MI.getOperand(0).getImm(); - assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs"); - recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2), - getStackMapEndMOP(MI.operands_begin(), - MI.operands_end())); + recordStackMapOpers(MI, ID, std::next(MI.operands_begin(), 2), + MI.operands_end()); } void StackMaps::recordPatchPoint(const MachineInstr &MI) { @@ -255,10 +241,10 @@ void StackMaps::recordPatchPoint(const MachineInstr &MI) { PatchPointOpers opers(&MI); int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm(); - assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs"); + MachineInstr::const_mop_iterator MOI = - llvm::next(MI.operands_begin(), opers.getStackMapStartIdx()); - recordStackMapOpers(MI, ID, MOI, getStackMapEndMOP(MOI, MI.operands_end()), + std::next(MI.operands_begin(), opers.getStackMapStartIdx()); + recordStackMapOpers(MI, ID, MOI, MI.operands_end(), opers.isAnyReg() && opers.hasDef()); #ifndef NDEBUG @@ -276,11 +262,16 @@ void StackMaps::recordPatchPoint(const MachineInstr &MI) { /// serializeToStackMapSection conceptually populates the following fields: /// /// uint32 : Reserved (header) +/// uint32 : NumFunctions +/// StkSizeRecord[NumFunctions] { +/// uint32 : Function Offset +/// uint32 : Stack Size +/// } /// uint32 : NumConstants /// int64 : Constants[NumConstants] /// uint32 : NumRecords /// StkMapRecord[NumRecords] { -/// uint32 : PatchPoint ID +/// uint64 : PatchPoint ID /// uint32 : Instruction Offset /// uint16 : Reserved (record flags) /// uint16 : NumLocations @@ -324,13 +315,22 @@ void StackMaps::serializeToStackMapSection() { // Serialize data. const char *WSMP = "Stack Maps: "; (void)WSMP; - const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo(); DEBUG(dbgs() << "********** Stack Map Output **********\n"); // Header. AP.OutStreamer.EmitIntValue(0, 4); + // Num functions. + AP.OutStreamer.EmitIntValue(FnStackSize.size(), 4); + + // Stack size entries. + for (FnStackSizeMap::iterator I = FnStackSize.begin(), E = FnStackSize.end(); + I != E; ++I) { + AP.OutStreamer.EmitSymbolValue(I->first, 4); + AP.OutStreamer.EmitIntValue(I->second, 4); + } + // Num constants. AP.OutStreamer.EmitIntValue(ConstPool.getNumConstants(), 4); @@ -345,7 +345,7 @@ void StackMaps::serializeToStackMapSection() { CSIE = CSInfos.end(); CSII != CSIE; ++CSII) { - unsigned CallsiteID = CSII->ID; + uint64_t CallsiteID = CSII->ID; const LocationVec &CSLocs = CSII->Locations; const LiveOutVec &LiveOuts = CSII->LiveOuts; @@ -356,7 +356,7 @@ void StackMaps::serializeToStackMapSection() { // simple overflow checks, but we may eventually communicate other // compilation errors this way. if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) { - AP.OutStreamer.EmitIntValue(UINT32_MAX, 4); // Invalid ID. + AP.OutStreamer.EmitIntValue(UINT64_MAX, 8); // Invalid ID. AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4); AP.OutStreamer.EmitIntValue(0, 2); // Reserved. AP.OutStreamer.EmitIntValue(0, 2); // 0 locations. @@ -364,7 +364,7 @@ void StackMaps::serializeToStackMapSection() { continue; } - AP.OutStreamer.EmitIntValue(CallsiteID, 4); + AP.OutStreamer.EmitIntValue(CallsiteID, 8); AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4); // Reserved for flags. @@ -381,19 +381,16 @@ void StackMaps::serializeToStackMapSection() { unsigned RegNo = 0; int Offset = Loc.Offset; if(Loc.Reg) { - RegNo = MCRI.getDwarfRegNum(Loc.Reg, false); - for (MCSuperRegIterator SR(Loc.Reg, TRI); - SR.isValid() && (int)RegNo < 0; ++SR) { - RegNo = TRI->getDwarfRegNum(*SR, false); - } + RegNo = getDwarfRegNum(Loc.Reg, TRI); + // If this is a register location, put the subregister byte offset in // the location offset. if (Loc.LocType == Location::Register) { assert(!Loc.Offset && "Register location should have zero offset"); - unsigned LLVMRegNo = MCRI.getLLVMRegNum(RegNo, false); - unsigned SubRegIdx = MCRI.getSubRegIndex(LLVMRegNo, Loc.Reg); + unsigned LLVMRegNo = TRI->getLLVMRegNum(RegNo, false); + unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNo, Loc.Reg); if (SubRegIdx) - Offset = MCRI.getSubRegIdxOffset(SubRegIdx); + Offset = TRI->getSubRegIdxOffset(SubRegIdx); } } else { @@ -408,15 +405,15 @@ void StackMaps::serializeToStackMapSection() { dbgs() << ""; break; case Location::Register: - dbgs() << "Register " << MCRI.getName(Loc.Reg); + dbgs() << "Register " << TRI->getName(Loc.Reg); break; case Location::Direct: - dbgs() << "Direct " << MCRI.getName(Loc.Reg); + dbgs() << "Direct " << TRI->getName(Loc.Reg); if (Loc.Offset) dbgs() << " + " << Loc.Offset; break; case Location::Indirect: - dbgs() << "Indirect " << MCRI.getName(Loc.Reg) + dbgs() << "Indirect " << TRI->getName(Loc.Reg) << " + " << Loc.Offset; break; case Location::Constant: @@ -447,7 +444,7 @@ void StackMaps::serializeToStackMapSection() { for (LiveOutVec::const_iterator LI = LiveOuts.begin(), LE = LiveOuts.end(); LI != LE; ++LI, ++operIdx) { DEBUG(dbgs() << WSMP << " LO " << operIdx << ": " - << MCRI.getName(LI->Reg) + << TRI->getName(LI->Reg) << " [encoding: .short " << LI->RegNo << ", .byte 0, .byte " << LI->Size << "]\n");