X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FTargetInstrInfoImpl.cpp;h=598b94af9c41e6f13056b623720813ebba7d2695;hb=e984e504b5f3090ab270cbdab02638ac3a2afb21;hp=4498c984e2641233c6d10af8256432e2e3f13aa4;hpb=8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde;p=oota-llvm.git

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 4498c984e26..598b94af9c4 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -23,8 +23,17 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
          "This only knows how to commute register operands so far");
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
+  MachineOperand &MO = MI->getOperand(0);
+  bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1;
   bool Reg1IsKill = MI->getOperand(1).isKill();
   bool Reg2IsKill = MI->getOperand(2).isKill();
+  if (UpdateReg0) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    Reg2IsKill = false;
+    MI->getOperand(0).setReg(Reg2);
+  }
   MI->getOperand(2).setReg(Reg1);
   MI->getOperand(1).setReg(Reg2);
   MI->getOperand(2).setIsKill(Reg1IsKill);
@@ -35,23 +44,24 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
                                                const std::vector<MachineOperand> &Pred) const {
   bool MadeChange = false;
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (TID->isPredicable()) {
-    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if (TID->OpInfo[i].isPredicate()) {
-        MachineOperand &MO = MI->getOperand(i);
-        if (MO.isReg()) {
-          MO.setReg(Pred[j].getReg());
-          MadeChange = true;
-        } else if (MO.isImm()) {
-          MO.setImm(Pred[j].getImm());
-          MadeChange = true;
-        } else if (MO.isMBB()) {
-          MO.setMBB(Pred[j].getMBB());
-          MadeChange = true;
-        }
-        ++j;
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.isPredicable())
+    return false;
+  
+  for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    if (TID.OpInfo[i].isPredicate()) {
+      MachineOperand &MO = MI->getOperand(i);
+      if (MO.isReg()) {
+        MO.setReg(Pred[j].getReg());
+        MadeChange = true;
+      } else if (MO.isImm()) {
+        MO.setImm(Pred[j].getImm());
+        MadeChange = true;
+      } else if (MO.isMBB()) {
+        MO.setMBB(Pred[j].getMBB());
+        MadeChange = true;
       }
+      ++j;
     }
   }
   return MadeChange;