X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FTargetInstrInfoImpl.cpp;h=ff9c129994eb79713544fee6886f7d2e592069c7;hb=6fa1c051dc515b6fd1f9a26ac12fed985469bff5;hp=cd2bfcce0232b872c09ce9a0bef851eb4744c5a6;hpb=749c6f6b5ed301c84aac562e414486549d7b98eb;p=oota-llvm.git diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index cd2bfcce023..ff9c129994e 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -14,17 +14,39 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" using namespace llvm; // commuteInstruction - The default implementation of this method just exchanges // operand 1 and 2. -MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { +MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, + bool NewMI) const { assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill(); + bool ChangeReg0 = false; + if (MI->getOperand(0).getReg() == Reg1) { + // Must be two address instruction! + assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + "Expecting a two-address instruction!"); + Reg2IsKill = false; + ChangeReg0 = true; + } + + if (NewMI) { + // Create a new instruction. + unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); + bool Reg0IsDead = MI->getOperand(0).isDead(); + return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead) + .addReg(Reg2, false, false, Reg2IsKill) + .addReg(Reg1, false, false, Reg1IsKill); + } + + if (ChangeReg0) + MI->getOperand(0).setReg(Reg2); MI->getOperand(2).setReg(Reg1); MI->getOperand(1).setReg(Reg2); MI->getOperand(2).setIsKill(Reg1IsKill); @@ -32,8 +54,28 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { return MI; } +/// CommuteChangesDestination - Return true if commuting the specified +/// instruction will also changes the destination operand. Also return the +/// current operand index of the would be new destination register by +/// reference. This can happen when the commutable instruction is also a +/// two-address instruction. +bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI, + unsigned &OpIdx) const{ + assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && + "This only knows how to commute register operands so far"); + if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { + // Must be two address instruction! + assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + "Expecting a two-address instruction!"); + OpIdx = 2; + return true; + } + return false; +} + + bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, - const std::vector &Pred) const { + const std::vector &Pred) const { bool MadeChange = false; const TargetInstrDesc &TID = MI->getDesc(); if (!TID.isPredicable()) @@ -57,3 +99,24 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, } return MadeChange; } + +void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, + const MachineInstr *Orig) const { + MachineInstr *MI = Orig->clone(); + MI->getOperand(0).setReg(DestReg); + MBB.insert(I, MI); +} + +unsigned +TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const { + unsigned FnSize = 0; + for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); + MBBI != E; ++MBBI) { + const MachineBasicBlock &MBB = *MBBI; + for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I) + FnSize += GetInstSizeInBytes(I); + } + return FnSize; +}