X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FTwoAddressInstructionPass.cpp;h=81864b7c0e4e81c6de067aae0d996d79db0d5beb;hb=fc329f4fa18cf4e7b64c1813041d4895b19fa347;hp=53b08d6bf0fb160cd209a38caa81af9dad095425;hpb=b9d5e7cdc9ce587f27e0ea9ced35db60f2601d2e;p=oota-llvm.git diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 53b08d6bf0f..81864b7c0e4 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -33,12 +33,14 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Support/Debug.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; @@ -46,57 +48,176 @@ using namespace llvm; STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); +STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); + +static cl::opt +EnableReMat("2-addr-remat", cl::init(false), cl::Hidden, + cl::desc("Two-addr conversion should remat when possible.")); namespace { - struct VISIBILITY_HIDDEN TwoAddressInstructionPass - : public MachineFunctionPass { + class VISIBILITY_HIDDEN TwoAddressInstructionPass + : public MachineFunctionPass { + const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; + MachineRegisterInfo *MRI; + LiveVariables *LV; + + bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, + unsigned Reg, + MachineBasicBlock::iterator OldPos); + public: static char ID; // Pass identification, replacement for typeid TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {} - virtual void getAnalysisUsage(AnalysisUsage &AU) const; + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.addPreserved(); + AU.addPreservedID(MachineLoopInfoID); + AU.addPreservedID(MachineDominatorsID); + AU.addPreservedID(PHIEliminationID); + MachineFunctionPass::getAnalysisUsage(AU); + } - /// runOnMachineFunction - pass entry point + /// runOnMachineFunction - Pass entry point. bool runOnMachineFunction(MachineFunction&); }; - - char TwoAddressInstructionPass::ID = 0; - RegisterPass - X("twoaddressinstruction", "Two-Address instruction pass"); } -const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo(); +char TwoAddressInstructionPass::ID = 0; +static RegisterPass +X("twoaddressinstruction", "Two-Address instruction pass"); + +const PassInfo *const llvm::TwoAddressInstructionPassID = &X; -void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addPreserved(); - AU.addPreservedID(PHIEliminationID); - MachineFunctionPass::getAnalysisUsage(AU); +/// Sink3AddrInstruction - A two-address instruction has been converted to a +/// three-address instruction to avoid clobbering a register. Try to sink it +/// past the instruction that would kill the above mentioned register to reduce +/// register pressure. +/// +bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, + MachineInstr *MI, unsigned SavedReg, + MachineBasicBlock::iterator OldPos) { + // Check if it's safe to move this instruction. + bool SeenStore = true; // Be conservative. + if (!MI->isSafeToMove(TII, SeenStore)) + return false; + + unsigned DefReg = 0; + SmallSet UseRegs; + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isRegister()) + continue; + unsigned MOReg = MO.getReg(); + if (!MOReg) + continue; + if (MO.isUse() && MOReg != SavedReg) + UseRegs.insert(MO.getReg()); + if (!MO.isDef()) + continue; + if (MO.isImplicit()) + // Don't try to move it if it implicitly defines a register. + return false; + if (DefReg) + // For now, don't move any instructions that define multiple registers. + return false; + DefReg = MO.getReg(); + } + + // Find the instruction that kills SavedReg. + MachineInstr *KillMI = NULL; + + for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg), + UE = MRI->use_end(); UI != UE; ++UI) { + MachineOperand &UseMO = UI.getOperand(); + if (!UseMO.isKill()) + continue; + KillMI = UseMO.getParent(); + break; + } + + if (!KillMI || KillMI->getParent() != MBB) + return false; + + // If any of the definitions are used by another instruction between the + // position and the kill use, then it's not safe to sink it. + // + // FIXME: This can be sped up if there is an easy way to query whether an + // instruction if before or after another instruction. Then we can use + // MachineRegisterInfo def / use instead. + MachineOperand *KillMO = NULL; + MachineBasicBlock::iterator KillPos = KillMI; + ++KillPos; + + for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) { + MachineInstr *OtherMI = I; + + for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = OtherMI->getOperand(i); + if (!MO.isRegister()) + continue; + unsigned MOReg = MO.getReg(); + if (!MOReg) + continue; + if (DefReg == MOReg) + return false; + + if (MO.isKill()) { + if (OtherMI == KillMI && MOReg == SavedReg) + // Save the operand that kills the register. We want unset the kill + // marker is we can sink MI past it. + KillMO = &MO; + else if (UseRegs.count(MOReg)) + // One of the uses is killed before the destination. + return false; + } + } + } + + // Update kill and LV information. + KillMO->setIsKill(false); + KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); + KillMO->setIsKill(true); + LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg); + VarInfo.removeKill(KillMI); + VarInfo.Kills.push_back(MI); + + // Move instruction to its destination. + MBB->remove(MI); + MBB->insert(KillPos, MI); + + ++Num3AddrSunk; + return true; } -/// runOnMachineFunction - Reduce two-address instructions to two -/// operands. +/// runOnMachineFunction - Reduce two-address instructions to two operands. /// bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { DOUT << "Machine Function\n"; const TargetMachine &TM = MF.getTarget(); - const TargetInstrInfo &TII = *TM.getInstrInfo(); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); - LiveVariables &LV = getAnalysis(); + MRI = &MF.getRegInfo(); + TII = TM.getInstrInfo(); + TRI = TM.getRegisterInfo(); + LV = &getAnalysis(); bool MadeChange = false; DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n"; DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; + SmallPtrSet ReMattedInstrs; + for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) { for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); - mi != me; ++mi) { - const TargetInstrDescriptor *TID = mi->getInstrDescriptor(); - + mi != me; ) { + MachineBasicBlock::iterator nmi = next(mi); + const TargetInstrDesc &TID = mi->getDesc(); bool FirstTied = true; - for (unsigned si = 1, e = TID->numOperands; si < e; ++si) { - int ti = TID->getOperandConstraint(si, TOI::TIED_TO); + + for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) { + int ti = TID.getOperandConstraint(si, TOI::TIED_TO); if (ti == -1) continue; @@ -104,15 +225,16 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { ++NumTwoAddressInstrs; DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM)); } + FirstTied = false; assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() && mi->getOperand(si).isUse() && "two address instruction invalid"); - // if the two operands are the same we just remove the use + // If the two operands are the same we just remove the use // and mark the def as def&use, otherwise we have to insert a copy. if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) { - // rewrite: + // Rewrite: // a = b op c // to: // a = b @@ -120,8 +242,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { unsigned regA = mi->getOperand(ti).getReg(); unsigned regB = mi->getOperand(si).getReg(); - assert(MRegisterInfo::isVirtualRegister(regA) && - MRegisterInfo::isVirtualRegister(regB) && + assert(TargetRegisterInfo::isVirtualRegister(regA) && + TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); #ifndef NDEBUG @@ -138,25 +260,27 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // rearrange the code to make it so. Making it the killing user will // allow us to coalesce A and B together, eliminating the copy we are // about to insert. - if (!LV.KillsRegister(mi, regB)) { + if (!mi->killsRegister(regB)) { // If this instruction is commutative, check to see if C dies. If // so, swap the B and C operands. This makes the live ranges of A // and C joinable. // FIXME: This code also works for A := B op C instructions. - if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) { + if (TID.isCommutable() && mi->getNumOperands() >= 3) { assert(mi->getOperand(3-si).isRegister() && "Not a proper commutative instruction!"); unsigned regC = mi->getOperand(3-si).getReg(); - if (LV.KillsRegister(mi, regC)) { + + if (mi->killsRegister(regC)) { DOUT << "2addr: COMMUTING : " << *mi; - MachineInstr *NewMI = TII.commuteInstruction(mi); + MachineInstr *NewMI = TII->commuteInstruction(mi); + if (NewMI == 0) { DOUT << "2addr: COMMUTING FAILED!\n"; } else { DOUT << "2addr: COMMUTED TO: " << *NewMI; // If the instruction changed to commute it, update livevar. if (NewMI != mi) { - LV.instructionChanged(mi, NewMI); // Update live variables + LV->instructionChanged(mi, NewMI); // Update live variables mbbi->insert(mi, NewMI); // Insert the new inst mbbi->erase(mi); // Nuke the old inst. mi = NewMI; @@ -171,44 +295,70 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // If this instruction is potentially convertible to a true // three-address instruction, - if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR) { + if (TID.isConvertibleTo3Addr()) { // FIXME: This assumes there are no more operands which are tied // to another register. #ifndef NDEBUG - for (unsigned i = si+1, e = TID->numOperands; i < e; ++i) - assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1); + for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i) + assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1); #endif - if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) { + if (MachineInstr *New=TII->convertToThreeAddress(mbbi, mi, *LV)) { DOUT << "2addr: CONVERTING 2-ADDR: " << *mi; DOUT << "2addr: TO 3-ADDR: " << *New; - mbbi->erase(mi); // Nuke the old inst. - mi = New; + bool Sunk = false; + + if (New->findRegisterUseOperand(regB, false, TRI)) + // FIXME: Temporary workaround. If the new instruction doesn't + // uses regB, convertToThreeAddress must have created more + // then one instruction. + Sunk = Sink3AddrInstruction(mbbi, New, regB, mi); + + mbbi->erase(mi); // Nuke the old inst. + + if (!Sunk) { + mi = New; + nmi = next(mi); + } + ++NumConvertedTo3Addr; - // Done with this instruction. - break; + break; // Done with this instruction. } } } InstructionRearranged: - const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); - MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); + const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA); + MachineInstr *Orig = MRI->getVRegDef(regB); + const TargetInstrDesc &OrigTID = Orig->getDesc(); + bool SawStore = false; + + if (EnableReMat && Orig && Orig->isSafeToMove(TII, SawStore) && + OrigTID.isAsCheapAsAMove() && !OrigTID.mayLoad() && + !OrigTID.isSimpleLoad()) { + DEBUG(cerr << "2addr: REMATTING : " << *Orig << "\n"); + TII->reMaterialize(*mbbi, mi, regA, Orig); + ReMattedInstrs.insert(Orig); + } else { + TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc); + } MachineBasicBlock::iterator prevMi = prior(mi); DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); - // Update live variables for regA - LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); - varInfo.DefInst = prevMi; + // Update live variables for regB. + LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB); + + // regB is used in this BB. + varInfoB.UsedBlocks[mbbi->getNumber()] = true; - if (LV.removeVirtualRegisterKilled(regB, mbbi, mi)) - LV.addVirtualRegisterKilled(regB, prevMi); + if (LV->removeVirtualRegisterKilled(regB, mbbi, mi)) + LV->addVirtualRegisterKilled(regB, prevMi); - if (LV.removeVirtualRegisterDead(regB, mbbi, mi)) - LV.addVirtualRegisterDead(regB, prevMi); + if (LV->removeVirtualRegisterDead(regB, mbbi, mi)) + LV->addVirtualRegisterDead(regB, prevMi); - // replace all occurences of regB with regA + // Replace all occurences of regB with regA. for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { if (mi->getOperand(i).isRegister() && mi->getOperand(i).getReg() == regB) @@ -222,6 +372,38 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM)); } + + mi = nmi; + } + } + + if (EnableReMat) { + // Check to see if the instructions that we rematerialized are now dead. If + // they are, expunge them here. + SmallPtrSet::iterator I = ReMattedInstrs.begin(); + SmallPtrSet::iterator E = ReMattedInstrs.end(); + + for (; I != E; ++I) { + MachineInstr *MI = *I; + bool InstrDead = true; + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isRegister()) + continue; + unsigned MOReg = MO.getReg(); + + if (!MOReg || !MO.isDef() || (MO.isImplicit() && MO.isDead())) + continue; + + if (MRI->use_begin(MOReg) != MRI->use_end()) { + InstrDead = false; + break; + } + } + + if (InstrDead) + MI->eraseFromParent(); } }