X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FVirtRegMap.cpp;h=e2dc636e69119c00377748613022631b4aada493;hb=58b1ac76d470eb5faa7e98feae97c4906d4d146e;hp=5650e3d01fa3edc44a37dfa3dab816056cfa60ca;hpb=e4b39007c9d3056334264eba9e2e6025e241d2c5;p=oota-llvm.git diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 5650e3d01fa..e2dc636e691 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -21,41 +21,49 @@ #include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" #include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" #include using namespace llvm; -STATISTIC(NumSpills, "Number of register spills"); -STATISTIC(NumReMats, "Number of re-materialization"); -STATISTIC(NumDRM , "Number of re-materializable defs elided"); -STATISTIC(NumStores, "Number of stores added"); -STATISTIC(NumLoads , "Number of loads added"); -STATISTIC(NumReused, "Number of values reused"); -STATISTIC(NumDSE , "Number of dead stores elided"); -STATISTIC(NumDCE , "Number of copies elided"); +STATISTIC(NumSpills , "Number of register spills"); +STATISTIC(NumPSpills , "Number of physical register spills"); +STATISTIC(NumReMats , "Number of re-materialization"); +STATISTIC(NumDRM , "Number of re-materializable defs elided"); +STATISTIC(NumStores , "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); +STATISTIC(NumReused , "Number of values reused"); +STATISTIC(NumDSE , "Number of dead stores elided"); +STATISTIC(NumDCE , "Number of copies elided"); +STATISTIC(NumDSS , "Number of dead spill slots removed"); +STATISTIC(NumCommutes, "Number of instructions commuted"); +STATISTIC(NumOmitted , "Number of reloads omited"); +STATISTIC(NumCopified, "Number of available reloads turned into copies"); namespace { enum SpillerName { simple, local }; - - static cl::opt - SpillerOpt("spiller", - cl::desc("Spiller to use: (default: local)"), - cl::Prefix, - cl::values(clEnumVal(simple, " simple spiller"), - clEnumVal(local, " local spiller"), - clEnumValEnd), - cl::init(local)); } +static cl::opt +SpillerOpt("spiller", + cl::desc("Spiller to use: (default: local)"), + cl::Prefix, + cl::values(clEnumVal(simple, "simple spiller"), + clEnumVal(local, "local spiller"), + clEnumValEnd), + cl::init(local)); + //===----------------------------------------------------------------------===// // VirtRegMap implementation //===----------------------------------------------------------------------===// @@ -64,43 +72,56 @@ VirtRegMap::VirtRegMap(MachineFunction &mf) : TII(*mf.getTarget().getInstrInfo()), MF(mf), Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), - ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) { + Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), + LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { + SpillSlotToUsesMap.resize(8); + ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- + TargetRegisterInfo::FirstVirtualRegister); grow(); } void VirtRegMap::grow() { - unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); + unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); Virt2PhysMap.grow(LastVirtReg); Virt2StackSlotMap.grow(LastVirtReg); Virt2ReMatIdMap.grow(LastVirtReg); Virt2SplitMap.grow(LastVirtReg); + Virt2SplitKillMap.grow(LastVirtReg); ReMatMap.grow(LastVirtReg); + ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1); } int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); - int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), - RC->getAlignment()); - Virt2StackSlotMap[virtReg] = frameIndex; + const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); + int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); + if (LowSpillSlot == NO_STACK_SLOT) + LowSpillSlot = SS; + if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) + HighSpillSlot = SS; + unsigned Idx = SS-LowSpillSlot; + while (Idx >= SpillSlotToUsesMap.size()) + SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); + Virt2StackSlotMap[virtReg] = SS; ++NumSpills; - return frameIndex; + return SS; } -void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); +void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - assert((frameIndex >= 0 || - (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && + assert((SS >= 0 || + (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && "illegal fixed frame index"); - Virt2StackSlotMap[virtReg] = frameIndex; + Virt2StackSlotMap[virtReg] = SS; } int VirtRegMap::assignVirtReMatId(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = ReMatId; @@ -108,12 +129,40 @@ int VirtRegMap::assignVirtReMatId(unsigned virtReg) { } void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = id; } +int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { + std::map::iterator I = + EmergencySpillSlots.find(RC); + if (I != EmergencySpillSlots.end()) + return I->second; + int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); + if (LowSpillSlot == NO_STACK_SLOT) + LowSpillSlot = SS; + if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) + HighSpillSlot = SS; + EmergencySpillSlots[RC] = SS; + return SS; +} + +void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { + if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { + // If FI < LowSpillSlot, this stack reference was produced by + // instruction selection and is not a spill + if (FI >= LowSpillSlot) { + assert(FI >= 0 && "Spill slot index should not be negative!"); + assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() + && "Invalid spill slot"); + SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); + } + } +} + void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI, ModRef MRInfo) { // Move previous memory references folded to new instruction. @@ -133,26 +182,48 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); } +void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isFI()) + continue; + int FI = MO.getIndex(); + if (MF.getFrameInfo()->isFixedObjectIndex(FI)) + continue; + // This stack reference was produced by instruction selection and + // is not a spill + if (FI < LowSpillSlot) + continue; + assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() + && "Invalid spill slot"); + SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); + } + MI2VirtMap.erase(MI); + SpillPt2VirtMap.erase(MI); + RestorePt2VirtMap.erase(MI); + EmergencySpillMap.erase(MI); +} + void VirtRegMap::print(std::ostream &OS) const { - const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); OS << "********** REGISTER MAP **********\n"; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, + e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) - OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; - + OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) + << "]\n"; } - for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, + e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; OS << '\n'; } void VirtRegMap::dump() const { - print(DOUT); + print(cerr); } @@ -172,7 +243,9 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { DOUT << "********** REWRITE MACHINE CODE **********\n"; DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); + const TargetInstrInfo &TII = *TM.getInstrInfo(); + const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); + // LoadedRegs - Keep track of which vregs are loaded, so that we only load // each vreg once (in the case where a spilled vreg is used by multiple @@ -189,34 +262,42 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { MachineInstr &MI = *MII; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isRegister() && MO.getReg()) - if (MRegisterInfo::isVirtualRegister(MO.getReg())) { + if (MO.isReg() && MO.getReg()) { + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); + unsigned SubIdx = MO.getSubReg(); unsigned PhysReg = VRM.getPhys(VirtReg); + unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg; if (!VRM.isAssignedReg(VirtReg)) { int StackSlot = VRM.getStackSlot(VirtReg); const TargetRegisterClass* RC = - MF.getSSARegMap()->getRegClass(VirtReg); + MF.getRegInfo().getRegClass(VirtReg); if (MO.isUse() && std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) == LoadedRegs.end()) { - MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); + TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); + MachineInstr *LoadMI = prior(MII); + VRM.addSpillSlotUse(StackSlot, LoadMI); LoadedRegs.push_back(VirtReg); ++NumLoads; - DOUT << '\t' << *prior(MII); + DOUT << '\t' << *LoadMI; } if (MO.isDef()) { - MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); + TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, + StackSlot, RC); + MachineInstr *StoreMI = next(MII); + VRM.addSpillSlotUse(StackSlot, StoreMI); ++NumStores; } } - MF.setPhysRegUsed(PhysReg); - MI.getOperand(i).setReg(PhysReg); + MF.getRegInfo().setPhysRegUsed(RReg); + MI.getOperand(i).setReg(RReg); } else { - MF.setPhysRegUsed(MO.getReg()); + MF.getRegInfo().setPhysRegUsed(MO.getReg()); } + } } DOUT << '\t' << MI; @@ -230,57 +311,6 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { // Local Spiller Implementation //===----------------------------------------------------------------------===// -namespace { - class AvailableSpills; - - /// LocalSpiller - This spiller does a simple pass over the machine basic - /// block to attempt to keep spills in registers as much as possible for - /// blocks that have low register pressure (the vreg may be spilled due to - /// register pressure in other blocks). - class VISIBILITY_HIDDEN LocalSpiller : public Spiller { - SSARegMap *RegMap; - const MRegisterInfo *MRI; - const TargetInstrInfo *TII; - public: - bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { - RegMap = MF.getSSARegMap(); - MRI = MF.getTarget().getRegisterInfo(); - TII = MF.getTarget().getInstrInfo(); - DOUT << "\n**** Local spiller rewriting function '" - << MF.getFunction()->getName() << "':\n"; - DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n"; - DEBUG(MF.dump()); - - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB) - RewriteMBB(*MBB, VRM); - - DOUT << "**** Post Machine Instrs ****\n"; - DEBUG(MF.dump()); - - return true; - } - private: - bool PrepForUnfoldOpti(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - std::vector &MaybeDeadStores, - AvailableSpills &Spills, BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - void SpillRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, - int Idx, unsigned PhysReg, int StackSlot, - const TargetRegisterClass *RC, - MachineInstr *&LastStore, - AvailableSpills &Spills, - SmallSet &ReMatDefs, - BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM); - void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); - }; -} - /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from /// top down, keep track of which spills slots or remat are available in each /// register. @@ -294,7 +324,7 @@ namespace { /// this bit and addAvailable sets it if. namespace { class VISIBILITY_HIDDEN AvailableSpills { - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled @@ -312,11 +342,17 @@ class VISIBILITY_HIDDEN AvailableSpills { void ClobberPhysRegOnly(unsigned PhysReg); public: - AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) - : MRI(mri), TII(tii) { + AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) + : TRI(tri), TII(tii) { + } + + /// clear - Reset the state. + void clear() { + SpillSlotsOrReMatsAvailable.clear(); + PhysRegsAvailable.clear(); } - const MRegisterInfo *getRegInfo() const { return MRI; } + const TargetRegisterInfo *getRegInfo() const { return TRI; } /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is /// available in a physical register, return that PhysReg, otherwise @@ -333,8 +369,7 @@ public: /// addAvailable - Mark that the specified stack slot / remat is available in /// the specified physreg. If CanClobber is true, the physreg can be modified /// at any time without changing the semantics of the program. - void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, - bool CanClobber = true) { + void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) { // If this stack slot is thought to be available in some other physreg, // remove its record. ModifyStackSlotOrReMat(SlotOrReMat); @@ -346,7 +381,7 @@ public: DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Remembering SS#" << SlotOrReMat; - DOUT << " in physreg " << MRI->getName(Reg) << "\n"; + DOUT << " in physreg " << TRI->getName(Reg) << "\n"; } /// canClobberPhysReg - Return true if the spiller is allowed to change the @@ -357,7 +392,7 @@ public: "Value not available!"); return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; } - + /// disallowClobberPhysReg - Unset the CanClobber bit of the specified /// stackslot register. The register is still available but is no longer /// allowed to be modifed. @@ -372,6 +407,8 @@ public: /// slot changes. This removes information about which register the previous /// value for this slot lives in (as the previous value is dead now). void ModifyStackSlotOrReMat(int SlotOrReMat); + + void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB); }; } @@ -387,7 +424,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " copied, it is available for use but can no longer be modified\n"; } } @@ -396,7 +433,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { /// stackslot register and its aliases. The register and its aliases may /// still available but is no longer allowed to be modifed. void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) disallowClobberPhysRegOnly(*AS); disallowClobberPhysRegOnly(PhysReg); } @@ -412,7 +449,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " clobbered, invalidating "; if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; @@ -425,7 +462,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { /// value. We use this to invalidate any info about stuff we thing lives in /// it and any of its aliases. void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) ClobberPhysRegOnly(*AS); ClobberPhysRegOnly(PhysReg); } @@ -451,7 +488,148 @@ void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { PhysRegsAvailable.erase(I); } +/// AddAvailableRegsToLiveIn - Availability information is being kept coming +/// into the specified MBB. Add available physical registers as live-in's +/// so register scavenger and post-allocation scheduler are happy. +void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB) { + for (std::multimap::iterator + I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end(); + I != E; ++I) { + unsigned Reg = (*I).first; + const TargetRegisterClass* RC = TRI->getPhysicalRegisterRegClass(Reg); + // FIXME: A temporary workaround. We can't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. Do not add it as a live-in. + if (!TII->isSafeToMoveRegClassDefs(RC)) + continue; + if (!MBB.isLiveIn(Reg)) + MBB.addLiveIn(Reg); + } +} + +/// findSinglePredSuccessor - Return via reference a vector of machine basic +/// blocks each of which is a successor of the specified BB and has no other +/// predecessor. +static void findSinglePredSuccessor(MachineBasicBlock *MBB, + SmallVectorImpl &Succs) { + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock *SuccMBB = *SI; + if (SuccMBB->pred_size() == 1) + Succs.push_back(SuccMBB); + } +} + +namespace { + /// LocalSpiller - This spiller does a simple pass over the machine basic + /// block to attempt to keep spills in registers as much as possible for + /// blocks that have low register pressure (the vreg may be spilled due to + /// register pressure in other blocks). + class VISIBILITY_HIDDEN LocalSpiller : public Spiller { + MachineRegisterInfo *RegInfo; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + DenseMap DistanceMap; + public: + bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { + RegInfo = &MF.getRegInfo(); + TRI = MF.getTarget().getRegisterInfo(); + TII = MF.getTarget().getInstrInfo(); + DOUT << "\n**** Local spiller rewriting function '" + << MF.getFunction()->getName() << "':\n"; + DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" + " ****\n"; + DEBUG(MF.dump()); + + // Spills - Keep track of which spilled values are available in physregs + // so that we can choose to reuse the physregs instead of emitting + // reloads. This is usually refreshed per basic block. + AvailableSpills Spills(TRI, TII); + + // SingleEntrySuccs - Successor blocks which have a single predecessor. + SmallVector SinglePredSuccs; + SmallPtrSet EarlyVisited; + + // Traverse the basic blocks depth first. + MachineBasicBlock *Entry = MF.begin(); + SmallPtrSet Visited; + for (df_ext_iterator > + DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); + DFI != E; ++DFI) { + MachineBasicBlock *MBB = *DFI; + if (!EarlyVisited.count(MBB)) + RewriteMBB(*MBB, VRM, Spills); + + // If this MBB is the only predecessor of a successor. Keep the + // availability information and visit it next. + do { + // Keep visiting single predecessor successor as long as possible. + SinglePredSuccs.clear(); + findSinglePredSuccessor(MBB, SinglePredSuccs); + if (SinglePredSuccs.empty()) + MBB = 0; + else { + // FIXME: More than one successors, each of which has MBB has + // the only predecessor. + MBB = SinglePredSuccs[0]; + if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) { + Spills.AddAvailableRegsToLiveIn(*MBB); + RewriteMBB(*MBB, VRM, Spills); + } + } + } while (MBB); + + // Clear the availability info. + Spills.clear(); + } + + DOUT << "**** Post Machine Instrs ****\n"; + DEBUG(MF.dump()); + + // Mark unused spill slots. + MachineFrameInfo *MFI = MF.getFrameInfo(); + int SS = VRM.getLowSpillSlot(); + if (SS != VirtRegMap::NO_STACK_SLOT) + for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) + if (!VRM.isSpillSlotUsed(SS)) { + MFI->RemoveStackObject(SS); + ++NumDSS; + } + return true; + } + private: + void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, + unsigned Reg, BitVector &RegKills, + std::vector &KillOps); + bool PrepForUnfoldOpti(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + std::vector &MaybeDeadStores, + AvailableSpills &Spills, BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + bool CommuteToFoldReload(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + unsigned VirtReg, unsigned SrcReg, int SS, + BitVector &RegKills, + std::vector &KillOps, + const TargetRegisterInfo *TRI, + VirtRegMap &VRM); + void SpillRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + int Idx, unsigned PhysReg, int StackSlot, + const TargetRegisterClass *RC, + bool isAvailable, MachineInstr *&LastStore, + AvailableSpills &Spills, + SmallSet &ReMatDefs, + BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM); + void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills); + }; +} /// InvalidateKills - MI is going to be deleted. If any of its operands are /// marked kill, then invalidate the information. @@ -460,11 +638,14 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, SmallVector *KillRegs = NULL) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) + if (!MO.isReg() || !MO.isUse() || !MO.isKill()) continue; unsigned Reg = MO.getReg(); + if (TargetRegisterInfo::isVirtualRegister(Reg)) + continue; if (KillRegs) KillRegs->push_back(Reg); + assert(Reg < KillOps.size()); if (KillOps[Reg] == &MO) { RegKills.reset(Reg); KillOps[Reg] = NULL; @@ -472,6 +653,17 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, } } +/// InvalidateKill - A MI that defines the specified register is being deleted, +/// invalidate the register kill information. +static void InvalidateKill(unsigned Reg, BitVector &RegKills, + std::vector &KillOps) { + if (RegKills[Reg]) { + KillOps[Reg]->setIsKill(false); + KillOps[Reg] = NULL; + RegKills.reset(Reg); + } +} + /// InvalidateRegDef - If the def operand of the specified def MI is now dead /// (since it's spill instruction is removed), mark it isDead. Also checks if /// the def MI has other definition operands that are not dead. Returns it by @@ -485,7 +677,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, MachineOperand *DefOp = NULL; for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = DefMI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { if (MO.getReg() == Reg) DefOp = &MO; else if (!MO.isDead()) @@ -496,13 +688,13 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, return false; bool FoundUse = false, Done = false; - MachineBasicBlock::iterator E = NewDef; + MachineBasicBlock::iterator E = &NewDef; ++I; ++E; for (; !Done && I != E; ++I) { MachineInstr *NMI = I; for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = NMI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != Reg) + if (!MO.isReg() || MO.getReg() != Reg) continue; if (MO.isUse()) FoundUse = true; @@ -521,26 +713,28 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, /// marked kill, then it must be due to register reuse. Transfer the kill info /// over. static void UpdateKills(MachineInstr &MI, BitVector &RegKills, - std::vector &KillOps) { - const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); + std::vector &KillOps, + const TargetRegisterInfo* TRI) { + const TargetInstrDesc &TID = MI.getDesc(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - if (RegKills[Reg]) { + if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { // That can't be right. Register is killed but not re-defined and it's // being reused. Let's fix that. - KillOps[Reg]->unsetIsKill(); - if (i < TID->numOperands && - TID->getOperandConstraint(i, TOI::TIED_TO) == -1) + KillOps[Reg]->setIsKill(false); + KillOps[Reg] = NULL; + RegKills.reset(Reg); + if (i < TID.getNumOperands() && + TID.getOperandConstraint(i, TOI::TIED_TO) == -1) // Unless it's a two-address operand, this is the new kill. MO.setIsKill(); } - if (MO.isKill()) { RegKills.set(Reg); KillOps[Reg] = &MO; @@ -549,12 +743,44 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills, for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); RegKills.reset(Reg); KillOps[Reg] = NULL; + // It also defines (or partially define) aliases. + for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { + RegKills.reset(*AS); + KillOps[*AS] = NULL; + } + } +} + +/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. +/// +static void ReMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + unsigned DestReg, unsigned Reg, + const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI, + VirtRegMap &VRM) { + TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); + MachineInstr *NewMI = prior(MII); + for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = NewMI->getOperand(i); + if (!MO.isReg() || MO.getReg() == 0) + continue; + unsigned VirtReg = MO.getReg(); + if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) + continue; + assert(MO.isUse()); + unsigned SubIdx = MO.getSubReg(); + unsigned Phys = VRM.getPhys(VirtReg); + assert(Phys); + unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; + MO.setReg(RReg); } + ++NumReMats; } @@ -590,8 +816,8 @@ namespace { std::vector Reuses; BitVector PhysRegsClobbered; public: - ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { - PhysRegsClobbered.resize(mri->getNumRegs()); + ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { + PhysRegsClobbered.resize(tri->getNumRegs()); } bool hasReuses() const { @@ -630,6 +856,9 @@ namespace { BitVector &RegKills, std::vector &KillOps, VirtRegMap &VRM) { + const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() + .getInstrInfo(); + if (Reuses.empty()) return PhysReg; // This is most often empty. for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { @@ -651,14 +880,14 @@ namespace { // value aliases the new register. If so, codegen the previous reload // and use this one. unsigned PRRU = Op.PhysRegReused; - const MRegisterInfo *MRI = Spills.getRegInfo(); - if (MRI->areAliases(PRRU, PhysReg)) { + const TargetRegisterInfo *TRI = Spills.getRegInfo(); + if (TRI->areAliases(PRRU, PhysReg)) { // Okay, we found out that an alias of a reused register // was used. This isn't good because it means we have // to undo a previous reuse. MachineBasicBlock *MBB = MI->getParent(); const TargetRegisterClass *AliasRC = - MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); + MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); // Copy Op out of the vector and remove it, we're going to insert an // explicit load for it. @@ -673,26 +902,28 @@ namespace { MI, Spills, MaybeDeadStores, Rejected, RegKills, KillOps, VRM); + MachineBasicBlock::iterator MII = MI; if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { - MRI->reMaterialize(*MBB, MI, NewPhysReg, - VRM.getReMaterializedMI(NewOp.VirtReg)); - ++NumReMats; + ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM); } else { - MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, + TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, NewOp.StackSlotOrReMat, AliasRC); + MachineInstr *LoadMI = prior(MII); + VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); // Any stores to this stack slot are not dead anymore. MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; ++NumLoads; } Spills.ClobberPhysReg(NewPhysReg); Spills.ClobberPhysReg(NewOp.PhysRegReused); + + unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg(); + unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; + MI->getOperand(NewOp.Operand).setReg(RReg); - MI->getOperand(NewOp.Operand).setReg(NewPhysReg); - - Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); - MachineBasicBlock::iterator MII = MI; + Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg); --MII; - UpdateKills(*MII, RegKills, KillOps); + UpdateKills(*MII, RegKills, KillOps, TRI); DOUT << '\t' << *MII; DOUT << "Reuse undone!\n"; @@ -735,7 +966,7 @@ namespace { /// xorl %edi, %eax /// movl %eax, -32(%ebp) /// movl -36(%ebp), %eax -/// orl %eax, -32(%ebp) +/// orl %eax, -32(%ebp) /// ==> /// xorl %edi, %eax /// orl -36(%ebp), %eax @@ -743,12 +974,12 @@ namespace { /// This enables unfolding optimization for a subsequent instruction which will /// also eliminate the newly introduced store instruction. bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MII, + MachineBasicBlock::iterator &MII, std::vector &MaybeDeadStores, - AvailableSpills &Spills, - BitVector &RegKills, - std::vector &KillOps, - VirtRegMap &VRM) { + AvailableSpills &Spills, + BitVector &RegKills, + std::vector &KillOps, + VirtRegMap &VRM) { MachineFunction &MF = *MBB.getParent(); MachineInstr &MI = *MII; unsigned UnfoldedOpc = 0; @@ -756,12 +987,15 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, unsigned UnfoldVR = 0; int FoldedSS = VirtRegMap::NO_STACK_SLOT; VirtRegMap::MI2VirtMapTy::const_iterator I, End; - for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { + for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { // Only transform a MI that folds a single register. if (UnfoldedOpc) return false; UnfoldVR = I->second.first; VirtRegMap::ModRef MR = I->second.second; + // MI2VirtMap be can updated which invalidate the iterator. + // Increment the iterator first. + ++I; if (VRM.isAssignedReg(UnfoldVR)) continue; // If this reference is not a use, any previous store is now dead. @@ -770,11 +1004,10 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; if (DeadStore && (MR & VirtRegMap::isModRef)) { unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); - if (!PhysReg || - DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1) + if (!PhysReg || !DeadStore->readsRegister(PhysReg)) continue; UnfoldPR = PhysReg; - UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(), + UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), false, true); } } @@ -784,27 +1017,29 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) + if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse()) continue; unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) + if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) continue; if (VRM.isAssignedReg(VirtReg)) { unsigned PhysReg = VRM.getPhys(VirtReg); - if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR)) + if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) return false; } else if (VRM.isReMaterialized(VirtReg)) continue; int SS = VRM.getStackSlot(VirtReg); unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); if (PhysReg) { - if (MRI->regsOverlap(PhysReg, UnfoldPR)) + if (TRI->regsOverlap(PhysReg, UnfoldPR)) return false; continue; } - PhysReg = VRM.getPhys(VirtReg); - if (!MRI->regsOverlap(PhysReg, UnfoldPR)) - continue; + if (VRM.hasPhys(VirtReg)) { + PhysReg = VRM.getPhys(VirtReg); + if (!TRI->regsOverlap(PhysReg, UnfoldPR)) + continue; + } // Ok, we'll need to reload the value into a register which makes // it impossible to perform the store unfolding optimization later. @@ -812,38 +1047,128 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, // unfolded. This allows us to perform the store unfolding // optimization. SmallVector NewMIs; - if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { + if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { assert(NewMIs.size() == 1); MachineInstr *NewMI = NewMIs.back(); NewMIs.clear(); - int Idx = NewMI->findRegisterUseOperandIdx(VirtReg); + int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); assert(Idx != -1); - SmallVector Ops; + SmallVector Ops; Ops.push_back(Idx); - MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS); + MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); if (FoldedMI) { + VRM.addSpillSlotUse(SS, FoldedMI); if (!VRM.hasPhys(UnfoldVR)) VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); MII = MBB.insert(MII, FoldedMI); + InvalidateKills(MI, RegKills, KillOps); VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); + MF.DeleteMachineInstr(NewMI); return true; } - delete NewMI; + MF.DeleteMachineInstr(NewMI); } } return false; } +/// CommuteToFoldReload - +/// Look for +/// r1 = load fi#1 +/// r1 = op r1, r2 +/// store r1, fi#1 +/// +/// If op is commutable and r2 is killed, then we can xform these to +/// r2 = op r2, fi#1 +/// store r2, fi#1 +bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MII, + unsigned VirtReg, unsigned SrcReg, int SS, + BitVector &RegKills, + std::vector &KillOps, + const TargetRegisterInfo *TRI, + VirtRegMap &VRM) { + if (MII == MBB.begin() || !MII->killsRegister(SrcReg)) + return false; + + MachineFunction &MF = *MBB.getParent(); + MachineInstr &MI = *MII; + MachineBasicBlock::iterator DefMII = prior(MII); + MachineInstr *DefMI = DefMII; + const TargetInstrDesc &TID = DefMI->getDesc(); + unsigned NewDstIdx; + if (DefMII != MBB.begin() && + TID.isCommutable() && + TII->CommuteChangesDestination(DefMI, NewDstIdx)) { + MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); + unsigned NewReg = NewDstMO.getReg(); + if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg)) + return false; + MachineInstr *ReloadMI = prior(DefMII); + int FrameIdx; + unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx); + if (DestReg != SrcReg || FrameIdx != SS) + return false; + int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false); + if (UseIdx == -1) + return false; + int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO); + if (DefIdx == -1) + return false; + assert(DefMI->getOperand(DefIdx).isReg() && + DefMI->getOperand(DefIdx).getReg() == SrcReg); + + // Now commute def instruction. + MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true); + if (!CommutedMI) + return false; + SmallVector Ops; + Ops.push_back(NewDstIdx); + MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS); + // Not needed since foldMemoryOperand returns new MI. + MF.DeleteMachineInstr(CommutedMI); + if (!FoldedMI) + return false; + + VRM.addSpillSlotUse(SS, FoldedMI); + VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); + // Insert new def MI and spill MI. + const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); + TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC); + MII = prior(MII); + MachineInstr *StoreMI = MII; + VRM.addSpillSlotUse(SS, StoreMI); + VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); + MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack. + + // Delete all 3 old instructions. + InvalidateKills(*ReloadMI, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(ReloadMI); + MBB.erase(ReloadMI); + InvalidateKills(*DefMI, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(DefMI); + MBB.erase(DefMI); + InvalidateKills(MI, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(&MI); + MBB.erase(&MI); + + ++NumCommutes; + return true; + } + + return false; +} + /// findSuperReg - Find the SubReg's super-register of given register class /// where its SubIdx sub-register is SubReg. static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, - unsigned SubIdx, const MRegisterInfo *MRI) { + unsigned SubIdx, const TargetRegisterInfo *TRI) { for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) { unsigned Reg = *I; - if (MRI->getSubReg(Reg, SubIdx) == SubReg) + if (TRI->getSubReg(Reg, SubIdx) == SubReg) return Reg; } return 0; @@ -855,14 +1180,16 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MII, int Idx, unsigned PhysReg, int StackSlot, const TargetRegisterClass *RC, - MachineInstr *&LastStore, + bool isAvailable, MachineInstr *&LastStore, AvailableSpills &Spills, SmallSet &ReMatDefs, BitVector &RegKills, std::vector &KillOps, VirtRegMap &VRM) { - MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); - DOUT << "Store:\t" << *next(MII); + TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); + MachineInstr *StoreMI = next(MII); + VRM.addSpillSlotUse(StackSlot, StoreMI); + DOUT << "Store:\t" << *StoreMI; // If there is a dead store to this stack slot, nuke it now. if (LastStore) { @@ -874,8 +1201,8 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, bool CheckDef = PrevMII != MBB.begin(); if (CheckDef) --PrevMII; - MBB.erase(LastStore); VRM.RemoveMachineInstrFromMaps(LastStore); + MBB.erase(LastStore); if (CheckDef) { // Look at defs of killed registers on the store. Mark the defs // as dead since the store has been deleted and they aren't @@ -887,8 +1214,8 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, if (ReMatDefs.count(DeadDef) && !HasOtherDef) { // FIXME: This assumes a remat def does not have side // effects. - MBB.erase(DeadDef); VRM.RemoveMachineInstrFromMaps(DeadDef); + MBB.erase(DeadDef); ++NumDRM; } } @@ -903,20 +1230,61 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, // in PhysReg. Spills.ModifyStackSlotOrReMat(StackSlot); Spills.ClobberPhysReg(PhysReg); - Spills.addAvailable(StackSlot, LastStore, PhysReg); + Spills.addAvailable(StackSlot, PhysReg, isAvailable); ++NumStores; } +/// TransferDeadness - A identity copy definition is dead and it's being +/// removed. Find the last def or use and mark it as dead / kill. +void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, + unsigned Reg, BitVector &RegKills, + std::vector &KillOps) { + int LastUDDist = -1; + MachineInstr *LastUDMI = NULL; + for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg), + RE = RegInfo->reg_end(); RI != RE; ++RI) { + MachineInstr *UDMI = &*RI; + if (UDMI->getParent() != MBB) + continue; + DenseMap::iterator DI = DistanceMap.find(UDMI); + if (DI == DistanceMap.end() || DI->second > CurDist) + continue; + if ((int)DI->second < LastUDDist) + continue; + LastUDDist = DI->second; + LastUDMI = UDMI; + } + + if (LastUDMI) { + const TargetInstrDesc &TID = LastUDMI->getDesc(); + MachineOperand *LastUD = NULL; + for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = LastUDMI->getOperand(i); + if (!MO.isReg() || MO.getReg() != Reg) + continue; + if (!LastUD || (LastUD->isUse() && MO.isDef())) + LastUD = &MO; + if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) + return; + } + if (LastUD->isDef()) + LastUD->setIsDead(); + else { + LastUD->setIsKill(); + RegKills.set(Reg); + KillOps[Reg] = LastUD; + } + } +} + /// rewriteMBB - Keep track of which spills are available even after the /// register allocator is done with them. If possible, avid reloading vregs. -void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { - DOUT << MBB.getBasicBlock()->getName() << ":\n"; +void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, + AvailableSpills &Spills) { + DOUT << "\n**** Local spiller rewriting MBB '" + << MBB.getBasicBlock()->getName() << ":\n"; MachineFunction &MF = *MBB.getParent(); - - // Spills - Keep track of which spilled values are available in physregs so - // that we can choose to reuse the physregs instead of emitting reloads. - AvailableSpills Spills(MRI, TII); // MaybeDeadStores - When we need to write a value back into a stack slot, // keep track of the inserted store. If the stack slot value is never read @@ -931,10 +1299,12 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { SmallSet ReMatDefs; // Keep track of kill information. - BitVector RegKills(MRI->getNumRegs()); + BitVector RegKills(TRI->getNumRegs()); std::vector KillOps; - KillOps.resize(MRI->getNumRegs(), NULL); + KillOps.resize(TRI->getNumRegs(), NULL); + unsigned Dist = 0; + DistanceMap.clear(); for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); MII != E; ) { MachineBasicBlock::iterator NextMII = MII; ++NextMII; @@ -947,85 +1317,193 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { NextMII = next(MII); MachineInstr &MI = *MII; - const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); + const TargetInstrDesc &TID = MI.getDesc(); + + if (VRM.hasEmergencySpills(&MI)) { + // Spill physical register(s) in the rare case the allocator has run out + // of registers to allocate. + SmallSet UsedSS; + std::vector &EmSpills = VRM.getEmergencySpills(&MI); + for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { + unsigned PhysReg = EmSpills[i]; + const TargetRegisterClass *RC = + TRI->getPhysicalRegisterRegClass(PhysReg); + assert(RC && "Unable to determine register class!"); + int SS = VRM.getEmergencySpillSlot(RC); + if (UsedSS.count(SS)) + assert(0 && "Need to spill more than one physical registers!"); + UsedSS.insert(SS); + TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); + MachineInstr *StoreMI = prior(MII); + VRM.addSpillSlotUse(SS, StoreMI); + TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); + MachineInstr *LoadMI = next(MII); + VRM.addSpillSlotUse(SS, LoadMI); + ++NumPSpills; + } + NextMII = next(MII); + } // Insert restores here if asked to. if (VRM.isRestorePt(&MI)) { std::vector &RestoreRegs = VRM.getRestorePtRestores(&MI); for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { - unsigned VirtReg = RestoreRegs[i]; + unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. if (!VRM.getPreSplitReg(VirtReg)) continue; // Split interval spilled again. unsigned Phys = VRM.getPhys(VirtReg); - MF.setPhysRegUsed(Phys); + RegInfo->setPhysRegUsed(Phys); + + // Check if the value being restored if available. If so, it must be + // from a predecessor BB that fallthrough into this BB. We do not + // expect: + // BB1: + // r1 = load fi#1 + // ... + // = r1 + // ... # r1 not clobbered + // ... + // = load fi#1 + bool DoReMat = VRM.isReMaterialized(VirtReg); + int SSorRMId = DoReMat + ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + // FIXME: A temporary workaround. Don't reuse available value if it's + // not safe to move the def of the virtual register's class. e.g. + // X86::RFP* register classes. + unsigned InReg = TII->isSafeToMoveRegClassDefs(RC) ? + Spills.getSpillSlotOrReMatPhysReg(SSorRMId) : 0; + if (InReg == Phys) { + // If the value is already available in the expected register, save + // a reload / remat. + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" instead of reloading into physreg " + << TRI->getName(Phys) << "\n"; + ++NumOmitted; + continue; + } else if (InReg && InReg != Phys) { + if (SSorRMId) + DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; + else + DOUT << "Reusing SS#" << SSorRMId; + DOUT << " from physreg " + << TRI->getName(InReg) << " for vreg" + << VirtReg <<" by copying it into physreg " + << TRI->getName(Phys) << "\n"; + + // If the reloaded / remat value is available in another register, + // copy it to the desired register. + TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); + + // This invalidates Phys. + Spills.ClobberPhysReg(Phys); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + + // Mark is killed. + MachineInstr *CopyMI = prior(MII); + MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg); + KillOpnd->setIsKill(); + UpdateKills(*CopyMI, RegKills, KillOps, TRI); + + DOUT << '\t' << *CopyMI; + ++NumCopified; + continue; + } + if (VRM.isReMaterialized(VirtReg)) { - MRI->reMaterialize(MBB, &MI, Phys, - VRM.getReMaterializedMI(VirtReg)); - ++NumReMats; + ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); } else { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); - MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC); + MachineInstr *LoadMI = prior(MII); + VRM.addSpillSlotUse(SSorRMId, LoadMI); ++NumLoads; } + // This invalidates Phys. Spills.ClobberPhysReg(Phys); - UpdateKills(*prior(MII), RegKills, KillOps); + // Remember it's available. + Spills.addAvailable(SSorRMId, Phys); + + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } } // Insert spills here if asked to. if (VRM.isSpillPt(&MI)) { - std::vector &SpillRegs = VRM.getSpillPtSpills(&MI); + std::vector > &SpillRegs = + VRM.getSpillPtSpills(&MI); for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { - unsigned VirtReg = SpillRegs[i]; + unsigned VirtReg = SpillRegs[i].first; + bool isKill = SpillRegs[i].second; if (!VRM.getPreSplitReg(VirtReg)) continue; // Split interval spilled again. - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); unsigned Phys = VRM.getPhys(VirtReg); int StackSlot = VRM.getStackSlot(VirtReg); - MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; - SpillRegToStackSlot(MBB, MII, i, Phys, StackSlot, RC, LastStore, - Spills, ReMatDefs, RegKills, KillOps, VRM); + TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); + MachineInstr *StoreMI = next(MII); + VRM.addSpillSlotUse(StackSlot, StoreMI); + DOUT << "Store:\t" << *StoreMI; + VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); } NextMII = next(MII); } /// ReusedOperands - Keep track of operand reuse in case we need to undo /// reuse. - ReuseInfo ReusedOperands(MI, MRI); - // Process all of the spilled uses and all non spilled reg references. + ReuseInfo ReusedOperands(MI, TRI); + SmallVector VirtUseOps; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || MO.getReg() == 0) + if (!MO.isReg() || MO.getReg() == 0) continue; // Ignore non-register operands. unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg)) { + if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { // Ignore physregs for spilling, but remember that it is used by this // function. - MF.setPhysRegUsed(VirtReg); + RegInfo->setPhysRegUsed(VirtReg); continue; } - - assert(MRegisterInfo::isVirtualRegister(VirtReg) && - "Not a virtual or a physical register?"); - // Assumes this is the last use of a split interval. IsKill will be unset - // if reg is use later unless it's a two-address operand. - if (MO.isUse() && VRM.getPreSplitReg(VirtReg) && - TID->getOperandConstraint(i, TOI::TIED_TO) == -1) - MI.getOperand(i).setIsKill(); + // We want to process implicit virtual register uses first. + if (MO.isImplicit()) + // If the virtual register is implicitly defined, emit a implicit_def + // before so scavenger knows it's "defined". + VirtUseOps.insert(VirtUseOps.begin(), i); + else + VirtUseOps.push_back(i); + } + + // Process all of the spilled uses and all non spilled reg references. + SmallVector PotentialDeadStoreSlots; + for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { + unsigned i = VirtUseOps[j]; + MachineOperand &MO = MI.getOperand(i); + unsigned VirtReg = MO.getReg(); + assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && + "Not a virtual register?"); unsigned SubIdx = MO.getSubReg(); if (VRM.isAssignedReg(VirtReg)) { // This virtual register was assigned a physreg! unsigned Phys = VRM.getPhys(VirtReg); - MF.setPhysRegUsed(Phys); + RegInfo->setPhysRegUsed(Phys); if (MO.isDef()) ReusedOperands.markClobbered(Phys); - unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; + unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; MI.getOperand(i).setReg(RReg); + if (VRM.isImplicitlyDefined(VirtReg)) + BuildMI(MBB, &MI, MI.getDebugLoc(), + TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); continue; } @@ -1040,14 +1518,6 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Check to see if this stack slot is available. unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); - if (!PhysReg && DoReMat) { - // This use is rematerializable. But perhaps the value is available in - // a register if the definition is not deleted. If so, check if we can - // reuse the value. - ReuseSlot = VRM.getStackSlot(VirtReg); - if (ReuseSlot != VirtRegMap::NO_STACK_SLOT) - PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot); - } // If this is a sub-register use, make sure the reuse register is in the // right register class. For example, for x86 not all of the 32-bit @@ -1061,7 +1531,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // the right register file. if (PhysReg && (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); if (!RC->contains(PhysReg)) PhysReg = 0; } @@ -1073,9 +1543,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // aren't allowed to modify the reused register. If none of these cases // apply, reuse it. bool CanReuse = true; - int ti = TID->getOperandConstraint(i, TOI::TIED_TO); + int ti = TID.getOperandConstraint(i, TOI::TIED_TO); if (ti != -1 && - MI.getOperand(ti).isRegister() && + MI.getOperand(ti).isReg() && MI.getOperand(ti).getReg() == VirtReg) { // Okay, we have a two address operand. We can reuse this physreg as // long as we are allowed to clobber the value and there isn't an @@ -1091,10 +1561,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { else DOUT << "Reusing SS#" << ReuseSlot; DOUT << " from physreg " - << MRI->getName(PhysReg) << " for vreg" + << TRI->getName(PhysReg) << " for vreg" << VirtReg <<" instead of reloading into physreg " - << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); // The only technical detail we have is that we don't know that @@ -1120,18 +1590,21 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (MI.getOperand(i).isKill() && ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { - // This was the last use and the spilled value is still available - // for reuse. That means the spill was unnecessary! - MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; - if (DeadStore) { - DOUT << "Removed dead store:\t" << *DeadStore; - InvalidateKills(*DeadStore, RegKills, KillOps); - VRM.RemoveMachineInstrFromMaps(DeadStore); - MBB.erase(DeadStore); - MaybeDeadStores[ReuseSlot] = NULL; - ++NumDSE; - } + + // The store of this spilled value is potentially dead, but we + // won't know for certain until we've confirmed that the re-use + // above is valid, which means waiting until the other operands + // are processed. For now we just track the spill slot, we'll + // remove it after the other operands are processed if valid. + + PotentialDeadStoreSlots.push_back(ReuseSlot); } + + // Assumes this is the last use. IsKill will be unset if reg is reused + // unless it's a two-address operand. + if (ti == -1) + MI.getOperand(i).setIsKill(); + continue; } // CanReuse @@ -1164,30 +1637,30 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Reusing SS#" << ReuseSlot; - DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" - << VirtReg + DOUT << " from physreg " << TRI->getName(PhysReg) + << " for vreg" << VirtReg << " instead of reloading into same physreg.\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); ReusedOperands.markClobbered(RReg); ++NumReused; continue; } - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); - MF.setPhysRegUsed(DesignatedReg); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + RegInfo->setPhysRegUsed(DesignatedReg); ReusedOperands.markClobbered(DesignatedReg); - MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); + TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); MachineInstr *CopyMI = prior(MII); - UpdateKills(*CopyMI, RegKills, KillOps); + UpdateKills(*CopyMI, RegKills, KillOps, TRI); // This invalidates DesignatedReg. Spills.ClobberPhysReg(DesignatedReg); - Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); + Spills.addAvailable(ReuseSlot, DesignatedReg); unsigned RReg = - SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; + SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; MI.getOperand(i).setReg(RReg); DOUT << '\t' << *prior(MII); ++NumReused; @@ -1206,14 +1679,15 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, Spills, MaybeDeadStores, RegKills, KillOps, VRM); - MF.setPhysRegUsed(PhysReg); + RegInfo->setPhysRegUsed(PhysReg); ReusedOperands.markClobbered(PhysReg); if (DoReMat) { - MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); - ++NumReMats; + ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM); } else { - const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); - MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); + const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); + TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); + MachineInstr *LoadMI = prior(MII); + VRM.addSpillSlotUse(SSorRMId, LoadMI); ++NumLoads; } // This invalidates PhysReg. @@ -1222,17 +1696,34 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Any stores to this stack slot are not dead anymore. if (!DoReMat) MaybeDeadStores[SSorRMId] = NULL; - Spills.addAvailable(SSorRMId, &MI, PhysReg); + Spills.addAvailable(SSorRMId, PhysReg); // Assumes this is the last use. IsKill will be unset if reg is reused // unless it's a two-address operand. - if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) + if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) MI.getOperand(i).setIsKill(); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); - UpdateKills(*prior(MII), RegKills, KillOps); + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } + // Ok - now we can remove stores that have been confirmed dead. + for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) { + // This was the last use and the spilled value is still available + // for reuse. That means the spill was unnecessary! + int PDSSlot = PotentialDeadStoreSlots[j]; + MachineInstr* DeadStore = MaybeDeadStores[PDSSlot]; + if (DeadStore) { + DOUT << "Removed dead store:\t" << *DeadStore; + InvalidateKills(*DeadStore, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(DeadStore); + MBB.erase(DeadStore); + MaybeDeadStores[PDSSlot] = NULL; + ++NumDSE; + } + } + + DOUT << '\t' << MI; @@ -1240,11 +1731,14 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // physical registers that may contain the value of the spilled virtual // register SmallSet FoldedSS; - for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { + for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { unsigned VirtReg = I->second.first; VirtRegMap::ModRef MR = I->second.second; DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; + // MI2VirtMap be can updated which invalidate the iterator. + // Increment the iterator first. + ++I; int SS = VRM.getStackSlot(VirtReg); if (SS == VirtRegMap::NO_STACK_SLOT) continue; @@ -1262,17 +1756,33 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { DOUT << "Promoted Load To Copy: " << MI; if (DestReg != InReg) { - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); - MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); + TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); + MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg); + unsigned SubIdx = DefMO->getSubReg(); // Revisit the copy so we make sure to notice the effects of the // operation on the destreg (either needing to RA it if it's // virtual or needing to clobber any values if it's physical). NextMII = &MI; --NextMII; // backtrack to the copy. + // Propagate the sub-register index over. + if (SubIdx) { + DefMO = NextMII->findRegisterDefOperand(DestReg); + DefMO->setSubReg(SubIdx); + } + + // Mark is killed. + MachineOperand *KillOpnd = NextMII->findRegisterUseOperand(InReg); + KillOpnd->setIsKill(); + BackTracked = true; - } else + } else { DOUT << "Removing now-noop copy: " << MI; + // Unset last kill since it's being reused. + InvalidateKill(InReg, RegKills, KillOps); + } + InvalidateKills(MI, RegKills, KillOps); VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); Erased = true; @@ -1282,8 +1792,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); SmallVector NewMIs; if (PhysReg && - MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { + TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { MBB.insert(MII, NewMIs[0]); + InvalidateKills(MI, RegKills, KillOps); VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); Erased = true; @@ -1303,19 +1814,30 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (MR & VirtRegMap::isModRef) { unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); SmallVector NewMIs; + // We can reuse this physreg as long as we are allowed to clobber + // the value and there isn't an earlier def that has already clobbered + // the physreg. if (PhysReg && - DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 && - MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) { - MBB.insert(MII, NewMIs[0]); - NewStore = NewMIs[1]; - MBB.insert(MII, NewStore); - VRM.RemoveMachineInstrFromMaps(&MI); - MBB.erase(&MI); - Erased = true; - --NextMII; - --NextMII; // backtrack to the unfolded instruction. - BackTracked = true; - isDead = true; + !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable! + MachineOperand *KillOpnd = + DeadStore->findRegisterUseOperand(PhysReg, true); + // Note, if the store is storing a sub-register, it's possible the + // super-register is needed below. + if (KillOpnd && !KillOpnd->getSubReg() && + TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ + MBB.insert(MII, NewMIs[0]); + NewStore = NewMIs[1]; + MBB.insert(MII, NewStore); + VRM.addSpillSlotUse(SS, NewStore); + InvalidateKills(MI, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(&MI); + MBB.erase(&MI); + Erased = true; + --NextMII; + --NextMII; // backtrack to the unfolded instruction. + BackTracked = true; + isDead = true; + } } } @@ -1351,17 +1873,25 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { int StackSlot; if (!(MR & VirtRegMap::isRef)) { if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { - assert(MRegisterInfo::isPhysicalRegister(SrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Src hasn't been allocated yet?"); + + if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot, + RegKills, KillOps, TRI, VRM)) { + NextMII = next(MII); + BackTracked = true; + goto ProcessNextInst; + } + // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark // this as a potentially dead store in case there is a subsequent // store into the stack slot without a read from it. MaybeDeadStores[StackSlot] = &MI; // If the stack slot value was previously available in some other - // register, change it now. Otherwise, make the register available, - // in PhysReg. - Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); + // register, change it now. Otherwise, make the register + // available in PhysReg. + Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/); } } } @@ -1370,20 +1900,30 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Process all of the spilled defs. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!(MO.isRegister() && MO.getReg() && MO.isDef())) + if (!(MO.isReg() && MO.getReg() && MO.isDef())) continue; unsigned VirtReg = MO.getReg(); - if (!MRegisterInfo::isVirtualRegister(VirtReg)) { + if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. - unsigned Src, Dst; - if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { + unsigned Src, Dst, SrcSR, DstSR; + if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { ++NumDCE; DOUT << "Removing now-noop copy: " << MI; + SmallVector KillRegs; + InvalidateKills(MI, RegKills, KillOps, &KillRegs); + if (MO.isDead() && !KillRegs.empty()) { + // Source register or an implicit super/sub-register use is killed. + assert(KillRegs[0] == Dst || + TRI->isSubRegister(KillRegs[0], Dst) || + TRI->isSuperRegister(KillRegs[0], Dst)); + // Last def is now dead. + TransferDeadness(&MBB, Dist, Src, RegKills, KillOps); + } + VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); Erased = true; - VRM.RemoveMachineInstrFromMaps(&MI); Spills.disallowClobberPhysReg(VirtReg); goto ProcessNextInst; } @@ -1401,7 +1941,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // If it is a folded reference, then it's not safe to clobber. bool Folded = FoldedSS.count(FrameIdx); // Otherwise, if it wasn't available, remember that it is now! - Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); + Spills.addAvailable(FrameIdx, DestReg, !Folded); goto ProcessNextInst; } @@ -1415,17 +1955,17 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // The only vregs left are stack slot definitions. int StackSlot = VRM.getStackSlot(VirtReg); - const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); + const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); // If this def is part of a two-address operand, make sure to execute // the store from the correct physical register. unsigned PhysReg; - int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); + int TiedOp = MI.getDesc().findTiedToSrcOperand(i); if (TiedOp != -1) { PhysReg = MI.getOperand(TiedOp).getReg(); if (SubIdx) { - unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI); - assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg && + unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); + assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && "Can't find corresponding super-register!"); PhysReg = SuperReg; } @@ -1439,39 +1979,44 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { } } - MF.setPhysRegUsed(PhysReg); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + assert(PhysReg && "VR not assigned a physical register?"); + RegInfo->setPhysRegUsed(PhysReg); + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; ReusedOperands.markClobbered(RReg); MI.getOperand(i).setReg(RReg); if (!MO.isDead()) { MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; - SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, LastStore, - Spills, ReMatDefs, RegKills, KillOps, VRM); + SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, + LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); NextMII = next(MII); // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. { - unsigned Src, Dst; - if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { + unsigned Src, Dst, SrcSR, DstSR; + if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { ++NumDCE; DOUT << "Removing now-noop copy: " << MI; + InvalidateKills(MI, RegKills, KillOps); + VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); Erased = true; - VRM.RemoveMachineInstrFromMaps(&MI); - UpdateKills(*LastStore, RegKills, KillOps); + UpdateKills(*LastStore, RegKills, KillOps, TRI); goto ProcessNextInst; } } } } ProcessNextInst: - if (!Erased && !BackTracked) - for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) - UpdateKills(*II, RegKills, KillOps); + DistanceMap.insert(std::make_pair(&MI, Dist++)); + if (!Erased && !BackTracked) { + for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II) + UpdateKills(*II, RegKills, KillOps, TRI); + } MII = NextMII; } + } llvm::Spiller* llvm::createSpiller() {