X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAArch64%2FAArch64InstrInfo.cpp;h=afb20341f781153f94e725db8a5170dd33383e1b;hb=0c0cd3a4ee0a9bf48b396b2c94bbd0504f2e0e57;hp=34312e2284440a856bc05a87020cb85bb3f0b244;hpb=84887ceca34fea5457923c1968c15fbf0e41c6eb;p=oota-llvm.git

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index 34312e22844..afb20341f78 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -132,12 +132,22 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
         .addImm(16);
       return;
     }
+  } else if (AArch64::FPR8RegClass.contains(DestReg, SrcReg)) {
+    // The copy of two FPR8 registers is implemented by the copy of two FPR32
+    const TargetRegisterInfo *TRI = &getRegisterInfo();
+    unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_8,
+                                            &AArch64::FPR32RegClass);
+    unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_8,
+                                            &AArch64::FPR32RegClass);
+    BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
+      .addReg(Src);
+    return;
   } else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
     // The copy of two FPR16 registers is implemented by the copy of two FPR32
     const TargetRegisterInfo *TRI = &getRegisterInfo();
-    unsigned Dst = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
+    unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
                                             &AArch64::FPR32RegClass);
-    unsigned Src = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
+    unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
                                             &AArch64::FPR32RegClass);
     BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
       .addReg(Src);
@@ -477,6 +487,10 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP8_STR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP16_STR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
@@ -543,6 +557,10 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP8_LDR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP16_LDR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
@@ -611,7 +629,8 @@ void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
                                              int &AccessScale, int &MinOffset,
                                              int &MaxOffset) const {
   switch (MI.getOpcode()) {
-  default: llvm_unreachable("Unkown load/store kind");
+  default:
+    llvm_unreachable("Unknown load/store kind");
   case TargetOpcode::DBG_VALUE:
     AccessScale = 1;
     MinOffset = INT_MIN;
@@ -711,18 +730,15 @@ unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   if (MI.getOpcode() == AArch64::INLINEASM)
     return getInlineAsmLength(MI.getOperand(0).getSymbolName(), MAI);
 
-  if (MI.isLabel())
-    return 0;
-
   switch (MI.getOpcode()) {
   case TargetOpcode::BUNDLE:
     return getInstBundleLength(MI);
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
-  case TargetOpcode::PROLOG_LABEL:
+  case TargetOpcode::CFI_INSTRUCTION:
   case TargetOpcode::EH_LABEL:
+  case TargetOpcode::GC_LABEL:
   case TargetOpcode::DBG_VALUE:
-    return 0;
   case AArch64::TLSDESCCALL:
     return 0;
   default: