X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMAsmPrinter.cpp;h=2544a01fa7f8e214dfb108bd4f61eb971e2d7d25;hb=52f83a9ab3a02b523035044f04702a430570771a;hp=9ad808c00e799694b5bfc414ef65aa65aabab6bc;hpb=642c8bef1931cfc05f6d23a9b25d7d182cc48c01;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 9ad808c00e7..2544a01fa7f 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -16,6 +16,7 @@ #include "ARM.h" #include "ARMConstantPoolValue.h" #include "ARMFPUName.h" +#include "ARMArchExtName.h" #include "ARMMachineFunctionInfo.h" #include "ARMTargetMachine.h" #include "ARMTargetObjectFile.h" @@ -57,6 +58,11 @@ using namespace llvm; #define DEBUG_TYPE "asm-printer" +ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM, + std::unique_ptr Streamer) + : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr), + InConstantPool(false) {} + void ARMAsmPrinter::EmitFunctionBodyEnd() { // Make sure to terminate any constant pools that were at the end // of the function. @@ -98,6 +104,7 @@ void ARMAsmPrinter::EmitXXStructor(const Constant *CV) { bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { AFI = MF.getInfo(); MCP = MF.getConstantPool(); + Subtarget = &MF.getSubtarget(); SetupMachineFunction(MF); @@ -119,6 +126,23 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Emit the rest of the function body. EmitFunctionBody(); + // If we need V4T thumb mode Register Indirect Jump pads, emit them. + // These are created per function, rather than per TU, since it's + // relatively easy to exceed the thumb branch range within a TU. + if (! ThumbIndirectPads.empty()) { + OutStreamer.EmitAssemblerFlag(MCAF_Code16); + EmitAlignment(1); + for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) { + OutStreamer.EmitLabel(ThumbIndirectPads[i].second); + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX) + .addReg(ThumbIndirectPads[i].first) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0)); + } + ThumbIndirectPads.clear(); + } + // We didn't modify anything. return false; } @@ -136,7 +160,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, assert(!MO.getSubReg() && "Subregs should be eliminated!"); if(ARM::GPRPairRegClass.contains(Reg)) { const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); Reg = TRI->getSubReg(Reg, ARM::gsub_0); } O << ARMInstPrinter::getRegisterName(Reg); @@ -229,7 +253,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'y': // Print a VFP single precision register as indexed double. if (MI->getOperand(OpNum).isReg()) { unsigned Reg = MI->getOperand(OpNum).getReg(); - const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); // Find the 'd' register that has this 's' register as a sub-register, // and determine the lane number. for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { @@ -261,7 +285,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, // inline asm statement. O << "{"; if (ARM::GPRPairRegClass.contains(RegBegin)) { - const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); O << ARMInstPrinter::getRegisterName(Reg0) << ", "; RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); @@ -317,7 +341,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const MachineOperand &MO = MI->getOperand(OpNum); if (!MO.isReg()) return true; - const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? ARM::gsub_0 : ARM::gsub_1); O << ARMInstPrinter::getRegisterName(Reg); @@ -343,7 +367,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned Reg = MI->getOperand(OpNum).getReg(); if (!ARM::QPRRegClass.contains(Reg)) return true; - const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); O << ARMInstPrinter::getRegisterName(SubReg); @@ -358,7 +382,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, if (!MO.isReg()) return true; const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); unsigned Reg = MO.getReg(); if(!ARM::GPRPairRegClass.contains(Reg)) return false; @@ -413,7 +437,8 @@ void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, } void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { - if (Subtarget->isTargetMachO()) { + Triple TT(TM.getTargetTriple()); + if (TT.isOSBinFormatMachO()) { Reloc::Model RelocM = TM.getRelocationModel(); if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) { // Declare all the text sections up front (before the DWARF sections @@ -476,10 +501,17 @@ void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified); // Emit ARM Build Attributes - if (Subtarget->isTargetELF()) + if (TT.isOSBinFormatELF()) emitAttributes(); - if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb()) + // Use the triple's architecture and subarchitecture to determine + // if we're thumb for the purposes of the top level code16 assembler + // flag. + bool isThumb = TT.getArch() == Triple::thumb || + TT.getArch() == Triple::thumbeb || + TT.getSubArch() == Triple::ARMSubArch_v7m || + TT.getSubArch() == Triple::ARMSubArch_v6m; + if (!M.getModuleInlineAsm().empty() && isThumb) OutStreamer.EmitAssemblerFlag(MCAF_Code16); } @@ -508,7 +540,8 @@ emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { - if (Subtarget->isTargetMachO()) { + Triple TT(TM.getTargetTriple()); + if (TT.isOSBinFormatMachO()) { // All darwin targets use mach-o. const TargetLoweringObjectFileMachO &TLOFMacho = static_cast(getObjFileLowering()); @@ -551,7 +584,7 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { } // Emit a .data.rel section containing any stubs that were created. - if (Subtarget->isTargetELF()) { + if (TT.isOSBinFormatELF()) { const TargetLoweringObjectFileELF &TLOFELF = static_cast(getObjFileLowering()); @@ -611,67 +644,96 @@ void ARMAsmPrinter::emitAttributes() { MCTargetStreamer &TS = *OutStreamer.getTargetStreamer(); ARMTargetStreamer &ATS = static_cast(TS); - ATS.switchVendor("aeabi"); + ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09"); - std::string CPUString = Subtarget->getCPUString(); + ATS.switchVendor("aeabi"); - // FIXME: remove krait check when GNU tools support krait cpu - if (CPUString != "generic" && CPUString != "krait") - ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString); + // Compute ARM ELF Attributes based on the default subtarget that + // we'd have constructed. The existing ARM behavior isn't LTO clean + // anyhow. + // FIXME: For ifunc related functions we could iterate over and look + // for a feature string that doesn't match the default one. + StringRef TT = TM.getTargetTriple(); + StringRef CPU = TM.getTargetCPU(); + StringRef FS = TM.getTargetFeatureString(); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS.str(); + else + ArchFS = FS; + } + const ARMBaseTargetMachine &ATM = + static_cast(TM); + const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian()); + + std::string CPUString = STI.getCPUString(); + + if (CPUString != "generic") { + // FIXME: remove krait check when GNU tools support krait cpu + if (STI.isKrait()) { + ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9"); + // We consider krait as a "cortex-a9" + hwdiv CPU + // Enable hwdiv through ".arch_extension idiv" + if (STI.hasDivide() || STI.hasDivideInARMMode()) + ATS.emitArchExtension(ARM::HWDIV); + } else + ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString); + } - ATS.emitAttribute(ARMBuildAttrs::CPU_arch, - getArchForCPU(CPUString, Subtarget)); + ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI)); // Tag_CPU_arch_profile must have the default value of 0 when "Architecture // profile is not applicable (e.g. pre v7, or cross-profile code)". - if (Subtarget->hasV7Ops()) { - if (Subtarget->isAClass()) { + if (STI.hasV7Ops()) { + if (STI.isAClass()) { ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ARMBuildAttrs::ApplicationProfile); - } else if (Subtarget->isRClass()) { + } else if (STI.isRClass()) { ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ARMBuildAttrs::RealTimeProfile); - } else if (Subtarget->isMClass()) { + } else if (STI.isMClass()) { ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile, ARMBuildAttrs::MicroControllerProfile); } } - ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ? - ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed); - if (Subtarget->isThumb1Only()) { - ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::Allowed); - } else if (Subtarget->hasThumb2()) { + ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, + STI.hasARMOps() ? ARMBuildAttrs::Allowed + : ARMBuildAttrs::Not_Allowed); + if (STI.isThumb1Only()) { + ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed); + } else if (STI.hasThumb2()) { ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::AllowThumb32); } - if (Subtarget->hasNEON()) { + if (STI.hasNEON()) { /* NEON is not exactly a VFP architecture, but GAS emit one of * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */ - if (Subtarget->hasFPARMv8()) { - if (Subtarget->hasCrypto()) + if (STI.hasFPARMv8()) { + if (STI.hasCrypto()) ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8); else ATS.emitFPU(ARM::NEON_FP_ARMV8); - } - else if (Subtarget->hasVFP4()) + } else if (STI.hasVFP4()) ATS.emitFPU(ARM::NEON_VFPV4); else ATS.emitFPU(ARM::NEON); // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture - if (Subtarget->hasV8Ops()) + if (STI.hasV8Ops()) ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch, ARMBuildAttrs::AllowNeonARMv8); } else { - if (Subtarget->hasFPARMv8()) - ATS.emitFPU(ARM::FP_ARMV8); - else if (Subtarget->hasVFP4()) - ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4); - else if (Subtarget->hasVFP3()) - ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3); - else if (Subtarget->hasVFP2()) + if (STI.hasFPARMv8()) + // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one + // FPU, but there are two different names for it depending on the CPU. + ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8); + else if (STI.hasVFP4()) + ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4); + else if (STI.hasVFP3()) + ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3); + else if (STI.hasVFP2()) ATS.emitFPU(ARM::VFPV2); } @@ -691,11 +753,42 @@ void ARMAsmPrinter::emitAttributes() { // Signal various FP modes. if (!TM.Options.UnsafeFPMath) { - ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed); - ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, - ARMBuildAttrs::Allowed); + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, + ARMBuildAttrs::IEEEDenormals); + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed); + + // If the user has permitted this code to choose the IEEE 754 + // rounding at run-time, emit the rounding attribute. + if (TM.Options.HonorSignDependentRoundingFPMathOption) + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed); + } else { + if (!STI.hasVFP2()) { + // When the target doesn't have an FPU (by design or + // intention), the assumptions made on the software support + // mirror that of the equivalent hardware support *if it + // existed*. For v7 and better we indicate that denormals are + // flushed preserving sign, and for V6 we indicate that + // denormals are flushed to positive zero. + if (STI.hasV7Ops()) + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, + ARMBuildAttrs::PreserveFPSign); + } else if (STI.hasVFP3()) { + // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is, + // the sign bit of the zero matches the sign bit of the input or + // result that is being flushed to zero. + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, + ARMBuildAttrs::PreserveFPSign); + } + // For VFPv2 implementations it is implementation defined as + // to whether denormals are flushed to positive zero or to + // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically + // LLVM has chosen to flush this to positive zero (most likely for + // GCC compatibility), so that's the chosen value here (the + // absence of its emission implies zero). } + // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the + // equivalent of GCC's -ffinite-math-only flag. if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath) ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model, ARMBuildAttrs::Allowed); @@ -703,27 +796,41 @@ void ARMAsmPrinter::emitAttributes() { ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model, ARMBuildAttrs::AllowIEE754); + if (STI.allowsUnalignedMem()) + ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access, + ARMBuildAttrs::Allowed); + else + ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access, + ARMBuildAttrs::Not_Allowed); + // FIXME: add more flags to ARMBuildAttributes.h // 8-bytes alignment stuff. ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1); ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1); // ABI_HardFP_use attribute to indicate single precision FP. - if (Subtarget->isFPOnlySP()) + if (STI.isFPOnlySP()) ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use, ARMBuildAttrs::HardFPSinglePrecision); // Hard float. Use both S and D registers and conform to AAPCS-VFP. - if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) + if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS); // FIXME: Should we signal R9 usage? - if (Subtarget->hasFP16()) - ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP); + if (STI.hasFP16()) + ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP); + + // FIXME: To support emitting this build attribute as GCC does, the + // -mfp16-format option and associated plumbing must be + // supported. For now the __fp16 type is exposed by default, so this + // attribute should be emitted with value 1. + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format, + ARMBuildAttrs::FP16FormatIEEE); - if (Subtarget->hasMPExtension()) - ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP); + if (STI.hasMPExtension()) + ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP); // Hardware divide in ARM mode is part of base arch, starting from ARMv8. // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M). @@ -731,14 +838,14 @@ void ARMAsmPrinter::emitAttributes() { // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits. // AllowDIVExt is only emitted if hwdiv isn't available in the base arch; // otherwise, the default value (AllowDIVIfExists) applies. - if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops()) - ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt); + if (STI.hasDivideInARMMode() && !STI.hasV8Ops()) + ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt); if (MMI) { if (const Module *SourceModule = MMI->getModule()) { // ABI_PCS_wchar_t to indicate wchar_t width // FIXME: There is no way to emit value 0 (wchar_t prohibited). - if (auto WCharWidthValue = cast_or_null( + if (auto WCharWidthValue = mdconst::extract_or_null( SourceModule->getModuleFlag("wchar_size"))) { int WCharWidth = WCharWidthValue->getZExtValue(); assert((WCharWidth == 2 || WCharWidth == 4) && @@ -749,7 +856,7 @@ void ARMAsmPrinter::emitAttributes() { // ABI_enum_size to indicate enum width // FIXME: There is no way to emit value 0 (enums prohibited) or value 3 // (all enums contain a value needing 32 bits to encode). - if (auto EnumWidthValue = cast_or_null( + if (auto EnumWidthValue = mdconst::extract_or_null( SourceModule->getModuleFlag("min_enum_size"))) { int EnumWidth = EnumWidthValue->getZExtValue(); assert((EnumWidth == 1 || EnumWidth == 4) && @@ -760,15 +867,24 @@ void ARMAsmPrinter::emitAttributes() { } } - if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization()) - ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, - ARMBuildAttrs::AllowTZVirtualization); - else if (Subtarget->hasTrustZone()) - ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, - ARMBuildAttrs::AllowTZ); - else if (Subtarget->hasVirtualization()) - ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, - ARMBuildAttrs::AllowVirtualization); + // TODO: We currently only support either reserving the register, or treating + // it as another callee-saved register, but not as SB or a TLS pointer; It + // would instead be nicer to push this from the frontend as metadata, as we do + // for the wchar and enum size tags + if (STI.isR9Reserved()) + ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved); + else + ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR); + + if (STI.hasTrustZone() && STI.hasVirtualization()) + ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, + ARMBuildAttrs::AllowTZVirtualization); + else if (STI.hasTrustZone()) + ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, + ARMBuildAttrs::AllowTZ); + else if (STI.hasVirtualization()) + ATS.emitAttribute(ARMBuildAttrs::Virtualization_use, + ARMBuildAttrs::AllowVirtualization); ATS.finishAttributeSection(); } @@ -1016,7 +1132,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { MCTargetStreamer &TS = *OutStreamer.getTargetStreamer(); ARMTargetStreamer &ATS = static_cast(TS); const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); const ARMFunctionInfo &AFI = *MF.getInfo(); unsigned FramePtr = RegInfo->getFrameRegister(MF); @@ -1229,18 +1345,34 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case ARM::tBX_CALL: { - EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr) - .addReg(ARM::LR) - .addReg(ARM::PC) - // Add predicate operands. - .addImm(ARMCC::AL) - .addReg(0)); + if (Subtarget->hasV5TOps()) + llvm_unreachable("Expected BLX to be selected for v5t+"); + + // On ARM v4t, when doing a call from thumb mode, we need to ensure + // that the saved lr has its LSB set correctly (the arch doesn't + // have blx). + // So here we generate a bl to a small jump pad that does bx rN. + // The jump pads are emitted after the function body. + + unsigned TReg = MI->getOperand(0).getReg(); + MCSymbol *TRegSym = nullptr; + for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) { + if (ThumbIndirectPads[i].first == TReg) { + TRegSym = ThumbIndirectPads[i].second; + break; + } + } - EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX) - .addReg(MI->getOperand(0).getReg()) - // Add predicate operands. - .addImm(ARMCC::AL) - .addReg(0)); + if (!TRegSym) { + TRegSym = OutContext.CreateTempSymbol(); + ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); + } + + // Create a link-saving branch to the Reg Indirect Jump Pad. + EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL) + // Predicate comes first here. + .addImm(ARMCC::AL).addReg(0) + .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext))); return; } case ARM::BMOVPCRX_CALL: { @@ -1570,6 +1702,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { EmitJumpTable(MI); return; } + case ARM::SPACE: + OutStreamer.EmitZeros(MI->getOperand(1).getImm()); + return; case ARM::TRAP: { // Non-Darwin binutils don't yet support the "trap" mnemonic. // FIXME: Remove this special case when they do.