X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMFastISel.cpp;h=9c8d228c1ee714b3df9fbb071db61cf52cc0fc31;hb=1106660066504d163543607b38371c97aef7708e;hp=5d33303ffa1731132fc4bfa5d2a37c1b673a3998;hpb=c76c3fe5cf36176e776eed9a6d6801cfd613918d;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 5d33303ffa1..9c8d228c1ee 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -93,11 +93,11 @@ class ARMFastISel final : public FastISel { explicit ARMFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) : FastISel(funcInfo, libInfo), + Subtarget( + &static_cast(funcInfo.MF->getSubtarget())), M(const_cast(*funcInfo.Fn->getParent())), - TM(funcInfo.MF->getTarget()), - TII(*TM.getSubtargetImpl()->getInstrInfo()), - TLI(*TM.getSubtargetImpl()->getTargetLowering()) { - Subtarget = &TM.getSubtarget(); + TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), + TLI(*Subtarget->getTargetLowering()) { AFI = funcInfo.MF->getInfo(); isThumb2 = AFI->isThumbFunction(); Context = &funcInfo.Fn->getContext(); @@ -105,39 +105,39 @@ class ARMFastISel final : public FastISel { // Code from FastISel.cpp. private: - unsigned FastEmitInst_r(unsigned MachineInstOpcode, + unsigned fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill); - unsigned FastEmitInst_rr(unsigned MachineInstOpcode, + unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill); - unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, + unsigned fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill); - unsigned FastEmitInst_ri(unsigned MachineInstOpcode, + unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm); - unsigned FastEmitInst_rri(unsigned MachineInstOpcode, + unsigned fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm); - unsigned FastEmitInst_i(unsigned MachineInstOpcode, + unsigned fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm); // Backend specific FastISel code. private: - bool TargetSelectInstruction(const Instruction *I) override; - unsigned TargetMaterializeConstant(const Constant *C) override; - unsigned TargetMaterializeAlloca(const AllocaInst *AI) override; + bool fastSelectInstruction(const Instruction *I) override; + unsigned fastMaterializeConstant(const Constant *C) override; + unsigned fastMaterializeAlloca(const AllocaInst *AI) override; bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, const LoadInst *LI) override; - bool FastLowerArguments() override; + bool fastLowerArguments() override; private: #include "ARMGenFastISel.inc" @@ -189,9 +189,7 @@ class ARMFastISel final : public FastISel { unsigned ARMSelectCallOp(bool UseReg); unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT); - const TargetLowering *getTargetLowering() { - return TM.getSubtargetImpl()->getTargetLowering(); - } + const TargetLowering *getTargetLowering() { return &TLI; } // Call handling routines. private: @@ -285,7 +283,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { return MIB; } -unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) { unsigned ResultReg = createResultReg(RC); @@ -307,7 +305,7 @@ unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { @@ -335,7 +333,7 @@ unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, @@ -367,7 +365,7 @@ unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) { @@ -393,7 +391,7 @@ unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, @@ -423,7 +421,7 @@ unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, return ResultReg; } -unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode, +unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); @@ -513,7 +511,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) - return false; + return 0; // If we can do this in a single instruction without a constant pool entry // do so now. @@ -546,11 +544,16 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { } } + unsigned ResultReg = 0; + if (Subtarget->useMovt(*FuncInfo.MF)) + ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); + + if (ResultReg) + return ResultReg; + // Load from constant pool. For now 32-bit only. if (VT != MVT::i32) - return false; - - unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + return 0; // MachineConstantPool wants an explicit alignment. unsigned Align = DL.getPrefTypeAlignment(C->getType()); @@ -559,21 +562,20 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { Align = DL.getTypeAllocSize(C->getType()); } unsigned Idx = MCP.getConstantPoolIndex(C, Align); - + ResultReg = createResultReg(TLI.getRegClassFor(VT)); if (isThumb2) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(ARM::t2LDRpci), DestReg) - .addConstantPoolIndex(Idx)); + TII.get(ARM::t2LDRpci), ResultReg) + .addConstantPoolIndex(Idx)); else { // The extra immediate is for addrmode2. - DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); + ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(ARM::LDRcp), DestReg) - .addConstantPoolIndex(Idx) - .addImm(0)); + TII.get(ARM::LDRcp), ResultReg) + .addConstantPoolIndex(Idx) + .addImm(0)); } - - return DestReg; + return ResultReg; } unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { @@ -582,9 +584,8 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { Reloc::Model RelocM = TM.getRelocationModel(); bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); - const TargetRegisterClass *RC = isThumb2 ? - (const TargetRegisterClass*)&ARM::rGPRRegClass : - (const TargetRegisterClass*)&ARM::GPRRegClass; + const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass + : &ARM::GPRRegClass; unsigned DestReg = createResultReg(RC); // FastISel TLS support on non-MachO is broken, punt to SelectionDAG. @@ -683,7 +684,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { return DestReg; } -unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { +unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) { EVT CEVT = TLI.getValueType(C->getType(), true); // Only handle simple types. @@ -702,7 +703,7 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF); -unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { +unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) { // Don't handle dynamic allocas. if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; @@ -889,9 +890,8 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { // put the alloca address into a register, set the base type back to // register and continue. This should almost never happen. if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { - const TargetRegisterClass *RC = isThumb2 ? - (const TargetRegisterClass*)&ARM::tGPRRegClass : - (const TargetRegisterClass*)&ARM::GPRRegClass; + const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass + : &ARM::GPRRegClass; unsigned ResultReg = createResultReg(RC); unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, @@ -905,7 +905,7 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { // Since the offset is too large for the load/store instruction // get the reg+offset into a register. if (needsLowering) { - Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, + Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, /*Op0IsKill*/false, Addr.Offset, MVT::i32); Addr.Offset = 0; } @@ -1078,7 +1078,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) { unsigned ResultReg; if (!ARMEmitLoad(VT, ResultReg, Addr, cast(I)->getAlignment())) return false; - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -1090,9 +1090,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, // This is mostly going to be Neon/vector support. default: return false; case MVT::i1: { - unsigned Res = createResultReg(isThumb2 ? - (const TargetRegisterClass*)&ARM::tGPRRegClass : - (const TargetRegisterClass*)&ARM::GPRRegClass); + unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass + : &ARM::GPRRegClass); unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, @@ -1280,7 +1279,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); - FastEmitBranch(FBB, DbgLoc); + fastEmitBranch(FBB, DbgLoc); FuncInfo.MBB->addSuccessor(TBB); return true; } @@ -1305,7 +1304,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); - FastEmitBranch(FBB, DbgLoc); + fastEmitBranch(FBB, DbgLoc); FuncInfo.MBB->addSuccessor(TBB); return true; } @@ -1313,7 +1312,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { dyn_cast(BI->getCondition())) { uint64_t Imm = CI->getZExtValue(); MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; - FastEmitBranch(Target, DbgLoc); + fastEmitBranch(Target, DbgLoc); return true; } @@ -1343,7 +1342,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); - FastEmitBranch(FBB, DbgLoc); + fastEmitBranch(FBB, DbgLoc); FuncInfo.MBB->addSuccessor(TBB); return true; } @@ -1496,18 +1495,17 @@ bool ARMFastISel::SelectCmp(const Instruction *I) { // Now set a register based on the comparison. Explicitly set the predicates // here. unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; - const TargetRegisterClass *RC = isThumb2 ? - (const TargetRegisterClass*)&ARM::rGPRRegClass : - (const TargetRegisterClass*)&ARM::GPRRegClass; + const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass + : &ARM::GPRRegClass; unsigned DestReg = createResultReg(RC); Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); - unsigned ZeroReg = TargetMaterializeConstant(Zero); + unsigned ZeroReg = fastMaterializeConstant(Zero); // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg) .addReg(ZeroReg).addImm(1) .addImm(ARMPred).addReg(ARM::CPSR); - UpdateValueMap(I, DestReg); + updateValueMap(I, DestReg); return true; } @@ -1526,7 +1524,7 @@ bool ARMFastISel::SelectFPExt(const Instruction *I) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM::VCVTDS), Result) .addReg(Op)); - UpdateValueMap(I, Result); + updateValueMap(I, Result); return true; } @@ -1545,7 +1543,7 @@ bool ARMFastISel::SelectFPTrunc(const Instruction *I) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM::VCVTSD), Result) .addReg(Op)); - UpdateValueMap(I, Result); + updateValueMap(I, Result); return true; } @@ -1589,7 +1587,7 @@ bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) { unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg).addReg(FP)); - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -1621,7 +1619,7 @@ bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) { unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); if (IntReg == 0) return false; - UpdateValueMap(I, IntReg); + updateValueMap(I, IntReg); return true; } @@ -1697,7 +1695,7 @@ bool ARMFastISel::SelectSelect(const Instruction *I) { .addImm(ARMCC::EQ) .addReg(ARM::CPSR); } - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -1787,7 +1785,7 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addReg(SrcReg1).addReg(SrcReg2)); - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -1829,7 +1827,7 @@ bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addReg(Op1).addReg(Op2)); - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -1972,7 +1970,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl &Args, break; } case CCValAssign::BCvt: { - unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, + unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, /*TODO: Kill=*/false); assert(BC != 0 && "Failed to emit a bitcast!"); Arg = BC; @@ -2055,7 +2053,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl &UsedRegs, UsedRegs.push_back(RVLocs[1].getLocReg()); // Finally update the result. - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); } else { assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); MVT CopyVT = RVLocs[0].getValVT(); @@ -2073,7 +2071,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl &UsedRegs, UsedRegs.push_back(RVLocs[0].getLocReg()); // Finally update the result. - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); } } @@ -2267,7 +2265,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { // Add a register mask with the call-preserved registers. // Proper defs for return values will be added by setPhysRegsDeadExcept(). - MIB.addRegMask(TRI.getCallPreservedMask(CC)); + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); // Finish off the call including any return values. SmallVector UsedRegs; @@ -2418,7 +2416,7 @@ bool ARMFastISel::SelectCall(const Instruction *I, // Add a register mask with the call-preserved registers. // Proper defs for return values will be added by setPhysRegsDeadExcept(). - MIB.addRegMask(TRI.getCallPreservedMask(CC)); + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); // Finish off the call including any return values. SmallVector UsedRegs; @@ -2486,19 +2484,12 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) { MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo(); MFI->setFrameAddressIsTaken(true); - unsigned LdrOpc; - const TargetRegisterClass *RC; - if (isThumb2) { - LdrOpc = ARM::t2LDRi12; - RC = (const TargetRegisterClass*)&ARM::tGPRRegClass; - } else { - LdrOpc = ARM::LDRi12; - RC = (const TargetRegisterClass*)&ARM::GPRRegClass; - } + unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; + const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass + : &ARM::GPRRegClass; const ARMBaseRegisterInfo *RegInfo = - static_cast( - TM.getSubtargetImpl()->getRegisterInfo()); + static_cast(Subtarget->getRegisterInfo()); unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF)); unsigned SrcReg = FramePtr; @@ -2516,7 +2507,7 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) { .addReg(SrcReg).addImm(0)); SrcReg = DestReg; } - UpdateValueMap(&I, SrcReg); + updateValueMap(&I, SrcReg); return true; } case Intrinsic::memcpy: @@ -2594,7 +2585,7 @@ bool ARMFastISel::SelectTrunc(const Instruction *I) { // Because the high bits are undefined, a truncate doesn't generate // any code. - UpdateValueMap(I, SrcReg); + updateValueMap(I, SrcReg); return true; } @@ -2756,7 +2747,7 @@ bool ARMFastISel::SelectIntExt(const Instruction *I) { MVT DestVT = DestEVT.getSimpleVT(); unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); if (ResultReg == 0) return false; - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } @@ -2811,12 +2802,12 @@ bool ARMFastISel::SelectShift(const Instruction *I, } AddOptionalDefs(MIB); - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } // TODO: SoftFP support. -bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { +bool ARMFastISel::fastSelectInstruction(const Instruction *I) { switch (I->getOpcode()) { case Instruction::Load: @@ -2994,7 +2985,7 @@ unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, return DestReg2; } -bool ARMFastISel::FastLowerArguments() { +bool ARMFastISel::fastLowerArguments() { if (!FuncInfo.CanLowerReturn) return false; @@ -3061,7 +3052,7 @@ bool ARMFastISel::FastLowerArguments() { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), ResultReg).addReg(DstReg, getKillRegState(true)); - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); } return true; @@ -3071,13 +3062,13 @@ namespace llvm { FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) { const TargetMachine &TM = funcInfo.MF->getTarget(); - - const ARMSubtarget *Subtarget = &TM.getSubtarget(); + const ARMSubtarget &STI = + static_cast(funcInfo.MF->getSubtarget()); // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl. bool UseFastISel = false; - UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only(); - UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb(); - UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb(); + UseFastISel |= STI.isTargetMachO() && !STI.isThumb1Only(); + UseFastISel |= STI.isTargetLinux() && !STI.isThumb(); + UseFastISel |= STI.isTargetNaCl() && !STI.isThumb(); if (UseFastISel) { // iOS always has a FP for backtracking, force other targets