X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMISelLowering.cpp;h=b82a2209e550bc7f7d15e32ed50efa4d53a44176;hb=235e2f6a68b5f37d6c1b554330eebc8d32f1aca9;hp=d5689de4b764e9c99fecab53c07439778c104a07;hpb=0696fdf3220c4cdd7fc518274048a35091cc17b1;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index d5689de4b76..b82a2209e55 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -392,8 +392,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); - setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); setOperationAction(ISD::SETCC, MVT::i32, Expand); setOperationAction(ISD::SETCC, MVT::f32, Expand); @@ -542,7 +540,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { /// getFunctionAlignment - Return the Log2 alignment of this function. unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { - return getTargetMachine().getSubtarget().isThumb() ? 1 : 2; + return getTargetMachine().getSubtarget().isThumb() ? 0 : 1; } //===----------------------------------------------------------------------===// @@ -1303,17 +1301,20 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), - CPAddr, NULL, 0); + CPAddr, + PseudoSourceValue::getConstantPool(), 0); SDValue Chain = Result.getValue(1); SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); if (!UseGOTOFF) - Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, + PseudoSourceValue::getGOT(), 0); return Result; } else { SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); - return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, + PseudoSourceValue::getConstantPool(), 0); } } @@ -1360,107 +1361,12 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, ARMPCLabelIndex, PCAdj); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, + PseudoSourceValue::getConstantPool(), 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } -static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG, - unsigned NumVecs) { - SDNode *Node = Op.getNode(); - EVT VT = Node->getValueType(0); - - // No expansion needed for 64-bit vectors. - if (VT.is64BitVector()) - return SDValue(); - - // FIXME: We need to expand VLD3 and VLD4 of 128-bit vectors into separate - // operations to load the even and odd registers. - return SDValue(); -} - -static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG, - unsigned NumVecs) { - SDNode *Node = Op.getNode(); - EVT VT = Node->getOperand(3).getValueType(); - - // No expansion needed for 64-bit vectors. - if (VT.is64BitVector()) - return SDValue(); - - // FIXME: We need to expand VST3 and VST4 of 128-bit vectors into separate - // operations to store the even and odd registers. - return SDValue(); -} - -static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG, - unsigned NumVecs) { - SDNode *Node = Op.getNode(); - EVT VT = Node->getValueType(0); - - if (!VT.is64BitVector()) - return SDValue(); // unimplemented - - // Change the lane number operand to be a TargetConstant; otherwise it - // will be legalized into a register. - ConstantSDNode *Lane = dyn_cast(Node->getOperand(NumVecs+3)); - if (!Lane) { - assert(false && "vld lane number must be a constant"); - return SDValue(); - } - SmallVector Ops(Node->op_begin(), Node->op_end()); - Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32); - return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size()); -} - -static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG, - unsigned NumVecs) { - SDNode *Node = Op.getNode(); - EVT VT = Node->getOperand(3).getValueType(); - - if (!VT.is64BitVector()) - return SDValue(); // unimplemented - - // Change the lane number operand to be a TargetConstant; otherwise it - // will be legalized into a register. - ConstantSDNode *Lane = dyn_cast(Node->getOperand(NumVecs+3)); - if (!Lane) { - assert(false && "vst lane number must be a constant"); - return SDValue(); - } - SmallVector Ops(Node->op_begin(), Node->op_end()); - Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32); - return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size()); -} - -SDValue -ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) { - unsigned IntNo = cast(Op.getOperand(1))->getZExtValue(); - switch (IntNo) { - case Intrinsic::arm_neon_vld3: - return LowerNeonVLDIntrinsic(Op, DAG, 3); - case Intrinsic::arm_neon_vld4: - return LowerNeonVLDIntrinsic(Op, DAG, 4); - case Intrinsic::arm_neon_vld2lane: - return LowerNeonVLDLaneIntrinsic(Op, DAG, 2); - case Intrinsic::arm_neon_vld3lane: - return LowerNeonVLDLaneIntrinsic(Op, DAG, 3); - case Intrinsic::arm_neon_vld4lane: - return LowerNeonVLDLaneIntrinsic(Op, DAG, 4); - case Intrinsic::arm_neon_vst3: - return LowerNeonVSTIntrinsic(Op, DAG, 3); - case Intrinsic::arm_neon_vst4: - return LowerNeonVSTIntrinsic(Op, DAG, 4); - case Intrinsic::arm_neon_vst2lane: - return LowerNeonVSTLaneIntrinsic(Op, DAG, 2); - case Intrinsic::arm_neon_vst3lane: - return LowerNeonVSTLaneIntrinsic(Op, DAG, 3); - case Intrinsic::arm_neon_vst4lane: - return LowerNeonVSTLaneIntrinsic(Op, DAG, 4); - default: return SDValue(); // Don't custom lower most intrinsics. - } -} - SDValue ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); @@ -2789,18 +2695,10 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); SDValue Vec = Op.getOperand(0); SDValue Lane = Op.getOperand(1); - - // FIXME: This is invalid for 8 and 16-bit elements - the information about - // sign / zero extension is lost! - Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); - Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT)); - - if (VT.bitsLT(MVT::i32)) - Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op); - else if (VT.bitsGT(MVT::i32)) - Op = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op); - - return Op; + assert(VT == MVT::i32 && + Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && + "unexpected type for custom-lowering vector extract"); + return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); } static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { @@ -2844,8 +2742,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::RETURNADDR: break; case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); - case ISD::INTRINSIC_VOID: - case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); case ISD::SHL: @@ -2888,7 +2784,8 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const { + MachineBasicBlock *BB, + DenseMap *EM) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { @@ -2919,12 +2816,15 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, F->insert(It, sinkMBB); // Update machine-CFG edges by first adding all successors of the current // block to the new block which will contain the Phi node for the select. - for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), - e = BB->succ_end(); i != e; ++i) - sinkMBB->addSuccessor(*i); + // Also inform sdisel of the edge changes. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) { + EM->insert(std::make_pair(*I, sinkMBB)); + sinkMBB->addSuccessor(*I); + } // Next, remove all successors of the current block, and add the true // and fallthrough blocks as its successors. - while(!BB->succ_empty()) + while (!BB->succ_empty()) BB->removeSuccessor(BB->succ_begin()); BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); @@ -4069,3 +3969,9 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, Ops, DAG); } + +bool +ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { + // The ARM target isn't yet aware of offsets. + return false; +}