X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrFormats.td;h=8a7603ad9096129c4f43f0bbca5a5f2397e638fb;hb=bdf714450b70509538aa5a8a676034418ce827b6;hp=80aa24e3f461b8b34f61b29a3f784bab0994f771;hpb=a0d2c8a40f890345237abfa9cece16c517e1e280;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 80aa24e3f46..8a7603ad909 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1,4 +1,4 @@ -//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// +//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// // // The LLVM Compiler Infrastructure // @@ -71,7 +71,7 @@ def NVTBLFrm : Format<41>; // Misc flags. -// the instruction has a Rn register operand. +// The instruction has an Rn register operand. // UnaryDP - Indicates this is a unary data processing instruction, i.e. // it doesn't have a Rn operand. class UnaryDP { bit isUnaryDataProc = 1; } @@ -135,7 +135,6 @@ def NeonDomain : Domain<2>; // Instructions in Neon domain only def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains //===----------------------------------------------------------------------===// - // ARM special operands. // @@ -144,6 +143,11 @@ def CondCodeOperand : AsmOperandClass { let SuperClasses = []; } +def CCOutOperand : AsmOperandClass { + let Name = "CCOut"; + let SuperClasses = []; +} + // ARM Predicate operand. Default to 14 = always (AL). Second part is CC // register whose default is 0 (no register). def pred : PredicateOperand { let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; + let ParserMatchClass = CCOutOperand; } // Same as cc_out except it defaults to setting CPSR. def s_cc_out : OptionalDefOperand { let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; + let ParserMatchClass = CCOutOperand; } // ARM special operands for disassembly only. @@ -185,7 +191,6 @@ def neg_zero : Operand { } //===----------------------------------------------------------------------===// - // ARM Instruction templates. // @@ -754,12 +759,9 @@ class ARMV6Pat : Pat { } //===----------------------------------------------------------------------===// -// // Thumb Instruction Format Definitions. // -// TI - Thumb instruction. - class ThumbI pattern> : InstThumb { @@ -770,6 +772,7 @@ class ThumbI Predicates = [IsThumb]; } +// TI - Thumb instruction. class TI pattern> : ThumbI; @@ -839,7 +842,7 @@ class T1sI pattern> : Thumb1sI; + "$Rn = $Rdn", pattern>; // Thumb1 instruction that can be predicated. class Thumb1pI pattern> : Thumb1pI; + "$Rn = $Rdn", pattern>; -class T1pI1 pattern> - : Thumb1pI; -class T1pI2 pattern> - : Thumb1pI; -class T1pI4 pattern> - : Thumb1pI; class T1pIs pattern> : Thumb1pI; @@ -908,12 +902,37 @@ class T1LoadStore opA, bits<3> opB> : Encoding16 { let Inst{15-12} = opA; let Inst{11-9} = opB; } -class T1LdSt opB> : T1LoadStore<0b0101, opB>; -class T1LdSt4Imm opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes -class T1LdSt1Imm opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte -class T1LdSt2Imm opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes class T1LdStSP opB> : T1LoadStore<0b1001, opB>; // SP relative +// Helper classes to encode Thumb1 loads and stores. For immediates, the +// following bits are used for "opA" (see A6.2.4): +// +// 0b0110 => Immediate, 4 bytes +// 0b1000 => Immediate, 2 bytes +// 0b0111 => Immediate, 1 byte +class T1pILdStEncode opcode, dag oops, dag iops, AddrMode am, + InstrItinClass itin, string opc, string asm, + list pattern> + : Thumb1pI, + T1LoadStore<0b0101, opcode> { + bits<3> Rt; + bits<8> addr; + let Inst{8-6} = addr{5-3}; // Rm + let Inst{5-3} = addr{2-0}; // Rn + let Inst{2-0} = Rt; +} +class T1pILdStEncodeImm opA, bit opB, dag oops, dag iops, AddrMode am, + InstrItinClass itin, string opc, string asm, + list pattern> + : Thumb1pI, + T1LoadStore { + bits<3> Rt; + bits<8> addr; + let Inst{10-6} = addr{7-3}; // imm5 + let Inst{5-3} = addr{2-0}; // Rn + let Inst{2-0} = Rt; +} + // A6.2.5 Miscellaneous 16-bit instructions encoding. class T1Misc opcode> : Encoding16 { let Inst{15-12} = 0b1011; @@ -942,6 +961,9 @@ class Thumb2sI pattern> : InstARM { + bits<1> s; // condition-code set flag ('1' if the insn should set the flags) + let Inst{20} = s; + let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); let AsmString = !strconcat(opc, "${s}${p}", asm); @@ -998,6 +1020,15 @@ class T2Ii8s4 Rt; + bits<4> Rt2; + bits<13> addr; + let Inst{15-12} = Rt{3-0}; + let Inst{11-8} = Rt2{3-0}; + let Inst{19-16} = addr{12-9}; + let Inst{23} = addr{8}; + let Inst{7-0} = addr{7-0}; } class T2sI Predicates = [HasVFP2]; } @@ -1094,13 +1126,16 @@ class VFPXI Predicates = [HasVFP2]; } class VFPAI pattern> : VFPI; + opc, asm, "", pattern> { + let PostEncoderMethod = "VFPThumb2PostEncoder"; +} // ARM VFP addrmode5 loads and stores class ADI5 opcod1, bits<2> opcod2, dag oops, dag iops, @@ -1281,8 +1316,8 @@ class ASuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, let Inst{4} = opcod5; } -// Single precision unary, if no NEON -// Same as ASuI except not available if NEON is enabled +// Single precision unary, if no NEON. Same as ASuI except not available if +// NEON is enabled. class ASuIn opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> @@ -1316,8 +1351,8 @@ class ASbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, let Inst{4} = op4; } -// Single precision binary, if no NEON -// Same as ASbI except not available if NEON is enabled +// Single precision binary, if no NEON. Same as ASbI except not available if +// NEON is enabled. class ASbIn opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern>