X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrInfo.h;h=4ce90fc56640ed801814c3c37032a7ce52ae2dcd;hb=e6be34a53ecbe8c2ff9f0793b13d847e94c0de91;hp=db52a2dbc776a345e5a62cb3b4b908ba951f0be6;hpb=1ee29257428960fede862fcfdbe80d5d007927e9;p=oota-llvm.git

diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index db52a2dbc77..4ce90fc5664 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -2,8 +2,7 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the "Instituto Nokia de Tecnologia" and
-// is distributed under the University of Illinois Open Source
+// This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
@@ -34,6 +33,7 @@ namespace ARMII {
     // so that we can tell if we forgot to set a value.
 
     AddrModeMask  = 0xf,
+    AddrModeNone  = 0,
     AddrMode1     = 1,
     AddrMode2     = 2,
     AddrMode3     = 3,
@@ -61,11 +61,71 @@ namespace ARMII {
     
     // Opcode
     OpcodeShift   = 9,
-    OpcodeMask    = 0xf << OpcodeShift
+    OpcodeMask    = 0xf << OpcodeShift,
+    
+    // Format
+    FormShift   = 13,
+    FormMask    = 31 << FormShift,
+
+    // Pseudo instructions
+    Pseudo      = 1 << FormShift,
+
+    // Multiply instructions
+    MulFrm      = 2 << FormShift,
+    MulSMLAW    = 3 << FormShift,
+    MulSMULW    = 4 << FormShift,
+    MulSMLA     = 5 << FormShift,
+    MulSMUL     = 6 << FormShift,
+
+    // Branch instructions
+    Branch      = 7 << FormShift,
+    BranchMisc  = 8 << FormShift,
+
+    // Data Processing instructions
+    DPRdIm      = 9 << FormShift,
+    DPRdReg     = 10 << FormShift,
+    DPRdSoReg   = 11 << FormShift,
+    DPRdMisc    = 12 << FormShift,
+
+    DPRnIm      = 13 << FormShift,
+    DPRnReg     = 14 << FormShift,
+    DPRnSoReg   = 15 << FormShift,
+
+    DPRIm       = 16 << FormShift,
+    DPRReg      = 17 << FormShift,
+    DPRSoReg    = 18 << FormShift,
+
+    DPRImS      = 19 << FormShift,
+    DPRRegS     = 20 << FormShift,
+    DPRSoRegS   = 21 << FormShift,
+
+    // Load and Store
+    LdFrm       = 22 << FormShift,
+    StFrm       = 23 << FormShift,
+
+    // Miscellaneous arithmetic instructions
+    ArithMisc   = 24 << FormShift,
+
+    // Thumb format
+    ThumbFrm    = 25 << FormShift,
+
+    // VFP format
+    VPFFrm      = 26 << FormShift,
+
+    // Field shifts - such shifts are used to set field while generating
+    // machine instructions.
+    RegRsShift  = 8,
+    RegRdShift  = 12,
+    RegRnShift  = 16,
+    L_BitShift  = 20,
+    S_BitShift  = 20,
+    U_BitShift  = 23,
+    IndexShift  = 24,
+    I_BitShift  = 25
   };
 }
 
-class ARMInstrInfo : public TargetInstrInfo {
+class ARMInstrInfo : public TargetInstrInfoImpl {
   const ARMRegisterInfo RI;
 public:
   ARMInstrInfo(const ARMSubtarget &STI);
@@ -74,7 +134,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.
@@ -96,14 +156,84 @@ public:
   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                              MachineBasicBlock *&FBB,
                              std::vector<MachineOperand> &Cond) const;
-  virtual void RemoveBranch(MachineBasicBlock &MBB) const;
-  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                            MachineBasicBlock *FBB,
-                            const std::vector<MachineOperand> &Cond) const;
+  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                                MachineBasicBlock *FBB,
+                                const std::vector<MachineOperand> &Cond) const;
+  virtual void copyRegToReg(MachineBasicBlock &MBB,
+                            MachineBasicBlock::iterator I,
+                            unsigned DestReg, unsigned SrcReg,
+                            const TargetRegisterClass *DestRC,
+                            const TargetRegisterClass *SrcRC) const;
+  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator MBBI,
+                                   unsigned SrcReg, bool isKill, int FrameIndex,
+                                   const TargetRegisterClass *RC) const;
+
+  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+                              SmallVectorImpl<MachineOperand> &Addr,
+                              const TargetRegisterClass *RC,
+                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                    MachineBasicBlock::iterator MBBI,
+                                    unsigned DestReg, int FrameIndex,
+                                    const TargetRegisterClass *RC) const;
+
+  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                               SmallVectorImpl<MachineOperand> &Addr,
+                               const TargetRegisterClass *RC,
+                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
+  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                         MachineBasicBlock::iterator MI,
+                                 const std::vector<CalleeSavedInfo> &CSI) const;
+  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+                                           MachineBasicBlock::iterator MI,
+                                 const std::vector<CalleeSavedInfo> &CSI) const;
+  
+  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+                                          MachineInstr* MI,
+                                          SmallVectorImpl<unsigned> &Ops,
+                                          int FrameIndex) const;
+
+  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+                                          MachineInstr* MI,
+                                          SmallVectorImpl<unsigned> &Ops,
+                                          MachineInstr* LoadMI) const {
+    return 0;
+  }
+
+  virtual bool canFoldMemoryOperand(MachineInstr *MI,
+                                    SmallVectorImpl<unsigned> &Ops) const;
+  
   virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
+
+  // Predication support.
+  virtual bool isPredicated(const MachineInstr *MI) const;
+
+  virtual
+  bool PredicateInstruction(MachineInstr *MI,
+                            const std::vector<MachineOperand> &Pred) const;
+
+  virtual
+  bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+                         const std::vector<MachineOperand> &Pred2) const;
+
+  virtual bool DefinesPredicate(MachineInstr *MI,
+                                std::vector<MachineOperand> &Pred) const;
 };
 
+  // Utility routines
+  namespace ARM {
+    /// GetInstSize - Returns the size of the specified MachineInstr.
+    ///
+    unsigned GetInstSize(MachineInstr *MI);
+
+    /// GetFunctionSize - Returns the size of the specified MachineFunction.
+    ///
+    unsigned GetFunctionSize(MachineFunction &MF);
+  }
 }
 
 #endif