X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrInfo.h;h=90f34ea08401397a6d2f97d0f49b916e8d5d254a;hb=12af22e8cc217827cf4f118b0f5e4ebbda9925ae;hp=d4199d1267fd8c12120601b0356b7b91be4774a3;hpb=864e2efce2cb5d02e376933933d96074723fe77c;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index d4199d1267f..90f34ea0840 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -1,4 +1,4 @@ -//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===// +//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,14 +11,11 @@ // //===----------------------------------------------------------------------===// -#ifndef ARMINSTRUCTIONINFO_H -#define ARMINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H +#define LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H -#include "llvm/Target/TargetInstrInfo.h" #include "ARMBaseInstrInfo.h" #include "ARMRegisterInfo.h" -#include "ARMSubtarget.h" -#include "ARM.h" namespace llvm { class ARMSubtarget; @@ -28,20 +25,22 @@ class ARMInstrInfo : public ARMBaseInstrInfo { public: explicit ARMInstrInfo(const ARMSubtarget &STI); + /// getNoopForMachoTarget - Return the noop instruction to use for a noop. + void getNoopForMachoTarget(MCInst &NopInst) const override; + // Return the non-pre/post incrementing version of 'Opc'. Return 0 // if there is not such an opcode. - unsigned getUnindexedOpcode(unsigned Opc) const; - - void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SubIdx, - const MachineInstr *Orig, - const TargetRegisterInfo *TRI) const; + unsigned getUnindexedOpcode(unsigned Opc) const override; /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - const ARMRegisterInfo &getRegisterInfo() const { return RI; } + const ARMRegisterInfo &getRegisterInfo() const override { return RI; } + +private: + void expandLoadStackGuard(MachineBasicBlock::iterator MI, + Reloc::Model RM) const override; }; }