X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrInfo.td;h=62f740be86e226267e53c98370841ac07ba77c2b;hb=c69d56f1154342a57c9bdd4c17a10333e3520127;hp=201f65c7f5a7f4923b9e83bcf63d8267e866df1d;hpb=64c88d741e51281edc15dcfc27dfaa500a89d43b;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 201f65c7f5a..62f740be86e 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2,8 +2,7 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the "Instituto Nokia de Tecnologia" and -// is distributed under the University of Illinois Open Source +// This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// @@ -17,7 +16,8 @@ // // Type profiles. -def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; +def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; @@ -39,21 +39,25 @@ def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; +def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; + // Node definitions. def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; -def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, - [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; +def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, + [SDNPHasChain, SDNPOutFlag]>; +def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet, +def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInFlag]>; def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, @@ -70,12 +74,17 @@ def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, [SDNPOutFlag]>; +def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, + [SDNPOutFlag]>; + def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; +def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; + //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // @@ -99,54 +108,57 @@ class RegConstraint { // so_imm_XFORM - Return a so_imm value packed into the format described for // so_imm def below. def so_imm_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(N->getValue()), + return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()), MVT::i32); }]>; // so_imm_neg_XFORM - Return a so_imm value packed into the format described for // so_imm_neg def below. def so_imm_neg_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()), + return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()), MVT::i32); }]>; // so_imm_not_XFORM - Return a so_imm value packed into the format described for // so_imm_not def below. def so_imm_not_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()), + return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()), MVT::i32); }]>; // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. def rot_imm : PatLeaf<(i32 imm), [{ - int32_t v = (int32_t)N->getValue(); + int32_t v = (int32_t)N->getZExtValue(); return v == 8 || v == 16 || v == 24; }]>; /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. def imm1_15 : PatLeaf<(i32 imm), [{ - return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16; + return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; }]>; /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. def imm16_31 : PatLeaf<(i32 imm), [{ - return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32; + return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; }]>; def so_imm_neg : - PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }], - so_imm_neg_XFORM>; + PatLeaf<(imm), [{ + return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; + }], so_imm_neg_XFORM>; def so_imm_not : - PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }], - so_imm_not_XFORM>; + PatLeaf<(imm), [{ + return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; + }], so_imm_not_XFORM>; // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. def sext_16_node : PatLeaf<(i32 GPR:$a), [{ - return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17; + return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; }]>; - +class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; +class UnOpFrag : PatFrag<(ops node:$Src), res>; //===----------------------------------------------------------------------===// // Operand Definitions. @@ -155,11 +167,6 @@ def sext_16_node : PatLeaf<(i32 GPR:$a), [{ // Branch target. def brtarget : Operand; -// Operand for printing out a condition code. -def CCOp : Operand { - let PrintMethod = "printCCOperand"; -} - // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand { let PrintMethod = "printRegisterList"; @@ -194,7 +201,7 @@ def so_reg : Operand, // reg reg imm // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. def so_imm : Operand, PatLeaf<(imm), - [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }], + [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }], so_imm_XFORM> { let PrintMethod = "printSOImmOperand"; } @@ -203,18 +210,19 @@ def so_imm : Operand, // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to // get the first/second pieces. def so_imm2part : Operand, - PatLeaf<(imm), - [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> { + PatLeaf<(imm), [{ + return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); + }]> { let PrintMethod = "printSOImm2PartOperand"; } def so_imm2part_1 : SDNodeXFormgetValue()); + unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); }]>; def so_imm2part_2 : SDNodeXFormgetValue()); + unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); }]>; @@ -275,6 +283,19 @@ def addrmodepc : Operand, let MIOperandInfo = (ops GPR, i32imm); } +// ARM Predicate operand. Default to 14 = always (AL). Second part is CC +// register whose default is 0 (no register). +def pred : PredicateOperand { + let PrintMethod = "printPredicateOperand"; +} + +// Conditional code result for instructions whose 's' bit is set, e.g. subs. +// +def cc_out : OptionalDefOperand { + let PrintMethod = "printSBitModifierOperand"; +} + //===----------------------------------------------------------------------===// // ARM Instruction flags. These need to match ARMInstrInfo.h. // @@ -313,169 +334,107 @@ def IndexModePre : IndexMode<1>; def IndexModePost : IndexMode<2>; //===----------------------------------------------------------------------===// -// ARM Instruction templates. -// - -// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. -class ARMPat : Pat { - list Predicates = [IsARM]; -} -class ARMV5TEPat : Pat { - list Predicates = [IsARM, HasV5TE]; -} -class ARMV6Pat : Pat { - list Predicates = [IsARM, HasV6]; -} -class InstARM opcod, AddrMode am, SizeFlagVal sz, IndexMode im, - dag ops, string asmstr, string cstr> - : Instruction { - let Namespace = "ARM"; - - bits<4> Opcode = opcod; - AddrMode AM = am; - bits<4> AddrModeBits = AM.Value; - - SizeFlagVal SZ = sz; - bits<3> SizeFlag = SZ.Value; - - IndexMode IM = im; - bits<2> IndexModeBits = IM.Value; - - dag OperandList = ops; - let AsmString = asmstr; - let Constraints = cstr; -} +include "ARMInstrFormats.td" -class PseudoInst pattern> - : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ops, asm, ""> { - let Pattern = pattern; -} +//===----------------------------------------------------------------------===// +// Multiclass helpers... +// -class I pattern> - // FIXME: Set all opcodes to 0 for now. - : InstARM<0, am, sz, im, ops, asm, cstr> { - let Pattern = pattern; - list Predicates = [IsARM]; +/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a +/// binop that produces a value. +multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode> { + def ri : AsI1; + def rr : AsI1; + def rs : AsI1; } -class AI pattern> - : I; -class AI1 pattern> - : I; -class AI2 pattern> - : I; -class AI3 pattern> - : I; -class AI4 pattern> - : I; -class AI1x2 pattern> - : I; - -// Pre-indexed ops -class AI2pr pattern> - : I; -class AI3pr pattern> - : I; - -// Post-indexed ops -class AI2po pattern> - : I; -class AI3po pattern> - : I; - -// BR_JT instructions -class JTI pattern> - : I; -class JTI1 pattern> - : I; -class JTI2 pattern> - : I; - - -class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; -class UnOpFrag : PatFrag<(ops node:$Src), res>; - - -/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a -/// binop that produces a value. -multiclass AI1_bin_irs { - def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), - !strconcat(opc, " $dst, $a, $b"), +/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the +/// instruction modifies the CSPR register. +let Defs = [CPSR] in { +multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> { + def ri : AI1; - def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, " $dst, $a, $b"), + def rr : AI1; - def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), - !strconcat(opc, " $dst, $a, $b"), + def rs : AI1; } +} -/// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns. -/// Similar to AI1_bin_irs except the instruction does not produce a result. -multiclass AI1_bin0_irs { - def ri : AI1<(ops GPR:$a, so_imm:$b), - !strconcat(opc, " $a, $b"), +/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test +/// patterns. Similar to AsI1_bin_irs except the instruction does not produce +/// a explicit result, only implicitly set CPSR. +let Defs = [CPSR] in { +multiclass AI1_cmp_irs opcod, string opc, PatFrag opnode> { + def ri : AI1; - def rr : AI1<(ops GPR:$a, GPR:$b), - !strconcat(opc, " $a, $b"), + def rr : AI1; - def rs : AI1<(ops GPR:$a, so_reg:$b), - !strconcat(opc, " $a, $b"), + def rs : AI1; } - -/// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop. -multiclass AI1_bin_is { - def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), - !strconcat(opc, " $dst, $a, $b"), - [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; - def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), - !strconcat(opc, " $dst, $a, $b"), - [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; -} - -/// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary -/// ops. -multiclass AI1_unary_irs { - def i : AI1<(ops GPR:$dst, so_imm:$a), - !strconcat(opc, " $dst, $a"), - [(set GPR:$dst, (opnode so_imm:$a))]>; - def r : AI1<(ops GPR:$dst, GPR:$a), - !strconcat(opc, " $dst, $a"), - [(set GPR:$dst, (opnode GPR:$a))]>; - def s : AI1<(ops GPR:$dst, so_reg:$a), - !strconcat(opc, " $dst, $a"), - [(set GPR:$dst, (opnode so_reg:$a))]>; } /// AI_unary_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -multiclass AI_unary_rrot { - def r : AI<(ops GPR:$dst, GPR:$Src), - !strconcat(opc, " $dst, $Src"), - [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>; - def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot), - !strconcat(opc, " $dst, $Src, ror $rot"), +/// FIXME: Remove the 'r' variant. Its rot_imm is zero. +multiclass AI_unary_rrot opcod, string opc, PatFrag opnode> { + def r : AExtI, + Requires<[IsARM, HasV6]> { + let Inst{19-16} = 0b1111; + } + def r_rot : AExtI, - Requires<[IsARM, HasV6]>; + Requires<[IsARM, HasV6]> { + let Inst{19-16} = 0b1111; + } } /// AI_bin_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. -multiclass AI_bin_rrot { - def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS), - !strconcat(opc, " $dst, $LHS, $RHS"), +multiclass AI_bin_rrot opcod, string opc, PatFrag opnode> { + def rr : AExtI, Requires<[IsARM, HasV6]>; - def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot), - !strconcat(opc, " $dst, $LHS, $RHS, ror $rot"), + def rr_rot : AExtI, Requires<[IsARM, HasV6]>; } +/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and +/// setting carry bit. But it can optionally set CPSR. +let Uses = [CPSR] in { +multiclass AsXI1_bin_c_irs opcod, string opc, PatFrag opnode> { + def ri : AXI1; + def rr : AXI1; + def rs : AXI1; +} +} //===----------------------------------------------------------------------===// // Instructions @@ -484,257 +443,355 @@ multiclass AI_bin_rrot { //===----------------------------------------------------------------------===// // Miscellaneous Instructions. // -def IMPLICIT_DEF_GPR : -PseudoInst<(ops GPR:$rD), - "@ IMPLICIT_DEF_GPR $rD", - [(set GPR:$rD, (undef))]>; - /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in /// the function. The first operand is the ID# for this instruction, the second /// is the index into the MachineConstantPool that this is, the third is the /// size in bytes of this constant pool entry. +let isNotDuplicable = 1 in def CONSTPOOL_ENTRY : -PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), +PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, + i32imm:$size), "${instid:label} ${cpidx:cpentry}", []>; +let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKUP : -PseudoInst<(ops i32imm:$amt), - "@ ADJCALLSTACKUP $amt", - [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>; +PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), + "@ ADJCALLSTACKUP $amt1", + [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; def ADJCALLSTACKDOWN : -PseudoInst<(ops i32imm:$amt), +PseudoInst<(outs), (ins i32imm:$amt, pred:$p), "@ ADJCALLSTACKDOWN $amt", - [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>; + [(ARMcallseq_start timm:$amt)]>; +} def DWARF_LOC : -PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file), +PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), ".loc $file, $line, $col", [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; -def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp), - "$cp:\n\tadd $dst, pc, $a", - [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; -let AddedComplexity = 10 in -def PICLD : AI2<(ops GPR:$dst, addrmodepc:$addr), - "${addr:label}:\n\tldr $dst, $addr", + +// Address computation and loads and stores in PIC mode. +let isNotDuplicable = 1 in { +def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), + Pseudo, "$cp:\n\tadd$p $dst, pc, $a", + [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; + +let AddedComplexity = 10 in { +let canFoldAsLoad = 1 in +def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; +def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", + [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; + +def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", + [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; + +def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", + [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; + +def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", + [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; +} +let AddedComplexity = 10 in { +def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr$p $src, $addr", + [(store GPR:$src, addrmodepc:$addr)]>; + +def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", + [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; + +def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", + [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; +} +} // isNotDuplicable = 1 + //===----------------------------------------------------------------------===// // Control Flow Instructions. // let isReturn = 1, isTerminator = 1 in - def BX_RET : AI<(ops), "bx lr", [(ARMretflag)]>; + def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> { + let Inst{7-4} = 0b0001; + let Inst{19-8} = 0b111111111111; + let Inst{27-20} = 0b00010010; +} // FIXME: remove when we have a way to marking a MI with these properties. -let isLoad = 1, isReturn = 1, isTerminator = 1 in - def LDM_RET : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops), - "ldm${addr:submode} $addr, $dst1", +// FIXME: $dst1 should be a def. But the extra ops must be in the end of the +// operand list. +// FIXME: Should pc be an implicit operand like PICADD, etc? +let isReturn = 1, isTerminator = 1 in + def LDM_RET : AXI4ld<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; -let isCall = 1, noResults = 1, +let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, - D0, D1, D2, D3, D4, D5, D6, D7] in { - def BL : AI<(ops i32imm:$func, variable_ops), - "bl ${func:call}", - [(ARMcall tglobaladdr:$func)]>; + D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { + def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + "bl ${func:call}", + [(ARMcall tglobaladdr:$func)]>; + + def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + "bl", " ${func:call}", + [(ARMcall_pred tglobaladdr:$func)]>; + // ARMv5T and above - def BLX : AI<(ops GPR:$dst, variable_ops), - "blx $dst", - [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>; + def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, + "blx $func", + [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> { + let Inst{7-4} = 0b0011; + let Inst{19-8} = 0b111111111111; + let Inst{27-20} = 0b00010010; + } + let Uses = [LR] in { // ARMv4T - def BX : AI<(ops GPR:$dst, variable_ops), - "bx $dst", - [(ARMcall_nolink GPR:$dst)]>; + def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops), + "mov lr, pc\n\tbx $func", + [(ARMcall_nolink GPR:$func)]>; } } -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { - def B : AI<(ops brtarget:$dst), "b $dst", - [(br bb:$dst)]>; - - def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id), - "mov pc, $dst \n$jt", - [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>; - def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id), - "ldr pc, $dst \n$jt", - [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt, - imm:$id)]>; - def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id), - "add pc, $dst, $idx \n$jt", - [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt, - imm:$id)]>; +let isBranch = 1, isTerminator = 1 in { + // B is "predicable" since it can be xformed into a Bcc. + let isBarrier = 1 in { + let isPredicable = 1 in + def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target", + [(br bb:$target)]>; + + let isNotDuplicable = 1, isIndirectBranch = 1 in { + def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + "mov pc, $target \n$jt", + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { + let Inst{20} = 0; // S Bit + let Inst{24-21} = 0b1101; + let Inst{27-26} = {0,0}; + } + def BR_JTm : JTI<(outs), + (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), + "ldr pc, $target \n$jt", + [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, + imm:$id)]> { + let Inst{20} = 1; // L bit + let Inst{21} = 0; // W bit + let Inst{22} = 0; // B bit + let Inst{24} = 1; // P bit + let Inst{27-26} = {0,1}; + } + def BR_JTadd : JTI<(outs), + (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), + "add pc, $target, $idx \n$jt", + [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, + imm:$id)]> { + let Inst{20} = 0; // S bit + let Inst{24-21} = 0b0100; + let Inst{27-26} = {0,0}; + } + } // isNotDuplicable = 1, isIndirectBranch = 1 + } // isBarrier = 1 + + // FIXME: should be able to write a pattern for ARMBrcond, but can't use + // a two-value operand where a dag node expects two operands. :( + def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), + "b", " $target", + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; } -let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in - def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst", - [(ARMbrcond bb:$dst, imm:$cc)]>; - //===----------------------------------------------------------------------===// // Load / store Instructions. // // Load -let isLoad = 1 in { -def LDR : AI2<(ops GPR:$dst, addrmode2:$addr), - "ldr $dst, $addr", +let canFoldAsLoad = 1 in +def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. -let isReMaterializable = 1 in -def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), - "ldr $dst, $addr", []>; +let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in +def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr", []>; // Loads with zero extension -def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr), - "ldrh $dst, $addr", +def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, + "ldr", "h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; -def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr), - "ldrb $dst, $addr", +def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", "b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; // Loads with sign extension -def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr), - "ldrsh $dst, $addr", +def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, + "ldr", "sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr), - "ldrsb $dst, $addr", +def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, + "ldr", "sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; +let mayLoad = 1 in { // Load doubleword -def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr), - "ldrd $dst, $addr", +def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, + "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed loads -def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), - "ldr $dst, $addr!", "$addr.base = $base_wb", []>; +def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), + (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; -def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset), - "ldr $dst, [$base], $offset", "$base = $base_wb", []>; +def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base, am2offset:$offset), LdFrm, + "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), - "ldrh $dst, $addr!", "$addr.base = $base_wb", []>; +def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdMiscFrm, + "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), - "ldrh $dst, [$base], $offset", "$base = $base_wb", []>; +def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdMiscFrm, + "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr), - "ldrb $dst, $addr!", "$addr.base = $base_wb", []>; +def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), + (ins addrmode2:$addr), LdFrm, + "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset), - "ldrb $dst, [$base], $offset", "$base = $base_wb", []>; +def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am2offset:$offset), LdFrm, + "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), - "ldrsh $dst, $addr!", "$addr.base = $base_wb", []>; +def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdMiscFrm, + "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), - "ldrsh $dst, [$base], $offset", "$base = $base_wb", []>; +def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdMiscFrm, + "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; -def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr), - "ldrsb $dst, $addr!", "$addr.base = $base_wb", []>; +def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdMiscFrm, + "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; -def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset), - "ldrsb $dst, [$base], $offset", "$base = $base_wb", []>; -} // isLoad +def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdMiscFrm, + "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; +} // Store -let isStore = 1 in { -def STR : AI2<(ops GPR:$src, addrmode2:$addr), - "str $src, $addr", +def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, + "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; // Stores with truncate -def STRH : AI3<(ops GPR:$src, addrmode3:$addr), - "strh $src, $addr", +def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, + "str", "h $src, $addr", [(truncstorei16 GPR:$src, addrmode3:$addr)]>; -def STRB : AI2<(ops GPR:$src, addrmode2:$addr), - "strb $src, $addr", +def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, + "str", "b $src, $addr", [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword -def STRD : AI3<(ops GPR:$src, addrmode3:$addr), - "strd $src, $addr", +let mayStore = 1 in +def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, + "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed stores -def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset), - "str $src, [$base, $offset]!", "$base = $base_wb", +def STR_PRE : AI2stwpr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, + "str", " $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; -def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), - "str $src, [$base], $offset", "$base = $base_wb", +def STR_POST : AI2stwpo<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", " $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; -def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), - "strh $src, [$base, $offset]!", "$base = $base_wb", +def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + "str", "h $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; -def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset), - "strh $src, [$base], $offset", "$base = $base_wb", +def STRH_POST: AI3sthpo<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + "str", "h $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; -def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), - "strb $src, [$base, $offset]!", "$base = $base_wb", +def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", "b $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; -def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset), - "strb $src, [$base], $offset", "$base = $base_wb", +def STRB_POST: AI2stbpo<(outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; -} // isStore //===----------------------------------------------------------------------===// // Load / store multiple Instructions. // -let isLoad = 1 in -def LDM : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops), - "ldm${addr:submode} $addr, $dst1", - []>; +// FIXME: $dst1 should be a def. +let mayLoad = 1 in +def LDM : AXI4ld<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", + []>; -let isStore = 1 in -def STM : AI4<(ops addrmode4:$addr, reglist:$src1, variable_ops), - "stm${addr:submode} $addr, $src1", - []>; +let mayStore = 1 in +def STM : AXI4st<(outs), + (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), + LdStMulFrm, "stm${p}${addr:submode} $addr, $src1", + []>; //===----------------------------------------------------------------------===// // Move Instructions. // -def MOVr : AI1<(ops GPR:$dst, GPR:$src), - "mov $dst, $src", []>; -def MOVs : AI1<(ops GPR:$dst, so_reg:$src), - "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>; +def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, + "mov", " $dst, $src", []>, UnaryDP; +def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, + "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP; -let isReMaterializable = 1 in -def MOVi : AI1<(ops GPR:$dst, so_imm:$src), - "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>; +let isReMaterializable = 1, isAsCheapAsAMove = 1 in +def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, + "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP; + +def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, + "mov", " $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; // These aren't really mov instructions, but we have to define them this way // due to flag operands. -def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src), - "movs $dst, $src, lsr #1", - [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; -def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), - "movs $dst, $src, asr #1", - [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; -def MOVrx : AI1<(ops GPR:$dst, GPR:$src), - "mov $dst, $src, rrx", - [(set GPR:$dst, (ARMrrx GPR:$src))]>; - +let Defs = [CPSR] in { +def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, + "mov", "s $dst, $src, lsr #1", + [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; +def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, + "mov", "s $dst, $src, asr #1", + [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; +} //===----------------------------------------------------------------------===// // Extend Instructions. @@ -742,31 +799,36 @@ def MOVrx : AI1<(ops GPR:$dst, GPR:$src), // Sign extenders -defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; -defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; +defm SXTB : AI_unary_rrot<0b01101010, + "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; +defm SXTH : AI_unary_rrot<0b01101011, + "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; -defm SXTAB : AI_bin_rrot<"sxtab", - BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; -defm SXTAH : AI_bin_rrot<"sxtah", - BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; +defm SXTAB : AI_bin_rrot<0b01101010, + "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; +defm SXTAH : AI_bin_rrot<0b01101011, + "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; // TODO: SXT(A){B|H}16 // Zero extenders let AddedComplexity = 16 in { -defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; -defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; -defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; +defm UXTB : AI_unary_rrot<0b01101110, + "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; +defm UXTH : AI_unary_rrot<0b01101111, + "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; +defm UXTB16 : AI_unary_rrot<0b01101100, + "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), (UXTB16r_rot GPR:$Src, 24)>; def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), (UXTB16r_rot GPR:$Src, 8)>; -defm UXTAB : AI_bin_rrot<"uxtab", +defm UXTAB : AI_bin_rrot<0b01101110, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; -defm UXTAH : AI_bin_rrot<"uxtah", +defm UXTAH : AI_bin_rrot<0b01101111, "uxtah", BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; } @@ -779,17 +841,51 @@ defm UXTAH : AI_bin_rrot<"uxtah", // Arithmetic Instructions. // -defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>; -defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>; -defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>; -defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm ADD : AsI1_bin_irs<0b0100, "add", + BinOpFrag<(add node:$LHS, node:$RHS)>>; +defm SUB : AsI1_bin_irs<0b0010, "sub", + BinOpFrag<(sub node:$LHS, node:$RHS)>>; + +// ADD and SUB with 's' bit set. +defm ADDS : ASI1_bin_s_irs<0b0100, "add", + BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm SUBS : ASI1_bin_s_irs<0b0010, "sub", + BinOpFrag<(subc node:$LHS, node:$RHS)>>; + +// FIXME: Do not allow ADC / SBC to be predicated for now. +defm ADC : AsXI1_bin_c_irs<0b0101, "adc", + BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm SBC : AsXI1_bin_c_irs<0b0110, "sbc", + BinOpFrag<(sube node:$LHS, node:$RHS)>>; // These don't define reg/reg forms, because they are handled above. -defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>; -defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>; -defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>; +def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, + "rsb", " $dst, $a, $b", + [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; + +def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, + "rsb", " $dst, $a, $b", + [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; + +// RSB with 's' bit set. +let Defs = [CPSR] in { +def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; +def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; +} + +// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. +let Uses = [CPSR] in { +def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), + DPFrm, "rsc${s} $dst, $a, $b", + [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; +def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), + DPSoRegFrm, "rsc${s} $dst, $a, $b", + [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; +} // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. def : ARMPat<(add GPR:$src, so_imm_neg:$imm), @@ -811,18 +907,25 @@ def : ARMPat<(add GPR:$src, so_imm_neg:$imm), // Bitwise Instructions. // -defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; -defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; -defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; -defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; - -def MVNr : AI<(ops GPR:$dst, GPR:$src), - "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; -def MVNs : AI<(ops GPR:$dst, so_reg:$src), - "mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; -let isReMaterializable = 1 in -def MVNi : AI<(ops GPR:$dst, so_imm:$imm), - "mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; +defm AND : AsI1_bin_irs<0b0000, "and", + BinOpFrag<(and node:$LHS, node:$RHS)>>; +defm ORR : AsI1_bin_irs<0b1100, "orr", + BinOpFrag<(or node:$LHS, node:$RHS)>>; +defm EOR : AsI1_bin_irs<0b0001, "eor", + BinOpFrag<(xor node:$LHS, node:$RHS)>>; +defm BIC : AsI1_bin_irs<0b1110, "bic", + BinOpFrag<(and node:$LHS, (not node:$RHS))>>; + +def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, + "mvn", " $dst, $src", + [(set GPR:$dst, (not GPR:$src))]>, UnaryDP; +def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, + "mvn", " $dst, $src", + [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP; +let isReMaterializable = 1, isAsCheapAsAMove = 1 in +def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, + "mvn", " $dst, $imm", + [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP; def : ARMPat<(and GPR:$src, so_imm_not:$imm), (BICri GPR:$src, so_imm_not:$imm)>; @@ -831,119 +934,173 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm), // Multiply Instructions. // -// AI_orr - Defines a (op r, r) pattern. -class AI_orr - : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, " $dst, $a, $b"), - [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; +def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + "mul", " $dst, $a, $b", + [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; -// AI_oorr - Defines a (op (op r, r), r) pattern. -class AI_oorr - : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), - !strconcat(opc, " $dst, $a, $b, $c"), - [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>; - -def MUL : AI_orr<"mul", mul>; -def MLA : AI_oorr<"mla", add, mul>; +def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + "mla", " $dst, $a, $b, $c", + [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; // Extra precision multiplies with low / high results -def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), - "smull $ldst, $hdst, $a, $b", - []>; +def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), + (ins GPR:$a, GPR:$b), + "smull", " $ldst, $hdst, $a, $b", []>; -def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), - "umull $ldst, $hdst, $a, $b", - []>; +def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), + (ins GPR:$a, GPR:$b), + "umull", " $ldst, $hdst, $a, $b", []>; // Multiply + accumulate -def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), - "smlal $ldst, $hdst, $a, $b", - []>; +def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), + (ins GPR:$a, GPR:$b), + "smlal", " $ldst, $hdst, $a, $b", []>; -def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), - "umlal $ldst, $hdst, $a, $b", - []>; +def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), + (ins GPR:$a, GPR:$b), + "umlal", " $ldst, $hdst, $a, $b", []>; -def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b), - "umaal $ldst, $hdst, $a, $b", - []>, Requires<[IsARM, HasV6]>; +def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), + (ins GPR:$a, GPR:$b), + "umaal", " $ldst, $hdst, $a, $b", []>, + Requires<[IsARM, HasV6]>; // Most significant word multiply -def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>; -def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>; +def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + "smmul", " $dst, $a, $b", + [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, + Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b0001; + let Inst{15-12} = 0b1111; +} + +def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + "smmla", " $dst, $a, $b, $c", + [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, + Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b0001; +} -def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c), - "smmls $dst, $a, $b, $c", +def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + "smmls", " $dst, $a, $b, $c", [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, - Requires<[IsARM, HasV6]>; + Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b1101; +} multiclass AI_smul { - def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "bb $dst, $a, $b"), + def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "bb"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16)))]>, - Requires<[IsARM, HasV5TE]>; - def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "bt $dst, $a, $b"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 0; + } + + def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "bt"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), (sra GPR:$b, 16)))]>, - Requires<[IsARM, HasV5TE]>; - def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "tb $dst, $a, $b"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 1; + } + + def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "tb"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sra GPR:$a, 16), (sext_inreg GPR:$b, i16)))]>, - Requires<[IsARM, HasV5TE]>; - def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "tt $dst, $a, $b"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 0; + } + + def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "tt"), " $dst, $a, $b", [(set GPR:$dst, (opnode (sra GPR:$a, 16), (sra GPR:$b, 16)))]>, - Requires<[IsARM, HasV5TE]>; - def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "wb $dst, $a, $b"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 1; + } + + def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "wb"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, (sext_inreg GPR:$b, i16)), 16))]>, - Requires<[IsARM, HasV5TE]>; - def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b), - !strconcat(opc, "wt $dst, $a, $b"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 0; + } + + def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + !strconcat(opc, "wt"), " $dst, $a, $b", [(set GPR:$dst, (sra (opnode GPR:$a, (sra GPR:$b, 16)), 16))]>, - Requires<[IsARM, HasV5TE]>; + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 1; + } } + multiclass AI_smla { - def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "bb $dst, $a, $b, $acc"), + def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "bb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), (sext_inreg GPR:$b, i16))))]>, - Requires<[IsARM, HasV5TE]>; - def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "bt $dst, $a, $b, $acc"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 0; + } + + def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "bt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), (sra GPR:$b, 16))))]>, - Requires<[IsARM, HasV5TE]>; - def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "tb $dst, $a, $b, $acc"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 1; + } + + def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "tb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), (sext_inreg GPR:$b, i16))))]>, - Requires<[IsARM, HasV5TE]>; - def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "tt $dst, $a, $b, $acc"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 0; + } + + def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "tt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), (sra GPR:$b, 16))))]>, - Requires<[IsARM, HasV5TE]>; + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 1; + let Inst{6} = 1; + } - def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "wb $dst, $a, $b, $acc"), + def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "wb"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, (sext_inreg GPR:$b, i16)), 16)))]>, - Requires<[IsARM, HasV5TE]>; - def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc), - !strconcat(opc, "wt $dst, $a, $b, $acc"), + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 0; + } + + def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), + !strconcat(opc, "wt"), " $dst, $a, $b, $acc", [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, (sra GPR:$b, 16)), 16)))]>, - Requires<[IsARM, HasV5TE]>; + Requires<[IsARM, HasV5TE]> { + let Inst{5} = 0; + let Inst{6} = 1; + } } defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; @@ -956,37 +1113,56 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; // Misc. Arithmetic Instructions. // -def CLZ : AI<(ops GPR:$dst, GPR:$src), - "clz $dst, $src", - [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; +def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), + "clz", " $dst, $src", + [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { + let Inst{7-4} = 0b0001; + let Inst{11-8} = 0b1111; + let Inst{19-16} = 0b1111; +} -def REV : AI<(ops GPR:$dst, GPR:$src), - "rev $dst, $src", - [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; +def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), + "rev", " $dst, $src", + [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b0011; + let Inst{11-8} = 0b1111; + let Inst{19-16} = 0b1111; +} -def REV16 : AI<(ops GPR:$dst, GPR:$src), - "rev16 $dst, $src", +def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), + "rev16", " $dst, $src", [(set GPR:$dst, (or (and (srl GPR:$src, 8), 0xFF), (or (and (shl GPR:$src, 8), 0xFF00), (or (and (srl GPR:$src, 8), 0xFF0000), (and (shl GPR:$src, 8), 0xFF000000)))))]>, - Requires<[IsARM, HasV6]>; + Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b1011; + let Inst{11-8} = 0b1111; + let Inst{19-16} = 0b1111; +} -def REVSH : AI<(ops GPR:$dst, GPR:$src), - "revsh $dst, $src", +def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), + "revsh", " $dst, $src", [(set GPR:$dst, (sext_inreg - (or (srl (and GPR:$src, 0xFFFF), 8), + (or (srl (and GPR:$src, 0xFF00), 8), (shl GPR:$src, 8)), i16))]>, - Requires<[IsARM, HasV6]>; + Requires<[IsARM, HasV6]> { + let Inst{7-4} = 0b1011; + let Inst{11-8} = 0b1111; + let Inst{19-16} = 0b1111; +} -def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), - "pkhbt $dst, $src1, $src2, LSL $shamt", +def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), + (ins GPR:$src1, GPR:$src2, i32imm:$shamt), + "pkhbt", " $dst, $src1, $src2, LSL $shamt", [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), (and (shl GPR:$src2, (i32 imm:$shamt)), 0xFFFF0000)))]>, - Requires<[IsARM, HasV6]>; + Requires<[IsARM, HasV6]> { + let Inst{6-4} = 0b001; +} // Alternate cases for PKHBT where identities eliminate some nodes. def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), @@ -995,11 +1171,14 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; -def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt), - "pkhtb $dst, $src1, $src2, ASR $shamt", +def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), + (ins GPR:$src1, GPR:$src2, i32imm:$shamt), + "pkhtb", " $dst, $src1, $src2, ASR $shamt", [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), (and (sra GPR:$src2, imm16_31:$shamt), - 0xFFFF)))]>, Requires<[IsARM, HasV6]>; + 0xFFFF)))]>, Requires<[IsARM, HasV6]> { + let Inst{6-4} = 0b101; +} // Alternate cases for PKHTB where identities eliminate some nodes. Note that // a shift amount of 0 is *not legal* here, it is PKHBT instead. @@ -1009,56 +1188,83 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; - //===----------------------------------------------------------------------===// // Comparison Instructions... // -defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; -defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; +defm CMP : AI1_cmp_irs<0b1010, "cmp", + BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; +defm CMN : AI1_cmp_irs<0b1011, "cmn", + BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; + +// Note that TST/TEQ don't set all the same flags that CMP does! +defm TST : AI1_cmp_irs<0b1000, "tst", + BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; +defm TEQ : AI1_cmp_irs<0b1001, "teq", + BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; + +defm CMPnz : AI1_cmp_irs<0b1010, "cmp", + BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; +defm CMNnz : AI1_cmp_irs<0b1011, "cmn", + BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), (CMNri GPR:$src, so_imm_neg:$imm)>; -// Note that TST/TEQ don't set all the same flags that CMP does! -def TSTrr : AI1<(ops GPR:$a, so_reg:$b), "tst $a, $b", []>; -def TSTri : AI1<(ops GPR:$a, so_imm:$b), "tst $a, $b", []>; -def TEQrr : AI1<(ops GPR:$a, so_reg:$b), "teq $a, $b", []>; -def TEQri : AI1<(ops GPR:$a, so_imm:$b), "teq $a, $b", []>; - -// Conditional moves -def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; +def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), + (CMNri GPR:$src, so_imm_neg:$imm)>; -def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>, - RegConstraint<"$false = $dst">; -def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>, - RegConstraint<"$false = $dst">; +// Conditional moves +// FIXME: should be able to write a pattern for ARMcmov, but can't use +// a two-value operand where a dag node expects two operands. :( +def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, + "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">, UnaryDP; + +def MOVCCs : AI1<0b1101, (outs GPR:$dst), + (ins GPR:$false, so_reg:$true), DPSoRegFrm, + "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">, UnaryDP; + +def MOVCCi : AI1<0b1101, (outs GPR:$dst), + (ins GPR:$false, so_imm:$true), DPFrm, + "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">, UnaryDP; // LEApcrel - Load a pc-relative address into a register without offending the // assembler. -def LEApcrel : AI1<(ops GPR:$dst, i32imm:$label), +def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+8))\n"), !strconcat("${:private}PCRELL${:uid}:\n\t", - "add $dst, pc, #PCRELV${:uid}")), + "add$p $dst, pc, #PCRELV${:uid}")), []>; -def LEApcrelJT : AI1<(ops GPR:$dst, i32imm:$label, i32imm:$id), +def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), + Pseudo, !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+8))\n"), !strconcat("${:private}PCRELL${:uid}:\n\t", - "add $dst, pc, #PCRELV${:uid}")), + "add$p $dst, pc, #PCRELV${:uid}")), []>; +//===----------------------------------------------------------------------===// +// TLS Instructions +// + +// __aeabi_read_tp preserves the registers r1-r3. +let isCall = 1, + Defs = [R0, R12, LR, CPSR] in { + def TPsoft : ABXI<0b1011, (outs), (ins), + "bl __aeabi_read_tp", + [(set R0, ARMthread_pointer)]>; +} + //===----------------------------------------------------------------------===// // Non-Instruction Patterns // @@ -1073,8 +1279,8 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), // Two piece so_imms. let isReMaterializable = 1 in -def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src), - "mov $dst, $src", +def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo, + "mov", " $dst, $src", [(set GPR:$dst, so_imm2part:$src)]>; def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), @@ -1098,13 +1304,8 @@ def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; -// truncstore i1 -> truncstore i8 -def : Pat<(truncstorei1 GPR:$src, addrmode2:$dst), - (STRB GPR:$src, addrmode2:$dst)>; -def : Pat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), - (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>; -def : Pat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), - (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>; +def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; +def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; // smul* and smla* def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),