X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrThumb2.td;h=d94b5c0c0d354740a7ebe176542e409925b8a72a;hb=09aa3f0ef35d9241c92439d74b8d5e9a81d814c2;hp=825b4f848b08192a8b43ce4fa52ac8cf7e8b9c9f;hpb=bdf714450b70509538aa5a8a676034418ce827b6;p=oota-llvm.git

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 825b4f848b0..d94b5c0c0d3 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -177,7 +177,7 @@ class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<12> imm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
@@ -191,7 +191,7 @@ class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> imm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
@@ -203,7 +203,7 @@ class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> imm;
 
-  let Inst{19-16}  = Rn{3-0};
+  let Inst{19-16}  = Rn;
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
@@ -216,7 +216,7 @@ class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<12> ShiftedRm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{3-0}   = ShiftedRm{3-0};
   let Inst{5-4}   = ShiftedRm{6-5};
   let Inst{14-12} = ShiftedRm{11-9};
@@ -229,7 +229,7 @@ class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<12> ShiftedRm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{3-0}   = ShiftedRm{3-0};
   let Inst{5-4}   = ShiftedRm{6-5};
   let Inst{14-12} = ShiftedRm{11-9};
@@ -242,7 +242,7 @@ class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> ShiftedRm;
 
-  let Inst{19-16} = Rn{3-0};
+  let Inst{19-16} = Rn;
   let Inst{3-0}   = ShiftedRm{3-0};
   let Inst{5-4}   = ShiftedRm{6-5};
   let Inst{14-12} = ShiftedRm{11-9};
@@ -255,8 +255,8 @@ class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<4> Rm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{3-0}   = Rm;
 }
 
 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
@@ -265,8 +265,8 @@ class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<4> Rm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{3-0}   = Rm;
 }
 
 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
@@ -275,8 +275,8 @@ class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<4> Rm;
 
-  let Inst{19-16} = Rn{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{19-16} = Rn;
+  let Inst{3-0}   = Rm;
 }
 
 
@@ -284,10 +284,14 @@ class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : T2I<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
-  bits<4> Rm;
+  bits<4> Rn;
+  bits<12> imm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{26}    = imm{11};
+  let Inst{14-12} = imm{10-8};
+  let Inst{7-0}   = imm{7-0};
 }
 
 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
@@ -297,8 +301,8 @@ class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> imm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
@@ -311,8 +315,8 @@ class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rm;
   bits<5> imm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{3-0}   = Rm;
   let Inst{14-12} = imm{4-2};
   let Inst{7-6}   = imm{1-0};
 }
@@ -324,8 +328,8 @@ class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rm;
   bits<5> imm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{3-0}   = Rm;
   let Inst{14-12} = imm{4-2};
   let Inst{7-6}   = imm{1-0};
 }
@@ -337,9 +341,9 @@ class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<4> Rm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{3-0}   = Rm;
 }
 
 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
@@ -349,9 +353,9 @@ class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<4> Rm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{3-0}   = Rm;
 }
 
 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
@@ -361,8 +365,8 @@ class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> ShiftedRm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
   let Inst{3-0}   = ShiftedRm{3-0};
   let Inst{5-4}   = ShiftedRm{6-5};
   let Inst{14-12} = ShiftedRm{11-9};
@@ -376,8 +380,8 @@ class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rn;
   bits<12> ShiftedRm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
   let Inst{3-0}   = ShiftedRm{3-0};
   let Inst{5-4}   = ShiftedRm{6-5};
   let Inst{14-12} = ShiftedRm{11-9};
@@ -392,10 +396,28 @@ class T2FourReg<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rm;
   bits<4> Ra;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
-  let Inst{3-0}   = Rm{3-0};
-  let Inst{15-12} = Ra{3-0};
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = Ra;
+  let Inst{11-8}  = Rd;
+  let Inst{3-0}   = Rm;
+}
+
+class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
+                dag oops, dag iops, InstrItinClass itin,
+                string opc, string asm, list<dag> pattern>
+  : T2I<oops, iops, itin, opc, asm, pattern> {
+  bits<4> RdLo;
+  bits<4> RdHi;
+  bits<4> Rn;
+  bits<4> Rm;
+
+  let Inst{31-23} = 0b111110111;
+  let Inst{22-20} = opc22_20;
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = RdLo;
+  let Inst{11-8}  = RdHi;
+  let Inst{7-4}   = opc7_4;
+  let Inst{3-0}   = Rm;
 }
 
 
@@ -587,16 +609,23 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
    }
    }
    // 12-bit imm
-   def ri12 : T2TwoRegImm<
+   def ri12 : T2I<
                   (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
                   !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
                   [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
+     bits<4> Rd;
+     bits<4> Rn;
+     bits<12> imm;
      let Inst{31-27} = 0b11110;
-     let Inst{25} = 1;
-     let Inst{24} = 0;
+     let Inst{26} = imm{11};
+     let Inst{25-24} = 0b10;
      let Inst{23-21} = op23_21;
      let Inst{20} = 0; // The S bit.
+     let Inst{19-16} = Rn;
      let Inst{15} = 0;
+     let Inst{14-12} = imm{10-8};
+     let Inst{11-8} = Rd;
+     let Inst{7-0} = imm{7-0};
    }
    // register
    def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
@@ -824,7 +853,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
     let Inst{20} = 1; // load
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<17> addr;
     let Inst{19-16} = addr{16-13}; // Rn
@@ -846,7 +875,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
     let Inst{8} = 0; // The W bit.
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<13> addr;
     let Inst{19-16} = addr{12-9}; // Rn
@@ -865,7 +894,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
     let Inst{11-6} = 0b000000;
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<10> addr;
     let Inst{19-16} = addr{9-6}; // Rn
@@ -889,7 +918,7 @@ multiclass T2I_st<bits<2> opcod, string opc,
     let Inst{20} = 0; // !load
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<17> addr;
     let Inst{19-16} = addr{16-13}; // Rn
@@ -909,7 +938,7 @@ multiclass T2I_st<bits<2> opcod, string opc,
     let Inst{8} = 0; // The W bit.
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<13> addr;
     let Inst{19-16} = addr{12-9}; // Rn
@@ -926,7 +955,7 @@ multiclass T2I_st<bits<2> opcod, string opc,
     let Inst{11-6} = 0b000000;
 
     bits<4> Rt;
-    let Inst{15-12} = Rt{3-0};
+    let Inst{15-12} = Rt;
 
     bits<10> addr;
     let Inst{19-16}   = addr{9-6}; // Rn
@@ -1090,7 +1119,7 @@ class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
   bits<4> Rd;
   bits<12> label;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{26}    = label{11};
   let Inst{14-12} = label{10-8};
   let Inst{7-0}   = label{7-0};
@@ -1125,59 +1154,55 @@ def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
   let Inst{15} = 0;
 }
 
+
+// FIXME: None of these add/sub SP special instructions should be necessary
+// at all for thumb2 since they use the same encodings as the generic
+// add/sub instructions. In thumb1 we need them since they have dedicated
+// encodings. At the least, they should be pseudo instructions.
 // ADD r, sp, {so_imm|i12}
-def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
-                        IIC_iALUi, "add", ".w\t$Rd, $sp, $imm", []> {
+def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
+                        IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 0;
   let Inst{24-21} = 0b1000;
-  let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
-def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
-                       IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
+def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
+                       IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
-  let Inst{25} = 1;
-  let Inst{24-21} = 0b0000;
-  let Inst{20} = 0; // The S bit.
-  let Inst{19-16} = 0b1101; // Rn = sp
+  let Inst{25-20} = 0b100000;
   let Inst{15} = 0;
 }
 
 // ADD r, sp, so_reg
 def t2ADDrSPs   : T2sTwoRegShiftedReg<
-                        (outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$ShiftedRm),
-                        IIC_iALUsi, "add", ".w\t$Rd, $sp, $ShiftedRm", []> {
+                        (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
+                        IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b1000;
-  let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
 
 // SUB r, sp, {so_imm|i12}
-def t2SUBrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
-                        IIC_iALUi, "sub", ".w\t$Rd, $sp, $imm", []> {
+def t2SUBrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
+                        IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 0;
   let Inst{24-21} = 0b1101;
-  let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
-def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
-                       IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
+def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm),
+                       IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
-  let Inst{25} = 1;
-  let Inst{24-21} = 0b0101;
-  let Inst{20} = 0; // The S bit.
-  let Inst{19-16} = 0b1101; // Rn = sp
+  let Inst{25-20} = 0b101010;
   let Inst{15} = 0;
 }
 
 // SUB r, sp, so_reg
-def t2SUBrSPs   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$imm),
+def t2SUBrSPs   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
                        IIC_iALUsi,
-                       "sub", "\t$Rd, $sp, $imm", []> {
+                       "sub", "\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b1101;
@@ -1371,7 +1396,7 @@ class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
 
   bits<4> Rt;
   bits<13> addr;
-  let Inst{15-12} = Rt{3-0};
+  let Inst{15-12} = Rt;
   let Inst{19-16} = addr{12-9};
   let Inst{7-0}   = addr{7-0};
 }
@@ -1456,7 +1481,7 @@ class T2IstT<bits<2> type, string opc, InstrItinClass ii>
 
   bits<4> Rt;
   bits<13> addr;
-  let Inst{15-12} = Rt{3-0};
+  let Inst{15-12} = Rt;
   let Inst{19-16} = addr{12-9};
   let Inst{7-0}   = addr{7-0};
 }
@@ -1666,7 +1691,7 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
   bits<4> Rd;
   bits<16> imm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
@@ -1687,7 +1712,7 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
   bits<4> Rd;
   bits<16> imm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
@@ -1833,9 +1858,9 @@ class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
   bits<4> Rn;
   bits<4> Rm;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
-  let Inst{3-0}   = Rm{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{3-0}   = Rm;
 }
 
 // Saturating add/subtract -- for disassembly only
@@ -1933,8 +1958,8 @@ class T2SatI<dag oops, dag iops, InstrItinClass itin,
   bits<5> sat_imm;
   bits<7> sh;
 
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
   let Inst{4-0}   = sat_imm{4-0};
   let Inst{21}    = sh{6};
   let Inst{14-12} = sh{4-2};
@@ -2068,7 +2093,7 @@ class T2BitFI<dag oops, dag iops, InstrItinClass itin,
   bits<5> msb;
   bits<5> lsb;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{4-0}   = msb{4-0};
   let Inst{14-12} = lsb{4-2};
   let Inst{7-6}   = lsb{1-0};
@@ -2079,7 +2104,7 @@ class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
     : T2BitFI<oops, iops, itin, opc, asm, pattern> {
   bits<4> Rn;
 
-  let Inst{19-16} = Rn{3-0};
+  let Inst{19-16} = Rn;
 }
 
 let Constraints = "$src = $Rd" in
@@ -2192,54 +2217,32 @@ def t2MLS: T2FourReg<
 // Extra precision multiplies with low / high results
 let neverHasSideEffects = 1 in {
 let isCommutable = 1 in {
-def t2SMULL : T2FourReg<
+def t2SMULL : T2MulLong<0b000, 0b0000,
                   (outs rGPR:$Rd, rGPR:$Ra),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
-                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b000;
-  let Inst{7-4} = 0b0000;
-}
+                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
 
-def t2UMULL : T2FourReg<
-                  (outs rGPR:$Rd, rGPR:$Ra),
+def t2UMULL : T2MulLong<0b010, 0b0000,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
-                   "umull", "\t$Rd, $Ra, $Rn, $Rm", []> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b010;
-  let Inst{7-4} = 0b0000;
-}
+                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 } // isCommutable
 
 // Multiply + accumulate
-def t2SMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2SMLAL : T2MulLong<0b100, 0b0000,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "smlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b100;
-  let Inst{7-4} = 0b0000;
-}
+                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 
-def t2UMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2UMLAL : T2MulLong<0b110, 0b0000,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "umlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b110;
-  let Inst{7-4} = 0b0000;
-}
+                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 
-def t2UMAAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2UMAAL : T2MulLong<0b110, 0b0110,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "umaal", "\t$Ra, $Rd, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b110;
-  let Inst{7-4} = 0b0110;
-}
+                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 } // neverHasSideEffects
 
 // Rounding variants of the below included for disassembly only
@@ -2532,7 +2535,7 @@ class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
   let Inst{15-12} = 0b1111;
   let Inst{7-6} = 0b10;
   let Inst{5-4} = op2;
-  let Rn{3-0} = Rm{3-0};
+  let Rn{3-0} = Rm;
 }
 
 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
@@ -2696,7 +2699,7 @@ def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
   bits<4> Rd;
   bits<16> imm;
 
-  let Inst{11-8}  = Rd{3-0};
+  let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
@@ -2795,8 +2798,8 @@ class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
 
   bits<4> Rn;
   bits<4> Rt;
-  let Inst{19-16} = Rn{3-0};
-  let Inst{15-12} = Rt{3-0};
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = Rt;
 }
 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
                 InstrItinClass itin, string opc, string asm, string cstr,
@@ -2811,9 +2814,9 @@ class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rt;
-  let Inst{11-8}  = Rd{3-0};
-  let Inst{19-16} = Rn{3-0};
-  let Inst{15-12} = Rt{3-0};
+  let Inst{11-8}  = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = Rt;
 }
 
 let mayLoad = 1 in {
@@ -2837,7 +2840,7 @@ def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
                          "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
                          [], {?, ?, ?, ?}> {
   bits<4> Rt2;
-  let Inst{11-8} = Rt2{3-0};
+  let Inst{11-8} = Rt2;
 }
 }
 
@@ -2862,7 +2865,7 @@ def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
                          "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
                          {?, ?, ?, ?}> {
   bits<4> Rt2;
-  let Inst{11-8} = Rt2{3-0};
+  let Inst{11-8} = Rt2;
 }
 }
 
@@ -3020,13 +3023,16 @@ def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 0;
+  
+  bits<4> p;
+  let Inst{25-22} = p;
 
-  bits<20> target;
-  let Inst{26} = target{19};
-  let Inst{11} = target{18};
-  let Inst{13} = target{17};
-  let Inst{21-16} = target{16-11};
-  let Inst{10-0} = target{10-0};
+  bits<21> target;
+  let Inst{26} = target{20};
+  let Inst{11} = target{19};
+  let Inst{13} = target{18};
+  let Inst{21-16} = target{17-12};
+  let Inst{10-0} = target{11-1};
 }
 
 
@@ -3041,8 +3047,8 @@ def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
 
   bits<4> cc;
   bits<4> mask;
-  let Inst{7-4} = cc{3-0};
-  let Inst{3-0} = mask{3-0};
+  let Inst{7-4} = cc;
+  let Inst{3-0} = mask;
 }
 
 // Branch and Exchange Jazelle -- for disassembly only
@@ -3056,7 +3062,7 @@ def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
   let Inst{12} = 0;
 
   bits<4> func;
-  let Inst{19-16} = func{3-0};
+  let Inst{19-16} = func;
 }
 
 // Change Processor State is a system instruction -- for disassembly only.
@@ -3122,7 +3128,7 @@ def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
   let Inst{7-4} = 0b1111;
 
   bits<4> opt;
-  let Inst{3-0} = opt{3-0};
+  let Inst{3-0} = opt;
 }
 
 // Secure Monitor Call is a system instruction -- for disassembly only
@@ -3134,7 +3140,7 @@ def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
   let Inst{15-12} = 0b1000;
 
   bits<4> opt;
-  let Inst{19-16} = opt{3-0};
+  let Inst{19-16} = opt;
 }
 
 class T2SRS<bits<12> op31_20,
@@ -3169,7 +3175,7 @@ class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
   let Inst{31-20} = op31_20{11-0};
 
   bits<4> Rn;
-  let Inst{19-16} = Rn{3-0};
+  let Inst{19-16} = Rn;
 }
 
 def t2RFEDBW : T2RFE<0b111010000011,
@@ -3235,7 +3241,7 @@ class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
           string opc, string asm, list<dag> pattern>
   : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
   bits<4> Rd;
-  let Inst{11-8} = Rd{3-0};
+  let Inst{11-8} = Rd;
 }
 
 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
@@ -3251,8 +3257,8 @@ class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
   : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
   bits<4> Rn;
   bits<4> mask;
-  let Inst{19-16} = Rn{3-0};
-  let Inst{11-8} = mask{3-0};
+  let Inst{19-16} = Rn;
+  let Inst{11-8} = mask;
 }
 
 def t2MSR : T2MSR<0b111100111000, 0b10, 0,