X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMRegisterInfo.td;h=61c77e64acf78144e5172a1738a52b06b1d8e71d;hb=e6be34a53ecbe8c2ff9f0793b13d847e94c0de91;hp=4e093fdae7fc36a1c2cdd42edad5f94c556a5c6c;hpb=cb20998b3f853f8ce78485941225310697b9e5ea;p=oota-llvm.git

diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 4e093fdae7f..61c77e64acf 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -2,8 +2,7 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the "Instituto Nokia de Tecnologia" and
-// is distributed under the University of Illinois Open Source
+// This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
@@ -13,10 +12,10 @@
 //===----------------------------------------------------------------------===//
 
 // Registers are identified with 4-bit ID numbers.
-class ARMReg<bits<4> num, string n, list<Register> aliases = []> : Register<n> {
+class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
   field bits<4> Num;
   let Namespace = "ARM";
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }
 
 class ARMFReg<bits<5> num, string n> : Register<n> {
@@ -25,22 +24,22 @@ class ARMFReg<bits<5> num, string n> : Register<n> {
 }
 
 // Integer registers
-def R0  : ARMReg< 0, "r0">,  DwarfRegNum<0>;
-def R1  : ARMReg< 1, "r1">,  DwarfRegNum<1>;
-def R2  : ARMReg< 2, "r2">,  DwarfRegNum<2>;
-def R3  : ARMReg< 3, "r3">,  DwarfRegNum<3>;
-def R4  : ARMReg< 4, "r4">,  DwarfRegNum<4>;
-def R5  : ARMReg< 5, "r5">,  DwarfRegNum<5>;
-def R6  : ARMReg< 6, "r6">,  DwarfRegNum<6>;
-def R7  : ARMReg< 7, "r7">,  DwarfRegNum<7>;
-def R8  : ARMReg< 8, "r8">,  DwarfRegNum<8>;
-def R9  : ARMReg< 9, "r9">,  DwarfRegNum<9>;
-def R10 : ARMReg<10, "r10">, DwarfRegNum<10>;
-def R11 : ARMReg<11, "r11">, DwarfRegNum<11>;
-def R12 : ARMReg<12, "r12">, DwarfRegNum<12>;
-def SP  : ARMReg<13, "sp">,  DwarfRegNum<13>;
-def LR  : ARMReg<14, "lr">,  DwarfRegNum<14>;
-def PC  : ARMReg<15, "pc">,  DwarfRegNum<15>;
+def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
+def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
+def R2  : ARMReg< 2, "r2">,  DwarfRegNum<[2]>;
+def R3  : ARMReg< 3, "r3">,  DwarfRegNum<[3]>;
+def R4  : ARMReg< 4, "r4">,  DwarfRegNum<[4]>;
+def R5  : ARMReg< 5, "r5">,  DwarfRegNum<[5]>;
+def R6  : ARMReg< 6, "r6">,  DwarfRegNum<[6]>;
+def R7  : ARMReg< 7, "r7">,  DwarfRegNum<[7]>;
+def R8  : ARMReg< 8, "r8">,  DwarfRegNum<[8]>;
+def R9  : ARMReg< 9, "r9">,  DwarfRegNum<[9]>;
+def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
+def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
+def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
+def SP  : ARMReg<13, "sp">,  DwarfRegNum<[13]>;
+def LR  : ARMReg<14, "lr">,  DwarfRegNum<[14]>;
+def PC  : ARMReg<15, "pc">,  DwarfRegNum<[15]>;
 
 // Float registers
 def S0  : ARMFReg< 0, "s0">;  def S1  : ARMFReg< 1, "s1">;
@@ -78,6 +77,9 @@ def D13 : ARMReg<13, "d13", [S26, S27]>;
 def D14 : ARMReg<14, "d14", [S28, S29]>;
 def D15 : ARMReg<15, "d15", [S30, S31]>;
 
+// Current Program Status Register.
+def CPSR : ARMReg<0, "cpsr">;
+
 // Register classes.
 //
 // pc  == Program Counter
@@ -99,30 +101,34 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
   // generate large stack offset. Make it available once we have register
   // scavenging. Similarly r3 is reserved in Thumb mode for now.
   let MethodBodies = [{
-    // FP is R11, R9 is available, R12 is available.
+    // FP is R11, R9 is available.
     static const unsigned ARM_GPR_AO_1[] = {
       ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+      ARM::R12,ARM::LR,
       ARM::R4, ARM::R5, ARM::R6, ARM::R7,
-      ARM::R8, ARM::R9, ARM::R10,ARM::R12,
-      ARM::LR, ARM::R11 };
-    // FP is R11, R9 is not available, R12 is available.
+      ARM::R8, ARM::R9, ARM::R10,
+      ARM::R11 };
+    // FP is R11, R9 is not available.
     static const unsigned ARM_GPR_AO_2[] = {
       ARM::R3, ARM::R2, ARM::R1, ARM::R0,
+      ARM::R12,ARM::LR,
       ARM::R4, ARM::R5, ARM::R6, ARM::R7,
-      ARM::R8, ARM::R10,ARM::R12,
-      ARM::LR, ARM::R11 };
-    // FP is R7, R9 is available, R12 is available.
+      ARM::R8, ARM::R10,
+      ARM::R11 };
+    // FP is R7, R9 is available.
     static const unsigned ARM_GPR_AO_3[] = {
       ARM::R3, ARM::R2, ARM::R1, ARM::R0,
-      ARM::R4, ARM::R5, ARM::R6, ARM::R8,
-      ARM::R9, ARM::R10,ARM::R11,ARM::R12,
-      ARM::LR, ARM::R7 };
-    // FP is R7, R9 is not available, R12 is available.
+      ARM::R12,ARM::LR,
+      ARM::R4, ARM::R5, ARM::R6,
+      ARM::R8, ARM::R9, ARM::R10,ARM::R11,
+      ARM::R7 };
+    // FP is R7, R9 is not available.
     static const unsigned ARM_GPR_AO_4[] = {
       ARM::R3, ARM::R2, ARM::R1, ARM::R0,
-      ARM::R4, ARM::R5, ARM::R6, ARM::R8,
-      ARM::R10,ARM::R11,ARM::R12,
-      ARM::LR, ARM::R7 };
+      ARM::R12,ARM::LR,
+      ARM::R4, ARM::R5, ARM::R6,
+      ARM::R8, ARM::R10,ARM::R11,
+      ARM::R7 };
 
     // FP is R7, only low registers available.
     static const unsigned THUMB_GPR_AO[] = {
@@ -151,7 +157,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
     GPRClass::iterator
     GPRClass::allocation_order_end(const MachineFunction &MF) const {
       const TargetMachine &TM = MF.getTarget();
-      const MRegisterInfo *RI = TM.getRegisterInfo();
+      const TargetRegisterInfo *RI = TM.getRegisterInfo();
       const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
       GPRClass::iterator I;
       if (Subtarget.isThumb())
@@ -184,3 +190,6 @@ def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
 // is double-word alignment though.
 def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8,
   D9, D10, D11, D12, D13, D14, D15]>;
+
+// Condition code registers.
+def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;