X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMRegisterInfo.td;h=61c77e64acf78144e5172a1738a52b06b1d8e71d;hb=e6be34a53ecbe8c2ff9f0793b13d847e94c0de91;hp=ca57598cc9ed96a96bdcf8e65331620075ffad04;hpb=9e071f0ae3eb92c61de4860fdb12d4499b50e392;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index ca57598cc9e..61c77e64acf 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -1,9 +1,8 @@ -//===- ARMRegisterInfo.td - ARM Register defs ----------*- tablegen -*-===// +//===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // -// This file was developed by the "Instituto Nokia de Tecnologia" and -// is distributed under the University of Illinois Open Source +// This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// @@ -13,126 +12,184 @@ //===----------------------------------------------------------------------===// // Registers are identified with 4-bit ID numbers. -class ARMReg : Register { +class ARMReg num, string n, list subregs = []> : Register { + field bits<4> Num; let Namespace = "ARM"; + let SubRegs = subregs; } -// Ri - 32-bit integer registers -class Ri num, string n> : ARMReg { - field bits<4> Num; - let Num = num; -} -// Rf - 32-bit floating-point registers -class Rf num, string n> : ARMReg { +class ARMFReg num, string n> : Register { field bits<5> Num; - let Num = num; -} -// Rd - Slots in the FP register file for 64-bit floating-point values. -class Rd num, string n, list aliases> : ARMReg { - field bits<5> Num; - let Num = num; - let Aliases = aliases; + let Namespace = "ARM"; } // Integer registers -def R0 : Ri< 0, "R0">, DwarfRegNum<0>; -def R1 : Ri< 1, "R1">, DwarfRegNum<1>; -def R2 : Ri< 2, "R2">, DwarfRegNum<2>; -def R3 : Ri< 3, "R3">, DwarfRegNum<3>; -def R4 : Ri< 4, "R4">, DwarfRegNum<4>; -def R5 : Ri< 5, "R5">, DwarfRegNum<5>; -def R6 : Ri< 6, "R6">, DwarfRegNum<6>; -def R7 : Ri< 7, "R7">, DwarfRegNum<7>; -def R8 : Ri< 8, "R8">, DwarfRegNum<8>; -def R9 : Ri< 9, "R9">, DwarfRegNum<9>; -def R10 : Ri<10, "R10">, DwarfRegNum<10>; -def R11 : Ri<11, "R11">, DwarfRegNum<11>; -def R12 : Ri<12, "R12">, DwarfRegNum<12>; -def R13 : Ri<13, "R13">, DwarfRegNum<13>; -def R14 : Ri<14, "R14">, DwarfRegNum<14>; -def R15 : Ri<15, "R15">, DwarfRegNum<15>; +def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; +def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; +def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; +def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; +def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; +def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; +def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; +def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; +def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; +def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; +def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; +def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; +def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; +def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; +def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; +def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; + +// Float registers +def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; +def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; +def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; +def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; +def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; +def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; +def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; +def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; +def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; +def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; +def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; +def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; +def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; +def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; +def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; +def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; -// TODO: update to VFP-v3 -// Floating-point registers -def S0 : Rf< 0, "S0">, DwarfRegNum<64>; -def S1 : Rf< 1, "S1">, DwarfRegNum<65>; -def S2 : Rf< 2, "S2">, DwarfRegNum<66>; -def S3 : Rf< 3, "S3">, DwarfRegNum<67>; -def S4 : Rf< 4, "S4">, DwarfRegNum<68>; -def S5 : Rf< 5, "S5">, DwarfRegNum<69>; -def S6 : Rf< 6, "S6">, DwarfRegNum<70>; -def S7 : Rf< 7, "S7">, DwarfRegNum<71>; -def S8 : Rf< 8, "S8">, DwarfRegNum<72>; -def S9 : Rf< 9, "S9">, DwarfRegNum<73>; -def S10 : Rf<10, "S10">, DwarfRegNum<74>; -def S11 : Rf<11, "S11">, DwarfRegNum<75>; -def S12 : Rf<12, "S12">, DwarfRegNum<76>; -def S13 : Rf<13, "S13">, DwarfRegNum<77>; -def S14 : Rf<14, "S14">, DwarfRegNum<78>; -def S15 : Rf<15, "S15">, DwarfRegNum<79>; -def S16 : Rf<16, "S16">, DwarfRegNum<80>; -def S17 : Rf<17, "S17">, DwarfRegNum<81>; -def S18 : Rf<18, "S18">, DwarfRegNum<82>; -def S19 : Rf<19, "S19">, DwarfRegNum<83>; -def S20 : Rf<20, "S20">, DwarfRegNum<84>; -def S21 : Rf<21, "S21">, DwarfRegNum<85>; -def S22 : Rf<22, "S22">, DwarfRegNum<86>; -def S23 : Rf<23, "S23">, DwarfRegNum<87>; -def S24 : Rf<24, "S24">, DwarfRegNum<88>; -def S25 : Rf<25, "S25">, DwarfRegNum<89>; -def S26 : Rf<26, "S26">, DwarfRegNum<90>; -def S27 : Rf<27, "S27">, DwarfRegNum<91>; -def S28 : Rf<28, "S28">, DwarfRegNum<92>; -def S29 : Rf<29, "S29">, DwarfRegNum<93>; -def S30 : Rf<30, "S30">, DwarfRegNum<94>; -def S31 : Rf<31, "S31">, DwarfRegNum<95>; +// Aliases of the F* registers used to hold 64-bit fp values (doubles) +def D0 : ARMReg< 0, "d0", [S0, S1]>; +def D1 : ARMReg< 1, "d1", [S2, S3]>; +def D2 : ARMReg< 2, "d2", [S4, S5]>; +def D3 : ARMReg< 3, "d3", [S6, S7]>; +def D4 : ARMReg< 4, "d4", [S8, S9]>; +def D5 : ARMReg< 5, "d5", [S10, S11]>; +def D6 : ARMReg< 6, "d6", [S12, S13]>; +def D7 : ARMReg< 7, "d7", [S14, S15]>; +def D8 : ARMReg< 8, "d8", [S16, S17]>; +def D9 : ARMReg< 9, "d9", [S18, S19]>; +def D10 : ARMReg<10, "d10", [S20, S21]>; +def D11 : ARMReg<11, "d11", [S22, S23]>; +def D12 : ARMReg<12, "d12", [S24, S25]>; +def D13 : ARMReg<13, "d13", [S26, S27]>; +def D14 : ARMReg<14, "d14", [S28, S29]>; +def D15 : ARMReg<15, "d15", [S30, S31]>; -// Aliases of the S* registers used to hold 64-bit fp values (doubles) -def D0 : Rd< 0, "D0", [S0, S1]>, DwarfRegNum<64>; -def D1 : Rd< 2, "D1", [S2, S3]>, DwarfRegNum<66>; -def D2 : Rd< 4, "D2", [S4, S5]>, DwarfRegNum<68>; -def D3 : Rd< 6, "D3", [S6, S7]>, DwarfRegNum<70>; -def D4 : Rd< 8, "D4", [S8, S9]>, DwarfRegNum<72>; -def D5 : Rd<10, "D5", [S10, S11]>, DwarfRegNum<74>; -def D6 : Rd<12, "D6", [S12, S13]>, DwarfRegNum<76>; -def D7 : Rd<14, "D7", [S14, S15]>, DwarfRegNum<78>; -def D8 : Rd<16, "D8", [S16, S17]>, DwarfRegNum<80>; -def D9 : Rd<18, "D9", [S18, S19]>, DwarfRegNum<82>; -def D10 : Rd<20, "D10", [S20, S21]>, DwarfRegNum<84>; -def D11 : Rd<22, "D11", [S22, S23]>, DwarfRegNum<86>; -def D12 : Rd<24, "D12", [S24, S25]>, DwarfRegNum<88>; -def D13 : Rd<26, "D13", [S26, S27]>, DwarfRegNum<90>; -def D14 : Rd<28, "D14", [S28, S29]>, DwarfRegNum<92>; -def D15 : Rd<30, "D15", [S30, S31]>, DwarfRegNum<94>; +// Current Program Status Register. +def CPSR : ARMReg<0, "cpsr">; // Register classes. // -// FIXME: the register order should be defined in terms of the preferred -// allocation order... +// pc == Program Counter +// lr == Link Register +// sp == Stack Pointer +// r12 == ip (scratch) +// r7 == Frame Pointer (thumb-style backtraces) +// r11 == Frame Pointer (arm-style backtraces) +// r10 == Stack Limit // -def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, - R7, R8, R9, R10, R11, R12, - R13, R14, R15]> { +def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, + R7, R8, R9, R10, R12, R11, + LR, SP, PC]> { let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; + // FIXME: We are reserving r12 in case the PEI needs to use it to + // generate large stack offset. Make it available once we have register + // scavenging. Similarly r3 is reserved in Thumb mode for now. let MethodBodies = [{ - IntRegsClass::iterator - IntRegsClass::allocation_order_end(const MachineFunction &MF) const { - // r15 == Program Counter - // r14 == Link Register - // r13 == Stack Pointer - // r12 == ip (scratch) - // r11 == Frame Pointer - // r10 == Stack Limit - return end() - 4; + // FP is R11, R9 is available. + static const unsigned ARM_GPR_AO_1[] = { + ARM::R3, ARM::R2, ARM::R1, ARM::R0, + ARM::R12,ARM::LR, + ARM::R4, ARM::R5, ARM::R6, ARM::R7, + ARM::R8, ARM::R9, ARM::R10, + ARM::R11 }; + // FP is R11, R9 is not available. + static const unsigned ARM_GPR_AO_2[] = { + ARM::R3, ARM::R2, ARM::R1, ARM::R0, + ARM::R12,ARM::LR, + ARM::R4, ARM::R5, ARM::R6, ARM::R7, + ARM::R8, ARM::R10, + ARM::R11 }; + // FP is R7, R9 is available. + static const unsigned ARM_GPR_AO_3[] = { + ARM::R3, ARM::R2, ARM::R1, ARM::R0, + ARM::R12,ARM::LR, + ARM::R4, ARM::R5, ARM::R6, + ARM::R8, ARM::R9, ARM::R10,ARM::R11, + ARM::R7 }; + // FP is R7, R9 is not available. + static const unsigned ARM_GPR_AO_4[] = { + ARM::R3, ARM::R2, ARM::R1, ARM::R0, + ARM::R12,ARM::LR, + ARM::R4, ARM::R5, ARM::R6, + ARM::R8, ARM::R10,ARM::R11, + ARM::R7 }; + + // FP is R7, only low registers available. + static const unsigned THUMB_GPR_AO[] = { + ARM::R2, ARM::R1, ARM::R0, + ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; + + GPRClass::iterator + GPRClass::allocation_order_begin(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb()) + return THUMB_GPR_AO; + if (Subtarget.useThumbBacktraces()) { + if (Subtarget.isR9Reserved()) + return ARM_GPR_AO_4; + else + return ARM_GPR_AO_3; + } else { + if (Subtarget.isR9Reserved()) + return ARM_GPR_AO_2; + else + return ARM_GPR_AO_1; + } + } + + GPRClass::iterator + GPRClass::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + GPRClass::iterator I; + if (Subtarget.isThumb()) + I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned)); + else if (Subtarget.useThumbBacktraces()) { + if (Subtarget.isR9Reserved()) { + I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); + } else { + I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); + } + } else { + if (Subtarget.isR9Reserved()) { + I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); + } else { + I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); + } + } + + // Mac OS X requires FP not to be clobbered for backtracing purpose. + return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; } }]; } -def FPRegs : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, +def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31]>; -def DFPRegs : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15]>; +// ARM requires only word alignment for double. It's more performant if it +// is double-word alignment though. +def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, + D9, D10, D11, D12, D13, D14, D15]>; + +// Condition code registers. +def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;