X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMTargetMachine.cpp;h=20e2624c8300e0bdf68330618f69d6db3312184e;hb=875710a2fd6b3c4f814961582594bd5c1cdb493a;hp=92f2f5bf40fc61cadd32d7b6251cf6006670f16f;hpb=439661395fd2a2a832dba01c65bc88718528313c;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 92f2f5bf40f..20e2624c830 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -10,173 +10,237 @@ // //===----------------------------------------------------------------------===// +#include "ARM.h" #include "ARMTargetMachine.h" #include "ARMFrameLowering.h" -#include "ARM.h" -#include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/PassManager.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Transforms/Scalar.h" using namespace llvm; -// This is duplicated code. Refactor this. -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, - MCContext &Ctx, TargetAsmBackend &TAB, - raw_ostream &OS, - MCCodeEmitter *Emitter, - bool RelaxAll, - bool NoExecStack) { - Triple TheTriple(TT); - - if (TheTriple.isOSDarwin()) - return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); - - if (TheTriple.isOSWindows()) { - llvm_unreachable("ARM does not support Windows COFF format"); - return NULL; - } +static cl::opt +DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, + cl::desc("Inhibit optimization of S->D register accesses on A15"), + cl::init(false)); - return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack); -} +static cl::opt +EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, + cl::desc("Run SimplifyCFG after expanding atomic operations" + " to make use of cmpxchg flow-based information"), + cl::init(true)); extern "C" void LLVMInitializeARMTarget() { // Register the target. - RegisterTargetMachine X(TheARMTarget); - RegisterTargetMachine Y(TheThumbTarget); - - // Register the MC Code Emitter - TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); - - // Register the asm backend. - TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend); - TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend); - - // Register the object streamer. - TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer); - TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer); - + RegisterTargetMachine X(TheARMLETarget); + RegisterTargetMachine Y(TheARMBETarget); + RegisterTargetMachine A(TheThumbLETarget); + RegisterTargetMachine B(TheThumbBETarget); } + /// TargetMachine ctor - Create an ARM architecture model. /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), - Subtarget(TT, CPU, FS), - JITInfo(), - InstrItins(Subtarget.getInstrItineraryData()) { - // Default to soft float ABI - if (FloatABIType == FloatABI::Default) - FloatABIType = FloatABI::Soft; + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool isLittle) + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + Subtarget(TT, CPU, FS, *this, isLittle, Options) { + + // Default to triple-appropriate float ABI + if (Options.FloatABIType == FloatABI::Default) + this->Options.FloatABIType = + Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft; +} + +void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) { + // Add first the target-independent BasicTTI pass, then our ARM pass. This + // allows the ARM pass to delegate to the target independent layer when + // appropriate. + PM.add(createBasicTargetTransformInfoPass(this)); + PM.add(createARMTargetTransformInfoPass(this)); } -ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget), - DataLayout(Subtarget.isAPCS_ABI() ? - std::string("e-p:32:32-f64:32:64-i64:32:64-" - "v128:32:128-v64:32:64-n32") : - std::string("e-p:32:32-f64:64:64-i64:64:64-" - "v128:64:128-v64:64:64-n32")), - ELFWriterInfo(*this), - TLInfo(*this), - TSInfo(*this), - FrameLowering(Subtarget) { + +void ARMTargetMachine::anchor() { } + +ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool isLittle) + : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { + initAsmInfo(); if (!Subtarget.hasARMOps()) report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " "support ARM mode execution!"); } +void ARMLETargetMachine::anchor() { } + +ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + +void ARMBETargetMachine::anchor() { } + +ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + +void ThumbTargetMachine::anchor() { } + ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), - InstrInfo(Subtarget.hasThumb2() - ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) - : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), - DataLayout(Subtarget.isAPCS_ABI() ? - std::string("e-p:32:32-f64:32:64-i64:32:64-" - "i16:16:32-i8:8:32-i1:8:32-" - "v128:32:128-v64:32:64-a:0:32-n32") : - std::string("e-p:32:32-f64:64:64-i64:64:64-" - "i16:16:32-i8:8:32-i1:8:32-" - "v128:64:128-v64:64:64-a:0:32-n32")), - ELFWriterInfo(*this), - TLInfo(*this), - TSInfo(*this), - FrameLowering(Subtarget.hasThumb2() - ? new ARMFrameLowering(Subtarget) - : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool isLittle) + : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, + isLittle) { + initAsmInfo(); } -// Pass Pipeline Configuration -bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - if (OptLevel != CodeGenOpt::None) - PM.add(createARMGlobalMergePass(getTargetLowering())); +void ThumbLETargetMachine::anchor() { } - return false; +ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + +void ThumbBETargetMachine::anchor() { } + +ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + +namespace { +/// ARM Code Generator Pass Configuration Options. +class ARMPassConfig : public TargetPassConfig { +public: + ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + ARMBaseTargetMachine &getARMTargetMachine() const { + return getTM(); + } + + const ARMSubtarget &getARMSubtarget() const { + return *getARMTargetMachine().getSubtargetImpl(); + } + + void addIRPasses() override; + bool addPreISel() override; + bool addInstSelector() override; + bool addPreRegAlloc() override; + bool addPreSched2() override; + bool addPreEmitPass() override; +}; +} // namespace + +TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) { + return new ARMPassConfig(this, PM); +} + +void ARMPassConfig::addIRPasses() { + addPass(createAtomicExpandLoadLinkedPass(TM)); + + // Cmpxchg instructions are often used with a subsequent comparison to + // determine whether it succeeded. We can exploit existing control-flow in + // ldrex/strex loops to simplify this, but it needs tidying up. + const ARMSubtarget *Subtarget = &getARMSubtarget(); + if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) + if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) + addPass(createCFGSimplificationPass()); + + TargetPassConfig::addIRPasses(); } -bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - PM.add(createARMISelDag(*this, OptLevel)); +bool ARMPassConfig::addPreISel() { + if (TM->getOptLevel() != CodeGenOpt::None) + addPass(createGlobalMergePass(TM)); + return false; } -bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) - PM.add(createARMLoadStoreOptimizationPass(true)); - if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9()) - PM.add(createMLxExpansionPass()); +bool ARMPassConfig::addInstSelector() { + addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); + const ARMSubtarget *Subtarget = &getARMSubtarget(); + if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() && + TM->Options.EnableFastISel) + addPass(createARMGlobalBaseRegPass()); + return false; +} + +bool ARMPassConfig::addPreRegAlloc() { + if (getOptLevel() != CodeGenOpt::None) + addPass(createARMLoadStoreOptimizationPass(true)); + if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9()) + addPass(createMLxExpansionPass()); + // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be + // enabled when NEON is available. + if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() && + getARMSubtarget().hasNEON() && !DisableA15SDOptimization) { + addPass(createA15SDOptimizerPass()); + } return true; } -bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None) { - if (!Subtarget.isThumb1Only()) - PM.add(createARMLoadStoreOptimizationPass()); - if (Subtarget.hasNEON()) - PM.add(createNEONMoveFixPass()); +bool ARMPassConfig::addPreSched2() { + if (getOptLevel() != CodeGenOpt::None) { + addPass(createARMLoadStoreOptimizationPass()); + printAndVerify("After ARM load / store optimizer"); + + if (getARMSubtarget().hasNEON()) + addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass)); } // Expand some pseudo instructions into multiple instructions to allow // proper scheduling. - PM.add(createARMExpandPseudoPass()); - - if (OptLevel != CodeGenOpt::None) { - if (!Subtarget.isThumb1Only()) - PM.add(createIfConverterPass()); + addPass(createARMExpandPseudoPass()); + + if (getOptLevel() != CodeGenOpt::None) { + if (!getARMSubtarget().isThumb1Only()) { + // in v8, IfConversion depends on Thumb instruction widths + if (getARMSubtarget().restrictIT() && + !getARMSubtarget().prefers32BitThumb()) + addPass(createThumb2SizeReductionPass()); + addPass(&IfConverterID); + } } - if (Subtarget.isThumb2()) - PM.add(createThumb2ITBlockPass()); + if (getARMSubtarget().isThumb2()) + addPass(createThumb2ITBlockPass()); return true; } -bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) - PM.add(createThumb2SizeReductionPass()); +bool ARMPassConfig::addPreEmitPass() { + if (getARMSubtarget().isThumb2()) { + if (!getARMSubtarget().prefers32BitThumb()) + addPass(createThumb2SizeReductionPass()); - PM.add(createARMConstantIslandPass()); - return true; -} + // Constant island pass work on unbundled instructions. + addPass(&UnpackMachineBundlesID); + } -bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - JITCodeEmitter &JCE) { - // Machine code emitter pass for ARM. - PM.add(createARMJITCodeEmitterPass(*this, JCE)); - return false; + addPass(createARMOptimizeBarriersPass()); + addPass(createARMConstantIslandPass()); + + return true; }