X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FDisassembler%2FARMDisassembler.cpp;h=c8d132135181ccaf78a23dc30e6a4e06df3ecd34;hb=0afa0094afdfe589f407feb76948f273b414b278;hp=805cf544734183059dcec50fb9c2239026ef0b10;hpb=3f3570a38be37ca18c545bd1b4c89604ecaf7e31;p=oota-llvm.git diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 805cf544734..c8d13213518 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -9,198 +9,319 @@ #define DEBUG_TYPE "arm-disassembler" -#include "ARMDisassembler.h" #include "ARM.h" #include "ARMRegisterInfo.h" +#include "ARMSubtarget.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" #include "llvm/MC/EDInstInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCContext.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/MC/MCDisassembler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +using namespace llvm; + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { +/// ARMDisassembler - ARM disassembler for all ARM platforms. +class ARMDisassembler : public MCDisassembler { +public: + /// Constructor - Initializes the disassembler. + /// + ARMDisassembler(const MCSubtargetInfo &STI) : + MCDisassembler(STI) { + } + + ~ARMDisassembler() { + } + + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const; + + /// getEDInfo - See MCDisassembler. + EDInstInfo *getEDInfo() const; +private: +}; + +/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. +class ThumbDisassembler : public MCDisassembler { +public: + /// Constructor - Initializes the disassembler. + /// + ThumbDisassembler(const MCSubtargetInfo &STI) : + MCDisassembler(STI) { + } + + ~ThumbDisassembler() { + } + + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const; + + /// getEDInfo - See MCDisassembler. + EDInstInfo *getEDInfo() const; +private: + mutable std::vector ITBlock; + DecodeStatus AddThumbPredicate(MCInst&) const; + void UpdateThumbVFPPredicate(MCInst&) const; +}; +} + +static bool Check(DecodeStatus &Out, DecodeStatus In) { + switch (In) { + case MCDisassembler::Success: + // Out stays the same. + return true; + case MCDisassembler::SoftFail: + Out = In; + return true; + case MCDisassembler::Fail: + Out = In; + return false; + } + return false; +} + + // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, unsigned Insn, uint64_t Adddress, const void *Decoder); -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + + #include "ARMGenDisassemblerTables.inc" #include "ARMGenInstrInfo.inc" #include "ARMGenEDInfo.inc" -using namespace llvm; - -static MCDisassembler *createARMDisassembler(const Target &T) { - return new ARMDisassembler; +static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { + return new ARMDisassembler(STI); } -static MCDisassembler *createThumbDisassembler(const Target &T) { - return new ThumbDisassembler; +static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { + return new ThumbDisassembler(STI); } EDInstInfo *ARMDisassembler::getEDInfo() const { @@ -211,15 +332,21 @@ EDInstInfo *ThumbDisassembler::getEDInfo() const { return instInfoARM; } - -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address,raw_ostream &os) const { +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { uint8_t bytes[4]; + assert(!(STI.getFeatureBits() & ARM::ModeThumb) && + "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); + // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) - return false; + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { + Size = 0; + return MCDisassembler::Fail; + } // Encoded as a small-endian 32-bit word in the stream. uint32_t insn = (bytes[3] << 24) | @@ -228,64 +355,58 @@ bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, (bytes[0] << 0); // Calling the auto-generated decoder function. - bool result = decodeARMInstruction32(MI, insn, Address, this); - if (result) { - Size = 4; - return true; - } - - // Instructions that are shared between ARM and Thumb modes. - // FIXME: This shouldn't really exist. It's an artifact of the - // fact that we fail to encode a few instructions properly for Thumb. - MI.clear(); - result = decodeCommonInstruction32(MI, insn, Address, this); - if (result) { + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return true; + return result; } // VFP and NEON instructions, similarly, are shared between ARM // and Thumb modes. MI.clear(); - result = decodeVFPInstruction32(MI, insn, Address, this); - if (result) { + result = decodeVFPInstruction32(MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return true; + return result; } MI.clear(); - result = decodeNEONDataInstruction32(MI, insn, Address, this); - if (result) { + result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) + return MCDisassembler::Fail; + return result; } MI.clear(); - result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); - if (result) { + result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) + return MCDisassembler::Fail; + return result; } MI.clear(); - result = decodeNEONDupInstruction32(MI, insn, Address, this); - if (result) { + result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) + return MCDisassembler::Fail; + return result; } MI.clear(); - return false; + Size = 0; + return MCDisassembler::Fail; } namespace llvm { @@ -298,30 +419,56 @@ extern MCInstrDesc ARMInsts[]; // that as a post-pass. static void AddThumb1SBit(MCInst &MI, bool InITBlock) { const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; + unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; MCInst::iterator I = MI.begin(); - for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { + for (unsigned i = 0; i < NumOps; ++i, ++I) { + if (I == MI.end()) break; if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { + if (i > 0 && OpInfo[i-1].isPredicate()) continue; MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); return; } } - if (OpInfo[MI.size()].isOptionalDef() && - OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) - MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); + MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); } // Most Thumb instructions don't have explicit predicates in the // encoding, but rather get their predicates from IT context. We need // to fix up the predicate operands using this context information as a // post-pass. -void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { +MCDisassembler::DecodeStatus +ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { + MCDisassembler::DecodeStatus S = Success; + // A few instructions actually have predicates encoded in them. Don't // try to overwrite it if we're seeing one of those. switch (MI.getOpcode()) { case ARM::tBcc: case ARM::t2Bcc: - return; + case ARM::tCBZ: + case ARM::tCBNZ: + case ARM::tCPS: + case ARM::t2CPS3p: + case ARM::t2CPS2p: + case ARM::t2CPS1p: + case ARM::tMOVSr: + // Some instructions (mostly conditional branches) are not + // allowed in IT blocks. + if (!ITBlock.empty()) + S = SoftFail; + else + return Success; + break; + case ARM::tB: + case ARM::t2B: + case ARM::t2TBB: + case ARM::t2TBH: + // Some instructions (mostly unconditional branches) can + // only appears at the end of, or outside of, an IT. + if (ITBlock.size() > 1) + S = SoftFail; + break; default: break; } @@ -331,13 +478,17 @@ void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { unsigned CC; if (!ITBlock.empty()) { CC = ITBlock.back(); + if (CC == 0xF) + CC = ARMCC::AL; ITBlock.pop_back(); } else CC = ARMCC::AL; const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; + unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; MCInst::iterator I = MI.begin(); - for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { + for (unsigned i = 0; i < NumOps; ++i, ++I) { + if (I == MI.end()) break; if (OpInfo[i].isPredicate()) { I = MI.insert(I, MCOperand::CreateImm(CC)); ++I; @@ -345,15 +496,18 @@ void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { MI.insert(I, MCOperand::CreateReg(0)); else MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); - return; + return S; } } - MI.insert(MI.end(), MCOperand::CreateImm(CC)); + I = MI.insert(I, MCOperand::CreateImm(CC)); + ++I; if (CC == ARMCC::AL) - MI.insert(MI.end(), MCOperand::CreateReg(0)); + MI.insert(I, MCOperand::CreateReg(0)); else - MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); + MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); + + return S; } // Thumb VFP instructions are a special case. Because we share their @@ -371,7 +525,8 @@ void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; MCInst::iterator I = MI.begin(); - for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { + unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; + for (unsigned i = 0; i < NumOps; ++i, ++I) { if (OpInfo[i].isPredicate() ) { I->setImm(CC); ++I; @@ -384,127 +539,147 @@ void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { } } - -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address,raw_ostream &os) const { +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { uint8_t bytes[4]; + assert((STI.getFeatureBits() & ARM::ModeThumb) && + "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); + // We want to read exactly 2 bytes of data. - if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) - return false; + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { + Size = 0; + return MCDisassembler::Fail; + } uint16_t insn16 = (bytes[1] << 8) | bytes[0]; - bool result = decodeThumbInstruction16(MI, insn16, Address, this); + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); + if (result != MCDisassembler::Fail) { + Size = 2; + Check(result, AddThumbPredicate(MI)); + return result; + } + + MI.clear(); + result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); if (result) { Size = 2; bool InITBlock = !ITBlock.empty(); - AddThumbPredicate(MI); + Check(result, AddThumbPredicate(MI)); AddThumb1SBit(MI, InITBlock); - return true; + return result; } MI.clear(); - result = decodeThumb2Instruction16(MI, insn16, Address, this); - if (result) { + result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 2; - AddThumbPredicate(MI); + Check(result, AddThumbPredicate(MI)); // If we find an IT instruction, we need to parse its condition // code and mask operands so that we can apply them correctly // to the subsequent instructions. if (MI.getOpcode() == ARM::t2IT) { - unsigned firstcond = MI.getOperand(0).getImm(); - uint32_t mask = MI.getOperand(1).getImm(); - unsigned zeros = CountTrailingZeros_32(mask); - mask >>= zeros+1; + // Nested IT blocks are UNPREDICTABLE. + if (!ITBlock.empty()) + return MCDisassembler::SoftFail; - for (unsigned i = 0; i < 4 - (zeros+1); ++i) { - if (firstcond ^ (mask & 1)) - ITBlock.push_back(firstcond ^ 1); + // (3 - the number of trailing zeros) is the number of then / else. + unsigned firstcond = MI.getOperand(0).getImm(); + unsigned Mask = MI.getOperand(1).getImm(); + unsigned CondBit0 = Mask >> 4 & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + assert(NumTZ <= 3 && "Invalid IT mask!"); + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == CondBit0; + if (T) + ITBlock.insert(ITBlock.begin(), firstcond); else - ITBlock.push_back(firstcond); - mask >>= 1; + ITBlock.insert(ITBlock.begin(), firstcond ^ 1); } + ITBlock.push_back(firstcond); } - return true; + return result; } // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) - return false; + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { + Size = 0; + return MCDisassembler::Fail; + } uint32_t insn32 = (bytes[3] << 8) | (bytes[2] << 0) | (bytes[1] << 24) | (bytes[0] << 16); MI.clear(); - result = decodeThumbInstruction32(MI, insn32, Address, this); - if (result) { + result = decodeThumbInstruction32(MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; bool InITBlock = ITBlock.size(); - AddThumbPredicate(MI); + Check(result, AddThumbPredicate(MI)); AddThumb1SBit(MI, InITBlock); - return true; + return result; } MI.clear(); - result = decodeThumb2Instruction32(MI, insn32, Address, this); - if (result) { + result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - AddThumbPredicate(MI); - return true; + Check(result, AddThumbPredicate(MI)); + return result; } MI.clear(); - result = decodeCommonInstruction32(MI, insn32, Address, this); - if (result) { + result = decodeVFPInstruction32(MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - AddThumbPredicate(MI); - return true; + UpdateThumbVFPPredicate(MI); + return result; } MI.clear(); - result = decodeVFPInstruction32(MI, insn32, Address, this); - if (result) { + result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - UpdateThumbVFPPredicate(MI); - return true; + Check(result, AddThumbPredicate(MI)); + return result; + } + + if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { + MI.clear(); + uint32_t NEONLdStInsn = insn32; + NEONLdStInsn &= 0xF0FFFFFF; + NEONLdStInsn |= 0x04000000; + result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); + if (result != MCDisassembler::Fail) { + Size = 4; + Check(result, AddThumbPredicate(MI)); + return result; + } } - MI.clear(); if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { + MI.clear(); uint32_t NEONDataInsn = insn32; NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 - result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); - if (result) { + result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - AddThumbPredicate(MI); - return true; + Check(result, AddThumbPredicate(MI)); + return result; } } - MI.clear(); - result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); - if (result) { - Size = 4; - AddThumbPredicate(MI); - return true; - } - - MI.clear(); - result = decodeNEONDupInstruction32(MI, insn32, Address, this); - if (result) { - Size = 4; - AddThumbPredicate(MI); - return true; - } - - return false; + Size = 0; + return MCDisassembler::Fail; } @@ -522,30 +697,31 @@ static const unsigned GPRDecoderTable[] = { ARM::R12, ARM::SP, ARM::LR, ARM::PC }; -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) - return false; + return MCDisassembler::Fail; unsigned Register = GPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return MCDisassembler::Success; } -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { - if (RegNo == 15) return false; +static DecodeStatus +DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { + if (RegNo == 15) return MCDisassembler::Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) - return false; + return MCDisassembler::Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register = 0; switch (RegNo) { @@ -568,20 +744,20 @@ static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, Register = ARM::R12; break; default: - return false; + return MCDisassembler::Fail; } Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return MCDisassembler::Success; } -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo == 13 || RegNo == 15) return false; + if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static const unsigned SPRDecoderTable[] = { +static const unsigned SPRDecoderTable[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, @@ -592,17 +768,17 @@ static const unsigned SPRDecoderTable[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31 }; -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return MCDisassembler::Fail; unsigned Register = SPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return MCDisassembler::Success; } -static const unsigned DPRDecoderTable[] = { +static const unsigned DPRDecoderTable[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, @@ -613,31 +789,32 @@ static const unsigned DPRDecoderTable[] = { ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return MCDisassembler::Fail; unsigned Register = DPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return MCDisassembler::Success; } -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) - return false; + return MCDisassembler::Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { if (RegNo > 15) - return false; + return MCDisassembler::Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } -static const unsigned QPRDecoderTable[] = { +static const unsigned QPRDecoderTable[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, @@ -645,65 +822,60 @@ static const unsigned QPRDecoderTable[] = { }; -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return MCDisassembler::Fail; RegNo >>= 1; unsigned Register = QPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return MCDisassembler::Success; } -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - if (Val == 0xF) return false; + if (Val == 0xF) return MCDisassembler::Fail; // AL predicate is not allowed on Thumb1 branches. if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) - return false; + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Val)); if (Val == ARMCC::AL) { Inst.addOperand(MCOperand::CreateReg(0)); } else Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); - return true; + return MCDisassembler::Success; } -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val) Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); else Inst.addOperand(MCOperand::CreateReg(0)); - return true; + return MCDisassembler::Success; } -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { uint32_t imm = Val & 0xFF; uint32_t rot = (Val & 0xF00) >> 7; uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); Inst.addOperand(MCOperand::CreateImm(rot_imm)); - return true; -} - -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - Val <<= 2; - Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); - return true; + return MCDisassembler::Success; } -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); unsigned imm = fieldFromInstruction32(Val, 7, 5); // Register-immediate - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { @@ -727,19 +899,22 @@ static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, unsigned Op = Shift | (imm << 3); Inst.addOperand(MCOperand::CreateImm(Op)); - return true; + return S; } -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); unsigned Rs = fieldFromInstruction32(Val, 8, 4); // Register-register - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) + return MCDisassembler::Fail; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { @@ -759,65 +934,103 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, Inst.addOperand(MCOperand::CreateImm(Shift)); - return true; + return S; } -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + bool writebackLoad = false; + unsigned writebackReg = 0; + switch (Inst.getOpcode()) { + default: + break; + case ARM::LDMIA_UPD: + case ARM::LDMDB_UPD: + case ARM::LDMIB_UPD: + case ARM::LDMDA_UPD: + case ARM::t2LDMIA_UPD: + case ARM::t2LDMDB_UPD: + writebackLoad = true; + writebackReg = Inst.getOperand(0).getReg(); + break; + } + // Empty register lists are not allowed. - if (CountPopulation_32(Val) == 0) return false; + if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; for (unsigned i = 0; i < 16; ++i) { if (Val & (1 << i)) { - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) + return MCDisassembler::Fail; + // Writeback not allowed if Rn is in the target list. + if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) + Check(S, MCDisassembler::SoftFail); } } - return true; + return S; } -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Vd = fieldFromInstruction32(Val, 8, 4); unsigned regs = Val & 0xFF; - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; + if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler::Fail; for (unsigned i = 0; i < (regs - 1); ++i) { - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; + if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Vd = fieldFromInstruction32(Val, 8, 4); unsigned regs = (Val & 0xFF) / 2; - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler::Fail; for (unsigned i = 0; i < (regs - 1); ++i) { - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { // This operand encodes a mask of contiguous zeros between a specified MSB // and LSB. To decode it, we create the mask of all bits MSB-and-lower, // the mask of all bits LSB-and-lower, and then xor them to create - // the mask of that's all ones on [msb, lsb]. Finally we not it to + // the mask of that's all ones on [msb, lsb]. Finally we not it to // create the final mask. unsigned msb = fieldFromInstruction32(Val, 5, 5); unsigned lsb = fieldFromInstruction32(Val, 0, 5); - uint32_t msb_mask = (1 << (msb+1)) - 1; - uint32_t lsb_mask = (1 << lsb) - 1; + + DecodeStatus S = MCDisassembler::Success; + if (lsb > msb) Check(S, MCDisassembler::SoftFail); + + uint32_t msb_mask = 0xFFFFFFFF; + if (msb != 31) msb_mask = (1U << (msb+1)) - 1; + uint32_t lsb_mask = (1U << lsb) - 1; + Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); - return true; + return S; } -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned CRd = fieldFromInstruction32(Insn, 12, 4); unsigned coproc = fieldFromInstruction32(Insn, 8, 4); @@ -842,8 +1055,24 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_PRE: case ARM::STCL_POST: case ARM::STCL_OPTION: + case ARM::t2LDC_OFFSET: + case ARM::t2LDC_PRE: + case ARM::t2LDC_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OFFSET: + case ARM::t2LDCL_PRE: + case ARM::t2LDCL_POST: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OFFSET: + case ARM::t2STC_PRE: + case ARM::t2STC_POST: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OFFSET: + case ARM::t2STCL_PRE: + case ARM::t2STCL_POST: + case ARM::t2STCL_OPTION: if (coproc == 0xA || coproc == 0xB) - return false; + return MCDisassembler::Fail; break; default: break; @@ -851,7 +1080,8 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.addOperand(MCOperand::CreateImm(coproc)); Inst.addOperand(MCOperand::CreateImm(CRd)); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; switch (Inst.getOpcode()) { case ARM::LDC_OPTION: case ARM::LDCL_OPTION: @@ -863,6 +1093,14 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STC2L_OPTION: case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::LDC2L_POST: + case ARM::STC2L_POST: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: break; default: Inst.addOperand(MCOperand::CreateReg(0)); @@ -882,6 +1120,10 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::t2LDCL_POST: + case ARM::t2STCL_POST: + case ARM::LDC2L_POST: + case ARM::STC2L_POST: imm |= U << 8; case ARM::LDC_OPTION: case ARM::LDCL_OPTION: @@ -891,6 +1133,10 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_OPTION: case ARM::STC2_OPTION: case ARM::STC2L_OPTION: + case ARM::t2LDC_OPTION: + case ARM::t2LDCL_OPTION: + case ARM::t2STC_OPTION: + case ARM::t2STCL_OPTION: Inst.addOperand(MCOperand::CreateImm(imm)); break; default: @@ -920,17 +1166,21 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_PRE: case ARM::STCL_POST: case ARM::STCL_OPTION: - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } - return true; + return S; } -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rm = fieldFromInstruction32(Insn, 0, 4); @@ -950,13 +1200,15 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STRT_POST_IMM: case ARM::STRBT_POST_REG: case ARM::STRBT_POST_IMM: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; // On loads, the writeback operand comes after Rt. switch (Inst.getOpcode()) { @@ -964,19 +1216,19 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDR_POST_REG: case ARM::LDRB_POST_IMM: case ARM::LDRB_POST_REG: - case ARM::LDR_PRE: case ARM::LDRBT_POST_REG: case ARM::LDRBT_POST_IMM: case ARM::LDRT_POST_REG: case ARM::LDRT_POST_IMM: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; ARM_AM::AddrOpc Op = ARM_AM::add; if (!fieldFromInstruction32(Insn, 23, 1)) @@ -989,10 +1241,12 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, else if (!P && writeback) idx_mode = ARMII::IndexModePost; - if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler::SoftFail; // UNPREDICTABLE if (reg) { - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; ARM_AM::ShiftOpc Opc = ARM_AM::lsl; switch( fieldFromInstruction32(Insn, 5, 2)) { case 0: @@ -1008,7 +1262,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, Opc = ARM_AM::ror; break; default: - return false; + return MCDisassembler::Fail; } unsigned amt = fieldFromInstruction32(Insn, 7, 5); unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); @@ -1020,13 +1274,16 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.addOperand(MCOperand::CreateImm(tmp)); } - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 13, 4); unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); @@ -1049,8 +1306,10 @@ static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, break; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; unsigned shift; if (U) shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); @@ -1058,11 +1317,14 @@ static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); Inst.addOperand(MCOperand::CreateImm(shift)); - return true; + return S; } -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rm = fieldFromInstruction32(Insn, 0, 4); @@ -1074,6 +1336,21 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, unsigned P = fieldFromInstruction32(Insn, 24, 1); bool writeback = (W == 1) | (P == 0); + + // For {LD,ST}RD, Rt must be even, else undefined. + switch (Inst.getOpcode()) { + case ARM::STRD: + case ARM::STRD_PRE: + case ARM::STRD_POST: + case ARM::LDRD: + case ARM::LDRD_PRE: + case ARM::LDRD_POST: + if (Rt & 0x1) return MCDisassembler::Fail; + break; + default: + break; + } + if (writeback) { // Writeback if (P) U |= ARMII::IndexModePre << 9; @@ -1085,16 +1362,19 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + case ARM::STRH: + case ARM::STRH_PRE: + case ARM::STRH_POST: + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } } - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; switch (Inst.getOpcode()) { case ARM::STRD: case ARM::STRD_PRE: @@ -1102,8 +1382,8 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; @@ -1115,35 +1395,47 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: + case ARM::LDRH: + case ARM::LDRH_PRE: + case ARM::LDRH_POST: + case ARM::LDRSH: + case ARM::LDRSH_PRE: + case ARM::LDRSH_POST: + case ARM::LDRSB: + case ARM::LDRSB_PRE: + case ARM::LDRSB_POST: case ARM::LDRHTr: case ARM::LDRSBTr: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; if (type) { Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); } else { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(U)); } - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned mode = fieldFromInstruction32(Insn, 23, 2); @@ -1163,89 +1455,182 @@ static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, } Inst.addOperand(MCOperand::CreateImm(mode)); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned reglist = fieldFromInstruction32(Insn, 0, 16); if (pred == 0xF) { switch (Inst.getOpcode()) { - case ARM::STMDA: + case ARM::LDMDA: Inst.setOpcode(ARM::RFEDA); break; - case ARM::STMDA_UPD: + case ARM::LDMDA_UPD: Inst.setOpcode(ARM::RFEDA_UPD); break; - case ARM::STMDB: + case ARM::LDMDB: Inst.setOpcode(ARM::RFEDB); break; - case ARM::STMDB_UPD: + case ARM::LDMDB_UPD: Inst.setOpcode(ARM::RFEDB_UPD); break; - case ARM::STMIA: + case ARM::LDMIA: Inst.setOpcode(ARM::RFEIA); break; - case ARM::STMIA_UPD: + case ARM::LDMIA_UPD: Inst.setOpcode(ARM::RFEIA_UPD); break; - case ARM::STMIB: + case ARM::LDMIB: Inst.setOpcode(ARM::RFEIB); break; - case ARM::STMIB_UPD: + case ARM::LDMIB_UPD: Inst.setOpcode(ARM::RFEIB_UPD); break; + case ARM::STMDA: + Inst.setOpcode(ARM::SRSDA); + break; + case ARM::STMDA_UPD: + Inst.setOpcode(ARM::SRSDA_UPD); + break; + case ARM::STMDB: + Inst.setOpcode(ARM::SRSDB); + break; + case ARM::STMDB_UPD: + Inst.setOpcode(ARM::SRSDB_UPD); + break; + case ARM::STMIA: + Inst.setOpcode(ARM::SRSIA); + break; + case ARM::STMIA_UPD: + Inst.setOpcode(ARM::SRSIA_UPD); + break; + case ARM::STMIB: + Inst.setOpcode(ARM::SRSIB); + break; + case ARM::STMIB_UPD: + Inst.setOpcode(ARM::SRSIB_UPD); + break; + default: + if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; + } + + // For stores (which become SRS's, the only operand is the mode. + if (fieldFromInstruction32(Insn, 20, 1) == 0) { + Inst.addOperand( + MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); + return S; } + return DecodeRFEInstruction(Inst, Insn, Address, Decoder); } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied - !DecodePredicateOperand(Inst, pred, Address, Decoder) || - !DecodeRegListOperand(Inst, reglist, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; // Tied + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction32(Insn, 18, 2); unsigned M = fieldFromInstruction32(Insn, 17, 1); unsigned iflags = fieldFromInstruction32(Insn, 6, 3); unsigned mode = fieldFromInstruction32(Insn, 0, 5); + DecodeStatus S = MCDisassembler::Success; + // imod == '01' --> UNPREDICTABLE - if (imod == 1) return false; + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) return MCDisassembler::Fail; - if (M && mode && imod && iflags) { + if (imod && M) { Inst.setOpcode(ARM::CPS3p); Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(iflags)); Inst.addOperand(MCOperand::CreateImm(mode)); - return true; - } else if (!mode && !M) { + } else if (imod && !M) { Inst.setOpcode(ARM::CPS2p); Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(iflags)); - return true; - } else if (!imod && !iflags && M) { + if (mode) S = MCDisassembler::SoftFail; + } else if (!imod && M) { + Inst.setOpcode(ARM::CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + if (iflags) S = MCDisassembler::SoftFail; + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE Inst.setOpcode(ARM::CPS1p); Inst.addOperand(MCOperand::CreateImm(mode)); - return true; + S = MCDisassembler::SoftFail; } - return false; + return S; +} + +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + unsigned imod = fieldFromInstruction32(Insn, 9, 2); + unsigned M = fieldFromInstruction32(Insn, 8, 1); + unsigned iflags = fieldFromInstruction32(Insn, 5, 3); + unsigned mode = fieldFromInstruction32(Insn, 0, 5); + + DecodeStatus S = MCDisassembler::Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) return MCDisassembler::Fail; + + if (imod && M) { + Inst.setOpcode(ARM::t2CPS3p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + Inst.addOperand(MCOperand::CreateImm(mode)); + } else if (imod && !M) { + Inst.setOpcode(ARM::t2CPS2p); + Inst.addOperand(MCOperand::CreateImm(imod)); + Inst.addOperand(MCOperand::CreateImm(iflags)); + if (mode) S = MCDisassembler::SoftFail; + } else if (!imod && M) { + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + if (iflags) S = MCDisassembler::SoftFail; + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + Inst.setOpcode(ARM::t2CPS1p); + Inst.addOperand(MCOperand::CreateImm(mode)); + S = MCDisassembler::SoftFail; + } + + return S; } -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, + +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 16, 4); unsigned Rn = fieldFromInstruction32(Insn, 0, 4); unsigned Rm = fieldFromInstruction32(Insn, 8, 4); @@ -1255,57 +1640,68 @@ static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) + return MCDisassembler::Fail; - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned add = fieldFromInstruction32(Val, 12, 1); unsigned imm = fieldFromInstruction32(Val, 0, 12); unsigned Rn = fieldFromInstruction32(Val, 13, 4); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; if (!add) imm *= -1; if (imm == 0 && !add) imm = INT32_MIN; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 9, 4); unsigned U = fieldFromInstruction32(Val, 8, 1); unsigned imm = fieldFromInstruction32(Val, 0, 8); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; if (U) Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); else Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); - return true; + return S; } -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); } -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; @@ -1313,39 +1709,44 @@ static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.setOpcode(ARM::BLXi); imm |= fieldFromInstruction32(Insn, 24, 1) << 1; Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); - return true; + return S; } Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(64 - Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned align = fieldFromInstruction32(Val, 4, 2); - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; if (!align) Inst.addOperand(MCOperand::CreateImm(0)); else Inst.addOperand(MCOperand::CreateImm(4 << align)); - return true; + return S; } -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned wb = fieldFromInstruction32(Insn, 16, 4); @@ -1354,7 +1755,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned Rm = fieldFromInstruction32(Insn, 0, 4); // First output register - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; // Second output register switch (Inst.getOpcode()) { @@ -1406,7 +1808,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VLD2b8: case ARM::VLD2b16: @@ -1426,7 +1829,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + return MCDisassembler::Fail; default: break; } @@ -1467,7 +1871,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VLD3q8: case ARM::VLD3q16: @@ -1481,7 +1886,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; @@ -1509,7 +1915,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VLD4q8: case ARM::VLD4q16: @@ -1517,7 +1924,8 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; @@ -1562,28 +1970,32 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } // AddrMode6 Base (register+alignment) - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; // AddrMode6 Offset (register) if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned wb = fieldFromInstruction32(Insn, 16, 4); @@ -1630,25 +2042,28 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } // AddrMode6 Base (register+alignment) - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; // AddrMode6 Offset (register) if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } // First input register - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; // Second input register switch (Inst.getOpcode()) { @@ -1700,7 +2115,8 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VST2b8: case ARM::VST2b16: @@ -1720,7 +2136,8 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; @@ -1762,7 +2179,8 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VST3q8: case ARM::VST3q16: @@ -1776,7 +2194,8 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; @@ -1804,7 +2223,8 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VST4q8: case ARM::VST4q16: @@ -1812,17 +2232,20 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } - return true; + return S; } -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -1833,28 +2256,35 @@ static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, align *= (1 << size); - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; if (regs == 2) { - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) + return MCDisassembler::Fail; } - if (Rm == 0xD) { - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (Rm != 0xF) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(align)); if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -1864,54 +2294,68 @@ static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; align *= 2*size; - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; - if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; - if (Rm == 0xD) { - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (Rm != 0xF) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(align)); if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rm = fieldFromInstruction32(Insn, 0, 4); unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) - return false; - if (Rm == 0xD) { - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (Rm != 0xF) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(0)); if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -1933,29 +2377,38 @@ static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, } } - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || - !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) - return false; - if (Rm == 0xD) { - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) + return MCDisassembler::Fail; + if (Rm != 0xF) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(align)); if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned imm = fieldFromInstruction32(Insn, 0, 4); @@ -1966,9 +2419,11 @@ static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned Q = fieldFromInstruction32(Insn, 6, 1); if (Q) { - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; } else { - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; } Inst.addOperand(MCOperand::CreateImm(imm)); @@ -1978,62 +2433,70 @@ static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VORRiv2i32: case ARM::VBICiv4i16: case ARM::VBICiv2i32: - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; break; case ARM::VORRiv8i16: case ARM::VORRiv4i32: case ARM::VBICiv8i16: case ARM::VBICiv4i32: - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; break; default: break; } - return true; + return S; } -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rm = fieldFromInstruction32(Insn, 0, 4); Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; unsigned size = fieldFromInstruction32(Insn, 18, 2); - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(8 << size)); - return true; + return S; } -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(8 - Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(16 - Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(32 - Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(64 - Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -2043,21 +2506,25 @@ static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned op = fieldFromInstruction32(Insn, 6, 1); unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; if (op) { - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; // Writeback } for (unsigned i = 0; i < length; ++i) { - if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) + return MCDisassembler::Fail; } - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { // The immediate needs to be a fully instantiated float. However, the // auto-generated decoder is only able to fill in some of the bits @@ -2079,102 +2546,126 @@ static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, fp_conv.integer |= (~b & 0x1) << 30; Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned dst = fieldFromInstruction16(Insn, 8, 3); unsigned imm = fieldFromInstruction16(Insn, 0, 8); - if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; + if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) + return MCDisassembler::Fail; - if (Inst.getOpcode() == ARM::tADR) - Inst.addOperand(MCOperand::CreateReg(ARM::PC)); - else if (Inst.getOpcode() == ARM::tADDrSPi) - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - else - return false; + switch(Inst.getOpcode()) { + default: + return MCDisassembler::Fail; + case ARM::tADR: + break; // tADR does not explicitly represent the PC as an operand. + case ARM::tADDrSPi: + Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + break; + } Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); - return true; + return MCDisassembler::Success; } -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 0, 3); unsigned Rm = fieldFromInstruction32(Val, 3, 3); - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 0, 3); unsigned imm = fieldFromInstruction32(Val, 3, 5); - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(Val << 2)); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateImm(Val << 2)); + Inst.addOperand(MCOperand::CreateImm(Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 6, 4); unsigned Rm = fieldFromInstruction32(Val, 2, 4); unsigned imm = fieldFromInstruction32(Val, 0, 2); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - if (Inst.getOpcode() != ARM::t2PLDs) { - unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; + DecodeStatus S = MCDisassembler::Success; + + switch (Inst.getOpcode()) { + case ARM::t2PLDs: + case ARM::t2PLDWs: + case ARM::t2PLIs: + break; + default: { + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + } } unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -2197,57 +2688,81 @@ static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, Inst.addOperand(MCOperand::CreateReg(ARM::PC)); break; default: - return false; + return MCDisassembler::Fail; } int imm = fieldFromInstruction32(Insn, 0, 12); if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; - DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); + if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { int imm = Val & 0xFF; if (!(Val & 0x100)) imm *= -1; Inst.addOperand(MCOperand::CreateImm(imm << 2)); - return true; + return MCDisassembler::Success; } -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 9, 4); unsigned imm = fieldFromInstruction32(Val, 0, 9); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Val, 8, 4); + unsigned imm = fieldFromInstruction32(Val, 0, 8); + + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; - return true; + Inst.addOperand(MCOperand::CreateImm(imm)); + + return S; } -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { int imm = Val & 0xFF; - if (!(Val & 0x100)) imm *= -1; + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x100)) + imm *= -1; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return MCDisassembler::Success; } -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 9, 4); unsigned imm = fieldFromInstruction32(Val, 0, 9); @@ -2258,33 +2773,69 @@ static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, case ARM::t2LDRHT: case ARM::t2LDRSBT: case ARM::t2LDRSHT: + case ARM::t2STRT: + case ARM::t2STRBT: + case ARM::t2STRHT: imm |= 0x100; break; default: break; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeT2Imm8(Inst, imm, Address, Decoder)) - return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } +static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned addr = fieldFromInstruction32(Insn, 0, 8); + addr |= fieldFromInstruction32(Insn, 9, 1) << 8; + addr |= Rn << 9; + unsigned load = fieldFromInstruction32(Insn, 20, 1); + + if (!load) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + + if (load) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + + if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, + return S; +} + +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction32(Val, 13, 4); unsigned imm = fieldFromInstruction32(Val, 0, 12); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imm = fieldFromInstruction16(Insn, 0, 7); @@ -2292,30 +2843,35 @@ static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, Inst.addOperand(MCOperand::CreateReg(ARM::SP)); Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + if (Inst.getOpcode() == ARM::tADDrSP) { unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction16(Insn, 3, 4); Inst.addOperand(MCOperand::CreateReg(ARM::SP)); Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; } - return true; + return S; } -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; unsigned flags = fieldFromInstruction16(Insn, 0, 3); @@ -2323,61 +2879,73 @@ static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(flags)); - return true; + return MCDisassembler::Success; } -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; unsigned Rm = fieldFromInstruction32(Insn, 0, 4); unsigned add = fieldFromInstruction32(Insn, 4, 1); - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(add)); - return true; + return S; } -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); - return true; + return MCDisassembler::Success; } -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0xA || Val == 0xB) - return false; + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - if (Val == 0) - Inst.addOperand(MCOperand::CreateImm(32)); - else - Inst.addOperand(MCOperand::CreateImm(Val)); - return true; +static DecodeStatus +DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + + if (Rn == ARM::SP) S = MCDisassembler::SoftFail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + return S; } -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus +DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned pred = fieldFromInstruction32(Insn, 22, 4); if (pred == 0xE || pred == 0xF) { - unsigned opc = fieldFromInstruction32(Insn, 4, 2); + unsigned opc = fieldFromInstruction32(Insn, 4, 28); switch (opc) { default: - return false; - case 0: + return MCDisassembler::Fail; + case 0xf3bf8f4: Inst.setOpcode(ARM::t2DSB); break; - case 1: + case 0xf3bf8f5: Inst.setOpcode(ARM::t2DMB); break; - case 2: + case 0xf3bf8f6: Inst.setOpcode(ARM::t2ISB); - return true; + break; } unsigned imm = fieldFromInstruction32(Insn, 0, 4); @@ -2390,17 +2958,18 @@ static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; - if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || - !DecodePredicateOperand(Inst, pred, Address, Decoder)) - return false; + if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } // Decode a shifted immediate operand. These basically consist // of an 8-bit value, and a 4-bit directive that specifies either // a splat operation or a rotation. -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned ctrl = fieldFromInstruction32(Val, 10, 2); if (ctrl == 0) { @@ -2428,43 +2997,27 @@ static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, Inst.addOperand(MCOperand::CreateImm(imm)); } - return true; + return MCDisassembler::Success; } -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder){ +static DecodeStatus +DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder){ Inst.addOperand(MCOperand::CreateImm(Val << 1)); - return true; + return MCDisassembler::Success; } -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder){ Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); - return true; + return MCDisassembler::Success; } -static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - bool isImm = fieldFromInstruction32(Val, 9, 1); - bool isAdd = fieldFromInstruction32(Val, 8, 1); - unsigned imm = fieldFromInstruction32(Val, 0, 8); - - if (!isImm) { - if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; - Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); - } else { - Inst.addOperand(MCOperand::CreateReg(0)); - Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); - } - - return true; -} - -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { switch (Val) { default: - return false; + return MCDisassembler::Fail; case 0xF: // SY case 0xE: // ST case 0xB: // ISH @@ -2477,51 +3030,863 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, } Inst.addOperand(MCOperand::CreateImm(Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - if (!Val) return false; + if (!Val) return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(Val)); - return true; + return MCDisassembler::Success; } -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned pred = fieldFromInstruction32(Insn, 28, 4); - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder){ + DecodeStatus S = MCDisassembler::Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); unsigned Rt = fieldFromInstruction32(Insn, 0, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned pred = fieldFromInstruction32(Insn, 28, 4); - if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; - return true; + return S; } +static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned imm = fieldFromInstruction32(Insn, 0, 12); + imm |= fieldFromInstruction32(Insn, 16, 4) << 13; + imm |= fieldFromInstruction32(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned imm = fieldFromInstruction32(Insn, 0, 12); + imm |= fieldFromInstruction32(Insn, 16, 4) << 13; + imm |= fieldFromInstruction32(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; + if (Rm == 0xF) S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + + +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned imm = fieldFromInstruction32(Insn, 0, 12); + imm |= fieldFromInstruction32(Insn, 16, 4) << 13; + imm |= fieldFromInstruction32(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned imm = fieldFromInstruction32(Insn, 0, 12); + imm |= fieldFromInstruction32(Insn, 16, 4) << 13; + imm |= fieldFromInstruction32(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 5, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 6, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 4, 2) != 0) + align = 4; + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 5, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 6, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 4, 2) != 0) + align = 4; + } + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + + +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + index = fieldFromInstruction32(Insn, 5, 3); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 5, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + index = fieldFromInstruction32(Insn, 5, 3); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 5, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + + +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 4, 2)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 4, 1)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 4, 2)) + return MCDisassembler::Fail; // UNDEFINED + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + + +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 4, 2)) + align = 4 << fieldFromInstruction32(Insn, 4, 2); + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + return MCDisassembler::Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction32(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler::Fail; + case 0: + if (fieldFromInstruction32(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction32(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction32(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction32(Insn, 6, 2); + if (fieldFromInstruction32(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction32(Insn, 4, 2)) + align = 4 << fieldFromInstruction32(Insn, 4, 2); + index = fieldFromInstruction32(Insn, 7, 1); + if (fieldFromInstruction32(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(align)); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + } else + Inst.addOperand(MCOperand::CreateReg(0)); + } + + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateImm(index)); + + return S; +} + +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); + unsigned Rm = fieldFromInstruction32(Insn, 0, 4); + unsigned pred = fieldFromInstruction32(Insn, 28, 4); + Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler::SoftFail; + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned pred = fieldFromInstruction16(Insn, 4, 4); + // The InstPrinter needs to have the low bit of the predicate in + // the mask operand to be able to print it properly. + unsigned mask = fieldFromInstruction16(Insn, 0, 5); + + if (pred == 0xF) { + pred = 0xE; + S = MCDisassembler::SoftFail; + } + + if ((mask & 0xF) == 0) { + // Preserve the high bit of the mask, which is the low bit of + // the predicate. + mask &= 0x10; + mask |= 0x8; + S = MCDisassembler::SoftFail; + } + + Inst.addOperand(MCOperand::CreateImm(pred)); + Inst.addOperand(MCOperand::CreateImm(mask)); + return S; +} + +static DecodeStatus +DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned addr = fieldFromInstruction32(Insn, 0, 8); + unsigned W = fieldFromInstruction32(Insn, 21, 1); + unsigned U = fieldFromInstruction32(Insn, 23, 1); + unsigned P = fieldFromInstruction32(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(S, MCDisassembler::SoftFail); + if (Rt == Rt2) + Check(S, MCDisassembler::SoftFail); + + // Rt + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + // Rt2 + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler::Fail; + // Writeback operand + if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + // addr + if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus +DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + unsigned addr = fieldFromInstruction32(Insn, 0, 8); + unsigned W = fieldFromInstruction32(Insn, 21, 1); + unsigned U = fieldFromInstruction32(Insn, 23, 1); + unsigned P = fieldFromInstruction32(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(S, MCDisassembler::SoftFail); + + // Writeback operand + if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + // Rt + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + // Rt2 + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler::Fail; + // addr + if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) { + unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); + if (sign1 != sign2) return MCDisassembler::Fail; + + unsigned Val = fieldFromInstruction32(Insn, 0, 8); + Val |= fieldFromInstruction32(Insn, 12, 3) << 8; + Val |= fieldFromInstruction32(Insn, 26, 1) << 11; + Val |= sign1 << 12; + Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, + uint64_t Address, + const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + // Shift of "asr #32" is not allowed in Thumb2 mode. + if (Val == 0x20) S = MCDisassembler::SoftFail; + Inst.addOperand(MCOperand::CreateImm(Val)); + return S; +}