X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlpha.td;h=6efdf554e1760f63ab480037c6ce5893b2350771;hb=1924aabf996be9335fab34e7ee4fa2aa5911389c;hp=1c01663de02fb3c03b8601c2e118e6b5356f91d8;hpb=3f5aa1cd8c8aed26b7feaac6ce7c12e891daa1a2;p=oota-llvm.git

diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index 1c01663de02..6efdf554e17 100644
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -12,16 +12,35 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
+//===----------------------------------------------------------------------===//
+// Subtarget Features
+//===----------------------------------------------------------------------===//
+
+def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
+                                  "Enable CIX extentions">;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AlphaRegisterInfo.td"
 
+//===----------------------------------------------------------------------===//
+// Calling Convention Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Schedule Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaSchedule.td"
+
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
@@ -29,28 +48,25 @@ include "AlphaRegisterInfo.td"
 include "AlphaInstrInfo.td"
 
 def AlphaInstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our target-specific information field.
  // let TSFlagsFields = [];
  // let TSFlagsShifts = [];
 }
 
-def Alpha : Target {
-  // Pointers on Alpha are 64-bits in size.
-  let PointerType = i64;
-
-  let CalleeSavedRegisters = 
-	//saved regs
-	[R9, R10, R11, R12, R13, R14, 
-	//Frame pointer
-//	R15, 
-	//return address
-//	R26, 
-	//Stack Pointer
-//	R30,
-         F2, F3, F4, F5, F6, F7, F8, F9];
+//===----------------------------------------------------------------------===//
+// Alpha Processor Definitions
+//===----------------------------------------------------------------------===//
+
+def : Processor<"generic", Alpha21264Itineraries, []>;
+def : Processor<"ev6"    , Alpha21264Itineraries, []>;
+def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureCIX]>;
 
+//===----------------------------------------------------------------------===//
+// The Alpha Target
+//===----------------------------------------------------------------------===//
+
+
+def Alpha : Target {
   // Pull in Instruction Info:
   let InstructionSet = AlphaInstrInfo;
 }