X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaCodeEmitter.cpp;h=ea828c804c796b743bac127005debbc785e21ee5;hb=6726b6d75a8b679068a58cb954ba97cf9d1690ba;hp=56f515e5492c68b0a14cc37a25f4d5ee11ff27f0;hpb=804e0fea4033e3b91dbc8198cef30de30f141bb5;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 56f515e5492..ea828c804c7 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -31,7 +31,7 @@ using namespace llvm; namespace { - + class AlphaCodeEmitter { MachineCodeEmitter &MCE; public: @@ -50,8 +50,7 @@ namespace { }; template - class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, - public AlphaCodeEmitter + class Emitter : public MachineFunctionPass, public AlphaCodeEmitter { const AlphaInstrInfo *II; TargetMachine &TM; @@ -60,7 +59,7 @@ namespace { public: static char ID; explicit Emitter(TargetMachine &tm, CodeEmitter &mce) - : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), + : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), II(0), TM(tm), MCE(mce) {} Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii) : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), @@ -72,8 +71,6 @@ namespace { return "Alpha Machine Code Emitter"; } - void emitInstruction(const MachineInstr &MI); - private: void emitBasicBlock(MachineBasicBlock &MBB); }; @@ -118,6 +115,7 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { const MachineInstr &MI = *I; + MCE.processDebugLoc(MI.getDebugLoc(), true); switch(MI.getOpcode()) { default: MCE.emitWordLE(getBinaryCodeForInstr(*I)); @@ -126,8 +124,10 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { case Alpha::PCLABEL: case Alpha::MEMLABEL: case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::KILL: break; //skip these } + MCE.processDebugLoc(MI.getDebugLoc(), false); } } @@ -166,12 +166,12 @@ static unsigned getAlphaRegNumber(unsigned Reg) { case Alpha::R30 : case Alpha::F30 : return 30; case Alpha::R31 : case Alpha::F31 : return 31; default: - LLVM_UNREACHABLE("Unhandled reg"); + llvm_unreachable("Unhandled reg"); } } unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { + const MachineOperand &MO) { unsigned rv = 0; // Return value; defaults to 0 for unhandled cases // or things that get fixed up later by the JIT. @@ -181,7 +181,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, } else if (MO.isImm()) { rv = MO.getImm(); } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) { - DOUT << MO << " is a relocated op for " << MI << "\n"; + DEBUG(errs() << MO << " is a relocated op for " << MI << "\n"); unsigned Reloc = 0; int Offset = 0; bool useGOT = false; @@ -217,7 +217,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, Offset = MI.getOperand(3).getImm(); break; default: - LLVM_UNREACHABLE("unknown relocatable instruction"); + llvm_unreachable("unknown relocatable instruction"); } if (MO.isGlobal()) MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), @@ -235,15 +235,13 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Alpha::reloc_bsr, MO.getMBB())); } else { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "ERROR: Unknown type of MachineOperand: " << MO; - llvm_report_error(Msg.str()); +#ifndef NDEBUG + errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; +#endif + llvm_unreachable(0); } return rv; } #include "AlphaGenCodeEmitter.inc" - -