X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaISelDAGToDAG.cpp;h=eaefef9c8b470241a3e46faae4e57ce2939cf535;hb=518bb53485df640d7b7e3f6b0544099020c42aa7;hp=c7eefccd4095119606733f1a4c69b6d1272bd839;hpb=83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb;p=oota-llvm.git

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index c7eefccd409..eaefef9c8b4 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -26,12 +26,13 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/LLVMContext.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
 #include <algorithm>
-#include <queue>
-#include <set>
 using namespace llvm;
 
 namespace {
@@ -40,8 +41,6 @@ namespace {
   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
   /// instructions for SelectionDAG operations.
   class AlphaDAGToDAGISel : public SelectionDAGISel {
-    AlphaTargetLowering AlphaLowering;
-
     static const int64_t IMM_LOW  = -32768;
     static const int64_t IMM_HIGH = 32767;
     static const int64_t IMM_MULT = 65536;
@@ -65,7 +64,7 @@ namespace {
     /// that the bits 1-7 of LHS are already zero.  If LHS is non-null, we are
     /// in checking mode.  If LHS is null, we assume that the mask has already
     /// been validated before.
-    uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
+    uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
       uint64_t BitsToCheck = 0;
       unsigned Result = 0;
       for (unsigned i = 0; i != 8; ++i) {
@@ -75,7 +74,7 @@ namespace {
           Result |= 1 << i;
           if (((Constant >> 8*i) & 0xFF) == 0xFF) {
             // If the entire byte is set, zapnot the byte.
-          } else if (LHS.Val == 0) {
+          } else if (LHS.getNode() == 0) {
             // Otherwise, if the mask was previously validated, we know its okay
             // to zapnot this entire byte even though all the bits aren't set.
           } else {
@@ -118,7 +117,7 @@ namespace {
       uint64_t complow = 1 << (63 - at);
       uint64_t comphigh = 1 << (64 - at);
       //cerr << x << ":" << complow << ":" << comphigh << "\n";
-      if (abs(complow - x) <= abs(comphigh - x))
+      if (abs64(complow - x) <= abs64(comphigh - x))
         return complow;
       else
         return comphigh;
@@ -132,38 +131,37 @@ namespace {
         return (x - y) == r;
     }
 
-    static bool isFPZ(SDOperand N) {
+    static bool isFPZ(SDValue N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
       return (CN && (CN->getValueAPF().isZero()));
     }
-    static bool isFPZn(SDOperand N) {
+    static bool isFPZn(SDValue N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
       return (CN && CN->getValueAPF().isNegZero());
     }
-    static bool isFPZp(SDOperand N) {
+    static bool isFPZp(SDValue N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
       return (CN && CN->getValueAPF().isPosZero());
     }
 
   public:
     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
-      : SelectionDAGISel(AlphaLowering), 
-        AlphaLowering(*TM.getTargetLowering())
+      : SelectionDAGISel(TM)
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
     /// i64.
-    inline SDOperand getI64Imm(int64_t Imm) {
+    inline SDValue getI64Imm(int64_t Imm) {
       return CurDAG->getTargetConstant(Imm, MVT::i64);
     }
 
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDOperand Op);
+    SDNode *Select(SDNode *N);
     
-    /// InstructionSelectBasicBlock - This callback is invoked by
+    /// InstructionSelect - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-    virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+    virtual void InstructionSelect();
     
     virtual const char *getPassName() const {
       return "Alpha DAG->DAG Pattern Instruction Selection";
@@ -171,16 +169,14 @@ namespace {
 
     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     /// inline asm expressions.
-    virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+    virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                               char ConstraintCode,
-                                              std::vector<SDOperand> &OutOps,
-                                              SelectionDAG &DAG) {
-      SDOperand Op0;
+                                              std::vector<SDValue> &OutOps) {
+      SDValue Op0;
       switch (ConstraintCode) {
       default: return true;
       case 'm':   // memory
         Op0 = Op;
-        AddToISelQueue(Op0);
         break;
       }
       
@@ -192,9 +188,21 @@ namespace {
 #include "AlphaGenDAGISel.inc"
     
 private:
-    SDOperand getGlobalBaseReg();
-    SDOperand getGlobalRetAddr();
-    void SelectCALL(SDOperand Op);
+    /// getTargetMachine - Return a reference to the TargetMachine, casted
+    /// to the target-specific type.
+    const AlphaTargetMachine &getTargetMachine() {
+      return static_cast<const AlphaTargetMachine &>(TM);
+    }
+
+    /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
+    /// to the target-specific type.
+    const AlphaInstrInfo *getInstrInfo() {
+      return getTargetMachine().getInstrInfo();
+    }
+
+    SDNode *getGlobalBaseReg();
+    SDNode *getGlobalRetAddr();
+    void SelectCALL(SDNode *Op);
 
   };
 }
@@ -202,60 +210,38 @@ private:
 /// getGlobalBaseReg - Output the instructions required to put the
 /// GOT address into a register.
 ///
-SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
-  unsigned GP = 0;
-  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
-        ee = RegInfo->livein_end(); ii != ee; ++ii)
-    if (ii->first == Alpha::R29) {
-      GP = ii->second;
-      break;
-    }
-  assert(GP && "GOT PTR not in liveins");
-  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                GP, MVT::i64);
+SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
+  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
+  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 
-/// getRASaveReg - Grab the return address
+/// getGlobalRetAddr - Grab the return address.
 ///
-SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
-  unsigned RA = 0;
-  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
-        ee = RegInfo->livein_end(); ii != ee; ++ii)
-    if (ii->first == Alpha::R26) {
-      RA = ii->second;
-      break;
-    }
-  assert(RA && "RA PTR not in liveins");
-  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
-                                RA, MVT::i64);
+SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
+  unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
+  return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
 }
 
-/// InstructionSelectBasicBlock - This callback is invoked by
+/// InstructionSelect - This callback is invoked by
 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
-  DEBUG(BB->dump());
-  
+void AlphaDAGToDAGISel::InstructionSelect() {
   // Select target instructions for the DAG.
-  DAG.setRoot(SelectRoot(DAG.getRoot()));
-  DAG.RemoveDeadNodes();
-  
-  // Emit machine code to BB. 
-  ScheduleAndEmitDAG(DAG);
+  SelectRoot(*CurDAG);
+  CurDAG->RemoveDeadNodes();
 }
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
-  SDNode *N = Op.Val;
-  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
-      N->getOpcode() < AlphaISD::FIRST_NUMBER) {
+SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
+  if (N->isMachineOpcode()) {
     return NULL;   // Already selected.
   }
+  DebugLoc dl = N->getDebugLoc();
 
   switch (N->getOpcode()) {
   default: break;
   case AlphaISD::CALL:
-    SelectCALL(Op);
+    SelectCALL(N);
     return NULL;
 
   case ISD::FrameIndex: {
@@ -264,53 +250,43 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                 getI64Imm(0));
   }
-  case ISD::GLOBAL_OFFSET_TABLE: {
-    SDOperand Result = getGlobalBaseReg();
-    ReplaceUses(Op, Result);
-    return NULL;
-  }
-  case AlphaISD::GlobalRetAddr: {
-    SDOperand Result = getGlobalRetAddr();
-    ReplaceUses(Op, Result);
-    return NULL;
-  }
+  case ISD::GLOBAL_OFFSET_TABLE:
+    return getGlobalBaseReg();
+  case AlphaISD::GlobalRetAddr:
+    return getGlobalRetAddr();
   
   case AlphaISD::DivCall: {
-    SDOperand Chain = CurDAG->getEntryNode();
-    SDOperand N0 = Op.getOperand(0);
-    SDOperand N1 = Op.getOperand(1);
-    SDOperand N2 = Op.getOperand(2);
-    AddToISelQueue(N0);
-    AddToISelQueue(N1);
-    AddToISelQueue(N2);
-    Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, 
-                                 SDOperand(0,0));
-    Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, 
+    SDValue Chain = CurDAG->getEntryNode();
+    SDValue N0 = N->getOperand(0);
+    SDValue N1 = N->getOperand(1);
+    SDValue N2 = N->getOperand(2);
+    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1, 
+                                 SDValue(0,0));
+    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2, 
                                  Chain.getValue(1));
-    Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, 
+    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, 
                                  Chain.getValue(1));
     SDNode *CNode =
-      CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, 
-                            Chain, Chain.getValue(1));
-    Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, 
-                                   SDOperand(CNode, 1));
+      CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, 
+                             Chain, Chain.getValue(1));
+    Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, 
+                                   SDValue(CNode, 1));
     return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
   }
 
   case ISD::READCYCLECOUNTER: {
-    SDOperand Chain = N->getOperand(0);
-    AddToISelQueue(Chain); //Select chain
-    return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
-                                 Chain);
+    SDValue Chain = N->getOperand(0);
+    return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
+                                  Chain);
   }
 
   case ISD::Constant: {
-    uint64_t uval = cast<ConstantSDNode>(N)->getValue();
+    uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
     
     if (uval == 0) {
-      SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+      SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
                                                 Alpha::R31, MVT::i64);
-      ReplaceUses(Op, Result);
+      ReplaceUses(SDValue(N, 0), Result);
       return NULL;
     }
 
@@ -324,17 +300,19 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
       // val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
       break; //(zext (LDAH (LDA)))
     //Else use the constant pool
-    ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
-    SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
-    SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
-                                        getGlobalBaseReg());
+    ConstantInt *C = ConstantInt::get(
+                                Type::getInt64Ty(*CurDAG->getContext()), uval);
+    SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+    SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI,
+                                         SDValue(getGlobalBaseReg(), 0));
     return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
-                                CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
+                                CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
   }
-  case ISD::TargetConstantFP: {
+  case ISD::TargetConstantFP:
+  case ISD::ConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     bool isDouble = N->getValueType(0) == MVT::f64;
-    MVT T = isDouble ? MVT::f64 : MVT::f32;
+    EVT T = isDouble ? MVT::f64 : MVT::f32;
     if (CN->getValueAPF().isPosZero()) {
       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
                                   T, CurDAG->getRegister(Alpha::F31, T),
@@ -344,20 +322,20 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
                                   T, CurDAG->getRegister(Alpha::F31, T),
                                   CurDAG->getRegister(Alpha::F31, T));
     } else {
-      abort();
+      llvm_report_error("Unhandled FP constant type");
     }
     break;
   }
 
   case ISD::SETCC:
-    if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
+    if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
 
       unsigned Opc = Alpha::WTF;
       bool rev = false;
       bool inv = false;
       switch(CC) {
-      default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
+      default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
       case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
         Opc = Alpha::CMPTEQ; break;
       case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: 
@@ -375,53 +353,31 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
       case ISD::SETUO:
         Opc = Alpha::CMPTUN; break;
       };
-      SDOperand tmp1 = N->getOperand(rev?1:0);
-      SDOperand tmp2 = N->getOperand(rev?0:1);
-      AddToISelQueue(tmp1);
-      AddToISelQueue(tmp2);
-      SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
+      SDValue tmp1 = N->getOperand(rev?1:0);
+      SDValue tmp2 = N->getOperand(rev?0:1);
+      SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2);
       if (inv) 
-        cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0), 
-                                    CurDAG->getRegister(Alpha::F31, MVT::f64));
+        cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl, 
+                                     MVT::f64, SDValue(cmp, 0), 
+                                     CurDAG->getRegister(Alpha::F31, MVT::f64));
       switch(CC) {
       case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
       case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
        {
-         SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
-                                              tmp1, tmp2);
-         cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, 
-                                     SDOperand(cmp2, 0), SDOperand(cmp, 0));
+         SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64,
+                                               tmp1, tmp2);
+         cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64, 
+                                      SDValue(cmp2, 0), SDValue(cmp, 0));
          break;
        }
       default: break;
       }
 
-      SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
-      return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
-                                   CurDAG->getRegister(Alpha::R31, MVT::i64),
-                                   SDOperand(LD,0));
-    }
-    break;
-
-  case ISD::SELECT:
-    if (N->getValueType(0).isFloatingPoint() &&
-        (N->getOperand(0).getOpcode() != ISD::SETCC ||
-         !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
-      //This should be the condition not covered by the Patterns
-      //FIXME: Don't have SelectCode die, but rather return something testable
-      // so that things like this can be caught in fall though code
-      //move int to fp
-      bool isDouble = N->getValueType(0) == MVT::f64;
-      SDOperand cond = N->getOperand(0);
-      SDOperand TV = N->getOperand(1);
-      SDOperand FV = N->getOperand(2);
-      AddToISelQueue(cond);
-      AddToISelQueue(TV);
-      AddToISelQueue(FV);
-      
-      SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
-      return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
-                                   MVT::f64, FV, TV, SDOperand(LD,0));
+      SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl,
+                                          MVT::i64, SDValue(cmp, 0));
+      return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64, 
+                                    CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                    SDValue(LD,0));
     }
     break;
 
@@ -431,8 +387,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     if (N->getOperand(0).getOpcode() == ISD::SRL &&
         (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
         (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
-      uint64_t sval = SC->getValue();
-      uint64_t mval = MC->getValue();
+      uint64_t sval = SC->getZExtValue();
+      uint64_t mval = MC->getZExtValue();
       // If the result is a zap, let the autogened stuff handle it.
       if (get_zapImm(N->getOperand(0), mval))
         break;
@@ -445,13 +401,12 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
         mask = mask | dontcare;
       
       if (get_zapImm(mask)) {
-        AddToISelQueue(N->getOperand(0).getOperand(0));
-        SDOperand Z = 
-          SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
-                                          N->getOperand(0).getOperand(0),
-                                          getI64Imm(get_zapImm(mask))), 0);
-        return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, 
-                                     getI64Imm(sval));
+        SDValue Z = 
+          SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64,
+                                         N->getOperand(0).getOperand(0),
+                                         getI64Imm(get_zapImm(mask))), 0);
+        return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z, 
+                                      getI64Imm(sval));
       }
     }
     break;
@@ -459,100 +414,34 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
 
   }
 
-  return SelectCode(Op);
+  return SelectCode(N);
 }
 
-void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
   //TODO: add flag stuff to prevent nondeturministic breakage!
 
-  SDNode *N = Op.Val;
-  SDOperand Chain = N->getOperand(0);
-  SDOperand Addr = N->getOperand(1);
-  SDOperand InFlag(0,0);  // Null incoming flag value.
-  AddToISelQueue(Chain);
-
-   std::vector<SDOperand> CallOperands;
-   std::vector<MVT> TypeOperands;
-  
-   //grab the arguments
-   for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
-     TypeOperands.push_back(N->getOperand(i).getValueType());
-     AddToISelQueue(N->getOperand(i));
-     CallOperands.push_back(N->getOperand(i));
-   }
-   int count = N->getNumOperands() - 2;
-
-   static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
-                                       Alpha::R19, Alpha::R20, Alpha::R21};
-   static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
-                                         Alpha::F19, Alpha::F20, Alpha::F21};
-   
-   for (int i = 6; i < count; ++i) {
-     unsigned Opc = Alpha::WTF;
-     if (TypeOperands[i].isInteger()) {
-       Opc = Alpha::STQ;
-     } else if (TypeOperands[i] == MVT::f32) {
-       Opc = Alpha::STS;
-     } else if (TypeOperands[i] == MVT::f64) {
-       Opc = Alpha::STT;
-     } else
-       assert(0 && "Unknown operand"); 
-
-     SDOperand Ops[] = { CallOperands[i],  getI64Imm((i - 6) * 8), 
-                         CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
-                         Chain };
-     Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
-   }
-   for (int i = 0; i < std::min(6, count); ++i) {
-     if (TypeOperands[i].isInteger()) {
-       Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
-       InFlag = Chain.getValue(1);
-     } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
-       Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
-       InFlag = Chain.getValue(1);
-     } else
-       assert(0 && "Unknown operand"); 
-   }
+  SDValue Chain = N->getOperand(0);
+  SDValue Addr = N->getOperand(1);
+  SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
+  DebugLoc dl = N->getDebugLoc();
 
-   // Finally, once everything is in registers to pass to the call, emit the
-   // call itself.
    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
-     SDOperand GOT = getGlobalBaseReg();
-     Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
+     SDValue GOT = SDValue(getGlobalBaseReg(), 0);
+     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
      InFlag = Chain.getValue(1);
-     Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, 
-                                             Addr.getOperand(0), Chain, InFlag), 0);
+     Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other, 
+                                            MVT::Flag, Addr.getOperand(0),
+                                            Chain, InFlag), 0);
    } else {
-     AddToISelQueue(Addr);
-     Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
+     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
      InFlag = Chain.getValue(1);
-     Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, 
-                                             Chain, InFlag), 0);
+     Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other,
+                                            MVT::Flag, Chain, InFlag), 0);
    }
    InFlag = Chain.getValue(1);
 
-   std::vector<SDOperand> CallResults;
-  
-   switch (N->getValueType(0).getSimpleVT()) {
-   default: assert(0 && "Unexpected ret value!");
-     case MVT::Other: break;
-   case MVT::i64:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
-     CallResults.push_back(Chain.getValue(0));
-     break;
-   case MVT::f32:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
-     CallResults.push_back(Chain.getValue(0));
-     break;
-   case MVT::f64:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
-     CallResults.push_back(Chain.getValue(0));
-     break;
-   }
-
-   CallResults.push_back(Chain);
-   for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
-     ReplaceUses(Op.getValue(i), CallResults[i]);
+  ReplaceUses(SDValue(N, 0), Chain);
+  ReplaceUses(SDValue(N, 1), InFlag);
 }