X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaISelLowering.cpp;h=b0d5be3e78e0208fdf8d3bd09073691a3e5e1f16;hb=0876aa5178907747cd2d57bdd264e47a573684be;hp=d6b1bb314e1b50ec57a7b6557d46d39a7ee1b27a;hpb=677c4f2cbc7d77b53715ce26fe30ca82e48e644a;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index d6b1bb314e1..b0d5be3e78e 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -26,12 +26,6 @@ using namespace llvm; -namespace llvm { - cl::opt EnableAlphaLSMark("enable-alpha-lsmark", - cl::desc("Emit symbols to correlate Mem ops to LLVM Values"), - cl::Hidden); -} - /// AddLiveIn - This helper function adds the specified physical register to the /// MachineFunction as a live in value. It also creates a corresponding virtual /// register for it. @@ -54,8 +48,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::EXTLOAD, MVT::i1, Promote); setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); @@ -69,20 +63,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); - if (EnableAlphaLSMark) { - setOperationAction(ISD::LOAD, MVT::i64, Custom); - setOperationAction(ISD::LOAD, MVT::f64, Custom); - setOperationAction(ISD::LOAD, MVT::f32, Custom); - - setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom); - setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom); - setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom); - - setOperationAction(ISD::EXTLOAD, MVT::i8, Custom); - setOperationAction(ISD::EXTLOAD, MVT::i16, Custom); - setOperationAction(ISD::EXTLOAD, MVT::i32, Custom); - } - setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); @@ -117,6 +97,10 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + + // FIXME: Alpha supports fcopysign natively!? + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); setOperationAction(ISD::SETCC, MVT::f32, Promote); @@ -141,9 +125,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::VAEND, MVT::Other, Expand); setOperationAction(ISD::VACOPY, MVT::Other, Custom); setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::i32, Custom); setStackPointerRegisterToSaveRestore(Alpha::R30); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); + setOperationAction(ISD::ConstantFP, MVT::f32, Expand); addLegalFPImmediate(+0.0); //F31 addLegalFPImmediate(-0.0); //-F31 @@ -164,19 +151,8 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { case AlphaISD::GPRelLo: return "Alpha::GPRelLo"; case AlphaISD::RelLit: return "Alpha::RelLit"; case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg"; + case AlphaISD::CALL: return "Alpha::CALL"; case AlphaISD::DivCall: return "Alpha::DivCall"; - case AlphaISD::LDQ_: return "Alpha::LDQ_"; - case AlphaISD::LDT_: return "Alpha::LDT_"; - case AlphaISD::LDS_: return "Alpha::LDS_"; - case AlphaISD::LDL_: return "Alpha::LDL_"; - case AlphaISD::LDWU_: return "Alpha::LDWU_"; - case AlphaISD::LDBU_: return "Alpha::LDBU_"; - case AlphaISD::STQ_: return "Alpha::STQ_"; - case AlphaISD::STT_: return "Alpha::STT_"; - case AlphaISD::STS_: return "Alpha::STS_"; - case AlphaISD::STL_: return "Alpha::STL_"; - case AlphaISD::STW_: return "Alpha::STW_"; - case AlphaISD::STB_: return "Alpha::STB_"; } } @@ -321,8 +297,8 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, if (Args.size() > 6) NumBytes = (Args.size() - 6) * 8; - Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, - DAG.getConstant(NumBytes, getPointerTy())); + Chain = DAG.getCALLSEQ_START(Chain, + DAG.getConstant(NumBytes, getPointerTy())); std::vector args_to_use; for (unsigned i = 0, e = Args.size(); i != e; ++i) { @@ -357,8 +333,11 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, RetVals.push_back(ActualRetTyVT); RetVals.push_back(MVT::Other); - SDOperand TheCall = SDOperand(DAG.getCall(RetVals, - Chain, Callee, args_to_use), 0); + std::vector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); + SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops); Chain = TheCall.getValue(RetTyVT != MVT::isVoid); Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, DAG.getConstant(NumBytes, getPointerTy())); @@ -382,48 +361,6 @@ void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB) BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA); } - - -static void getValueInfo(const Value* v, int& type, int& fun, int& offset) -{ - fun = type = offset = 0; - if (v == NULL) { - type = 0; - } else if (const GlobalValue* GV = dyn_cast(v)) { - type = 1; - const Module* M = GV->getParent(); - for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii) - ++offset; - } else if (const Argument* Arg = dyn_cast(v)) { - type = 2; - const Function* F = Arg->getParent(); - const Module* M = F->getParent(); - for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii) - ++fun; - for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii) - ++offset; - } else if (const Instruction* I = dyn_cast(v)) { - assert(dyn_cast(I->getType())); - type = 3; - const BasicBlock* bb = I->getParent(); - const Function* F = bb->getParent(); - const Module* M = F->getParent(); - for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii) - ++fun; - for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii) - offset += ii->size(); - for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii) - ++offset; - } else if (const Constant* C = dyn_cast(v)) { - //Don't know how to look these up yet - type = 0; - } else { - assert(0 && "Error in value marking"); - } - //type = 4: register spilling - //type = 5: global address loading or constant loading -} - static int getUID() { static int id = 0; @@ -475,8 +412,9 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { } } case ISD::ConstantPool: { - Constant *C = cast(Op)->get(); - SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64); + ConstantPoolSDNode *CP = cast(Op); + Constant *C = CP->get(); + SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); @@ -521,97 +459,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { } break; - case ISD::LOAD: - case ISD::SEXTLOAD: - case ISD::ZEXTLOAD: - case ISD::EXTLOAD: - { - SDOperand Chain = Op.getOperand(0); - SDOperand Address = Op.getOperand(1); - - unsigned Opc; - unsigned opcode = Op.getOpcode(); - - if (opcode == ISD::LOAD) - switch (Op.Val->getValueType(0)) { - default: Op.Val->dump(); assert(0 && "Bad load!"); - case MVT::i64: Opc = AlphaISD::LDQ_; break; - case MVT::f64: Opc = AlphaISD::LDT_; break; - case MVT::f32: Opc = AlphaISD::LDS_; break; - } - else - switch (cast(Op.getOperand(3))->getVT()) { - default: Op.Val->dump(); assert(0 && "Bad sign extend!"); - case MVT::i32: Opc = AlphaISD::LDL_; - assert(opcode != ISD::ZEXTLOAD && "Not sext"); break; - case MVT::i16: Opc = AlphaISD::LDWU_; - assert(opcode != ISD::SEXTLOAD && "Not zext"); break; - case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise - case MVT::i8: Opc = AlphaISD::LDBU_; - assert(opcode != ISD::SEXTLOAD && "Not zext"); break; - } - - int i, j, k; - getValueInfo(dyn_cast(Op.getOperand(2))->getValue(), i, j, k); - - SDOperand Zero = DAG.getConstant(0, MVT::i64); - std::vector VTS; - VTS.push_back(Op.Val->getValueType(0)); - VTS.push_back(MVT::Other); - std::vector ARGS; - ARGS.push_back(Chain); - ARGS.push_back(Zero); - ARGS.push_back(Address); - ARGS.push_back(DAG.getConstant(i, MVT::i64)); - ARGS.push_back(DAG.getConstant(j, MVT::i64)); - ARGS.push_back(DAG.getConstant(k, MVT::i64)); - ARGS.push_back(DAG.getConstant(getUID(), MVT::i64)); - return DAG.getNode(Opc, VTS, ARGS); - } - - case ISD::TRUNCSTORE: - case ISD::STORE: - { - SDOperand Chain = Op.getOperand(0); - SDOperand Value = Op.getOperand(1); - SDOperand Address = Op.getOperand(2); - - unsigned Opc; - unsigned opcode = Op.getOpcode(); - - if (opcode == ISD::STORE) { - switch(Value.getValueType()) { - default: assert(0 && "unknown Type in store"); - case MVT::i64: Opc = AlphaISD::STQ_; break; - case MVT::f64: Opc = AlphaISD::STT_; break; - case MVT::f32: Opc = AlphaISD::STS_; break; - } - } else { //ISD::TRUNCSTORE - switch(cast(Op.getOperand(4))->getVT()) { - default: assert(0 && "unknown Type in store"); - case MVT::i8: Opc = AlphaISD::STB_; break; - case MVT::i16: Opc = AlphaISD::STW_; break; - case MVT::i32: Opc = AlphaISD::STL_; break; - } - } - - int i, j, k; - getValueInfo(cast(Op.getOperand(3))->getValue(), i, j, k); - - SDOperand Zero = DAG.getConstant(0, MVT::i64); - std::vector VTS; - VTS.push_back(MVT::Other); - std::vector ARGS; - ARGS.push_back(Chain); - ARGS.push_back(Value); - ARGS.push_back(Zero); - ARGS.push_back(Address); - ARGS.push_back(DAG.getConstant(i, MVT::i64)); - ARGS.push_back(DAG.getConstant(j, MVT::i64)); - ARGS.push_back(DAG.getConstant(k, MVT::i64)); - ARGS.push_back(DAG.getConstant(getUID(), MVT::i64)); - return DAG.getNode(Opc, VTS, ARGS); - } case ISD::VAARG: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); @@ -687,3 +534,13 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return SDOperand(); } + +SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op, + SelectionDAG &DAG) { + assert(Op.getValueType() == MVT::i32 && + Op.getOpcode() == ISD::VAARG && + "Unknown node to custom promote!"); + + // The code in LowerOperation already handles i32 vaarg + return LowerOperation(Op, DAG); +}