X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaLLRP.cpp;h=0c51bc554be949e8d2893577a3a1acf436115f11;hb=1924aabf996be9335fab34e7ee4fa2aa5911389c;hp=15d12c75931127a3e87131f2d24dedb3e694e712;hpb=9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index 15d12c75931..0c51bc554be 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -39,7 +39,7 @@ namespace { static char ID; AlphaLLRPPass(AlphaTargetMachine &tm) - : MachineFunctionPass((intptr_t)&ID), TM(tm) { } + : MachineFunctionPass(&ID), TM(tm) { } virtual const char *getPassName() const { return "Alpha NOP inserter"; @@ -49,6 +49,7 @@ namespace { const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; + DebugLoc dl = DebugLoc::getUnknownLoc(); unsigned count = 0; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { @@ -73,7 +74,7 @@ namespace { prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; @@ -85,10 +86,10 @@ namespace { MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; @@ -99,12 +100,12 @@ namespace { && prev[2]->getOperand(1).getImm() == MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; } @@ -120,9 +121,6 @@ namespace { case Alpha::ALTENT: case Alpha::MEMLABEL: case Alpha::PCLABEL: - case Alpha::IDEF_I: - case Alpha::IDEF_F32: - case Alpha::IDEF_F64: --count; break; case Alpha::BR: @@ -139,7 +137,7 @@ namespace { if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign;