X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPUISelLowering.h;h=ab349bb7851f8b1047a4977401554bc8a9650fc4;hb=3f2bf85d14759cc4b28a86805f566ac805a54d00;hp=3c73aa51c06233b800405dc5f0caa350f9dfd6ab;hpb=203b2d6eed0f35fc8492c78ed2ae1afa854bfbf1;p=oota-llvm.git diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index 3c73aa51c06..ab349bb7851 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -23,11 +23,11 @@ namespace llvm { namespace SPUISD { enum NodeType { // Start the numbering where the builting ops and target ops leave off. - FIRST_NUMBER = ISD::BUILTIN_OP_END+SPU::INSTRUCTION_LIST_END, - + FIRST_NUMBER = ISD::BUILTIN_OP_END, + // Pseudo instructions: RET_FLAG, ///< Return with flag, matched by bi instruction - + Hi, ///< High address component (upper 16) Lo, ///< Low address component (lower 16) PCRelAddr, ///< Program counter relative address @@ -37,102 +37,138 @@ namespace llvm { LDRESULT, ///< Load result (value, chain) CALL, ///< CALL instruction SHUFB, ///< Vector shuffle (permute) - INSERT_MASK, ///< Insert element shuffle mask + SHUFFLE_MASK, ///< Shuffle mask CNTB, ///< Count leading ones in bytes - PROMOTE_SCALAR, ///< Promote scalar->vector - EXTRACT_ELT0, ///< Extract element 0 - EXTRACT_ELT0_CHAINED, ///< Extract element 0, with chain - EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend - EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend - EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend - EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend - MPY, ///< 16-bit Multiply (low parts of a 32-bit) - MPYU, ///< Multiply Unsigned - MPYH, ///< Multiply High - MPYHH, ///< Multiply High-High + PREFSLOT2VEC, ///< Promote scalar->vector + VEC2PREFSLOT, ///< Extract element 0 SHLQUAD_L_BITS, ///< Rotate quad left, by bits SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes - VEC_SHL, ///< Vector shift left - VEC_SRL, ///< Vector shift right (logical) - VEC_SRA, ///< Vector shift right (arithmetic) VEC_ROTL, ///< Vector rotate left VEC_ROTR, ///< Vector rotate right - ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill - ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill - ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI) - ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain - FSMBI, ///< Form Select Mask for Bytes, Immediate + ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count + SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI) SELB, ///< Select bits -> (b & mask) | (a & ~mask) - FPInterp, ///< Floating point interpolate - FPRecipEst, ///< Floating point reciprocal estimate - SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits + // Markers: These aren't used to generate target-dependent nodes, but + // are used during instruction selection. + ADD64_MARKER, ///< i64 addition marker + SUB64_MARKER, ///< i64 subtraction marker + MUL64_MARKER, ///< i64 multiply marker LAST_SPUISD ///< Last user-defined instruction }; } - /// Predicates that are used for node matching: + //! Utility functions specific to CellSPU: namespace SPU { - SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); - SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); - SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); - SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); - SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); - SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG); - SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG); + SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG, + EVT ValueType); + SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG, + EVT ValueType); + SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG, + EVT ValueType); + SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG, + EVT ValueType); + SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, + EVT ValueType); + SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG); + SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG); + + SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG, + const SPUTargetMachine &TM); + //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form + SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat, + DebugLoc dl); } class SPUTargetMachine; // forward dec'l. - + class SPUTargetLowering : public TargetLowering { int VarArgsFrameIndex; // FrameIndex for start of varargs area. - int ReturnAddrIndex; // FrameIndex for return slot. SPUTargetMachine &SPUTM; public: + //! The venerable constructor + /*! + This is where the CellSPU backend sets operation handling (i.e., legal, + custom, expand or promote.) + */ SPUTargetLowering(SPUTargetMachine &TM); - + + //! Get the target machine + SPUTargetMachine &getSPUTargetMachine() { + return SPUTM; + } + /// getTargetNodeName() - This method returns the name of a target specific /// DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ValueType for ISD::SETCC - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; - - /// LowerOperation - Provide custom lowering hooks for some operations. - /// - virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); - - virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; - - virtual void computeMaskedBitsForTargetNode(const SDOperand Op, + virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; + + //! Custom lowering hooks + virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); + + //! Custom lowering hook for nodes with illegal result types. + virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, + SelectionDAG &DAG); + + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + + virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, - APInt &KnownZero, + APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth = 0) const; + virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, + unsigned Depth = 0) const; + ConstraintType getConstraintType(const std::string &ConstraintLetter) const; - std::pair + std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + EVT VT) const; - void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, - std::vector &Ops, + void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, + bool hasMemory, + std::vector &Ops, SelectionDAG &DAG) const; /// isLegalAddressImmediate - Return true if the integer value can be used /// as the offset of the target addressing mode. virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; virtual bool isLegalAddressImmediate(GlobalValue *) const; + + virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; + + /// getFunctionAlignment - Return the Log2 alignment of this function. + virtual unsigned getFunctionAlignment(const Function *F) const; + + virtual SDValue + LowerFormalArguments(SDValue Chain, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl &InVals); + + virtual SDValue + LowerCall(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool isTailCall, + const SmallVectorImpl &Outs, + const SmallVectorImpl &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl &InVals); + + virtual SDValue + LowerReturn(SDValue Chain, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl &Outs, + DebugLoc dl, SelectionDAG &DAG); }; }