X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPUInstrInfo.cpp;h=4af995a78139b5c622861d854a6213c277646773;hb=baeb911d60401818dc9fe0db6182cd048e4fdd03;hp=e72cd1243c52220b25ac0c189c58eea75c36b867;hpb=cc8cd0cbf12c12916d4b38ef0de5be5501c8270e;p=oota-llvm.git

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index e72cd1243c5..4af995a7813 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -17,53 +17,68 @@
 #include "SPUTargetMachine.h"
 #include "SPUGenInstrInfo.inc"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include <iostream>
+#include "llvm/Support/Streams.h"
+#include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
+namespace {
+  //! Predicate for an unconditional branch instruction
+  inline bool isUncondBranch(const MachineInstr *I) {
+    unsigned opc = I->getOpcode();
+
+    return (opc == SPU::BR
+            || opc == SPU::BRA
+            || opc == SPU::BI);
+  }
+
+  //! Predicate for a conditional branch instruction
+  inline bool isCondBranch(const MachineInstr *I) {
+    unsigned opc = I->getOpcode();
+
+    return (opc == SPU::BRNZr32
+            || opc == SPU::BRNZv4i32
+            || opc == SPU::BRZr32
+            || opc == SPU::BRZv4i32
+            || opc == SPU::BRHNZr16
+            || opc == SPU::BRHNZv8i16
+            || opc == SPU::BRHZr16
+            || opc == SPU::BRHZv8i16);
+  }
+}
+
 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
   : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
     TM(tm),
     RI(*TM.getSubtargetImpl(), *this)
-{
-  /* NOP */
-}
-
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *
-SPUInstrInfo::getPointerRegClass() const
-{
-  return &SPU::R32CRegClass;
-}
+{ /* NOP */ }
 
 bool
 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
                           unsigned& sourceReg,
-                          unsigned& destReg) const {
-  // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
-  // cases where we can safely say that what's being done is really a move
-  // (see how PowerPC does this -- it's the model for this code too.)
+                          unsigned& destReg,
+                          unsigned& SrcSR, unsigned& DstSR) const {
+  SrcSR = DstSR = 0;  // No sub-registers.
+
   switch (MI.getOpcode()) {
   default:
     break;
   case SPU::ORIv4i32:
   case SPU::ORIr32:
-  case SPU::ORIr64:
   case SPU::ORHIv8i16:
   case SPU::ORHIr16:
-  case SPU::ORHI1To2:
+  case SPU::ORHIi8i16:
   case SPU::ORBIv16i8:
   case SPU::ORBIr8:
-  case SPU::ORI2To4:
-  case SPU::ORI1To4:
+  case SPU::ORIi16i32:
+  case SPU::ORIi8i32:
   case SPU::AHIvec:
   case SPU::AHIr16:
-  case SPU::AIvec:
+  case SPU::AIv4i32:
     assert(MI.getNumOperands() == 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
     if (MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
@@ -74,16 +89,28 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
   case SPU::AIr32:
     assert(MI.getNumOperands() == 3 &&
            "wrong number of operands to AIr32");
-    if (MI.getOperand(0).isRegister() &&
-        (MI.getOperand(1).isRegister() ||
-         MI.getOperand(1).isFrameIndex()) &&
-        (MI.getOperand(2).isImmediate() &&
+    if (MI.getOperand(0).isReg() &&
+        MI.getOperand(1).isReg() &&
+        (MI.getOperand(2).isImm() &&
          MI.getOperand(2).getImm() == 0)) {
       sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
       return true;
     }
     break;
+  case SPU::LRr8:
+  case SPU::LRr16:
+  case SPU::LRr32:
+  case SPU::LRf32:
+  case SPU::LRr64:
+  case SPU::LRf64:
+  case SPU::LRr128:
+  case SPU::LRv16i8:
+  case SPU::LRv8i16:
+  case SPU::LRv4i32:
+  case SPU::LRv4f32:
+  case SPU::LRv2i64:
+  case SPU::LRv2f64:
   case SPU::ORv16i8_i8:
   case SPU::ORv8i16_i16:
   case SPU::ORv4i32_i32:
@@ -96,18 +123,68 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
   case SPU::ORi64_v2i64:
   case SPU::ORf32_v4f32:
   case SPU::ORf64_v2f64:
+/*
+  case SPU::ORi128_r64:
+  case SPU::ORi128_f64:
+  case SPU::ORi128_r32:
+  case SPU::ORi128_f32:
+  case SPU::ORi128_r16:
+  case SPU::ORi128_r8:
+*/
+  case SPU::ORi128_vec:
+/*
+  case SPU::ORr64_i128:
+  case SPU::ORf64_i128:
+  case SPU::ORr32_i128:
+  case SPU::ORf32_i128:
+  case SPU::ORr16_i128:
+  case SPU::ORr8_i128:
+*/
+  case SPU::ORvec_i128:
+/*
+  case SPU::ORr16_r32:
+  case SPU::ORr8_r32:
+  case SPU::ORf32_r32:
+  case SPU::ORr32_f32:
+  case SPU::ORr32_r16:
+  case SPU::ORr32_r8:
+  case SPU::ORr16_r64:
+  case SPU::ORr8_r64:
+  case SPU::ORr64_r16:
+  case SPU::ORr64_r8:
+*/
+  case SPU::ORr64_r32:
+  case SPU::ORr32_r64:
+  case SPU::ORf32_r32:
+  case SPU::ORr32_f32:
+  case SPU::ORf64_r64:
+  case SPU::ORr64_f64: {
+    assert(MI.getNumOperands() == 2 &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           "invalid SPU OR<type>_<vec> or LR instruction!");
+    if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
+    break;
+  }
   case SPU::ORv16i8:
   case SPU::ORv8i16:
   case SPU::ORv4i32:
+  case SPU::ORv2i64:
+  case SPU::ORr8:
+  case SPU::ORr16:
   case SPU::ORr32:
   case SPU::ORr64:
+  case SPU::ORr128:
   case SPU::ORf32:
   case SPU::ORf64:
-  case SPU::ORgprc:
     assert(MI.getNumOperands() == 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid SPU OR(vec|r32|r64|gprc) instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -121,7 +198,8 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
 }
 
 unsigned
-SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
+SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
+                                  int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
   case SPU::LQDv16i8:
@@ -132,24 +210,22 @@ SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case SPU::LQDr128:
   case SPU::LQDr64:
   case SPU::LQDr32:
-  case SPU::LQDr16:
-  case SPU::LQXv4i32:
-  case SPU::LQXr128:
-  case SPU::LQXr64:
-  case SPU::LQXr32:
-  case SPU::LQXr16:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
-      FrameIndex = MI->getOperand(2).getIndex();
+  case SPU::LQDr16: {
+    const MachineOperand MOp1 = MI->getOperand(1);
+    const MachineOperand MOp2 = MI->getOperand(2);
+    if (MOp1.isImm() && MOp2.isFI()) {
+      FrameIndex = MOp2.getIndex();
       return MI->getOperand(0).getReg();
     }
     break;
   }
+  }
   return 0;
 }
 
 unsigned
-SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
+SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
+                                 int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
   case SPU::STQDv16i8:
@@ -161,62 +237,55 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case SPU::STQDr64:
   case SPU::STQDr32:
   case SPU::STQDr16:
-    // case SPU::STQDr8:
-  case SPU::STQXv16i8:
-  case SPU::STQXv8i16:
-  case SPU::STQXv4i32:
-  case SPU::STQXv4f32:
-  case SPU::STQXv2f64:
-  case SPU::STQXr128:
-  case SPU::STQXr64:
-  case SPU::STQXr32:
-  case SPU::STQXr16:
-    // case SPU::STQXr8:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
-      FrameIndex = MI->getOperand(2).getIndex();
+  case SPU::STQDr8: {
+    const MachineOperand MOp1 = MI->getOperand(1);
+    const MachineOperand MOp2 = MI->getOperand(2);
+    if (MOp1.isImm() && MOp2.isFI()) {
+      FrameIndex = MOp2.getIndex();
       return MI->getOperand(0).getReg();
     }
     break;
   }
+  }
   return 0;
 }
 
-void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const
 {
-  if (DestRC != SrcRC) {
-    cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
-    abort();
-  }
+  // We support cross register class moves for our aliases, such as R3 in any
+  // reg class to any other reg class containing R3.  This is required because
+  // we instruction select bitconvert i64 -> f64 as a noop for example, so our
+  // types have no specific meaning.
+
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (MI != MBB.end()) DL = MI->getDebugLoc();
 
   if (DestRC == SPU::R8CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::R16CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::R32CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::R32FPRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
-      .addReg(SrcReg);
+    BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::R64CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::R64FPRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
-      .addReg(SrcReg);
+    BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::GPRCRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
-      .addReg(SrcReg);
+    BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
   } else if (DestRC == SPU::VECREGRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
-      .addReg(SrcReg);
+    BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
   } else {
-    std::cerr << "Attempt to copy unknown/unsupported register class!\n";
-    abort();
+    // Attempt to copy unknown/unsupported register class!
+    return false;
   }
+
+  return true;
 }
 
 void
@@ -226,48 +295,43 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      const TargetRegisterClass *RC) const
 {
   unsigned opc;
+  bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
   if (RC == SPU::GPRCRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr128
-      : SPU::STQXr128;
+    opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
   } else if (RC == SPU::R64CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr64
-      : SPU::STQXr64;
+    opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
   } else if (RC == SPU::R64FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr64
-      : SPU::STQXr64;
+    opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
   } else if (RC == SPU::R32CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr32
-      : SPU::STQXr32;
+    opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
   } else if (RC == SPU::R32FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr32
-      : SPU::STQXr32;
+    opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
   } else if (RC == SPU::R16CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
-      SPU::STQDr16
-      : SPU::STQXr16;
+    opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
+  } else if (RC == SPU::R8CRegisterClass) {
+    opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
+  } else if (RC == SPU::VECREGRegisterClass) {
+    opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
   } else {
     assert(0 && "Unknown regclass!");
     abort();
   }
 
-  addFrameReference(BuildMI(MBB, MI, get(opc))
-                    .addReg(SrcReg, false, false, isKill), FrameIdx);
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (MI != MBB.end()) DL = MI->getDebugLoc();
+  addFrameReference(BuildMI(MBB, MI, DL, get(opc))
+                    .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
 }
 
 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     bool isKill,
-                                     SmallVectorImpl<MachineOperand> &Addr,
-                                     const TargetRegisterClass *RC,
-                                     SmallVectorImpl<MachineInstr*> &NewMIs) const {
+                                  bool isKill,
+                                  SmallVectorImpl<MachineOperand> &Addr,
+                                  const TargetRegisterClass *RC,
+                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
   cerr << "storeRegToAddr() invoked!\n";
   abort();
 
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     /* do what storeRegToStackSlot does here */
   } else {
     unsigned Opc = 0;
@@ -287,17 +351,11 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
       assert(0 && "Unknown regclass!");
       abort();
     }
-    MachineInstrBuilder MIB = BuildMI(get(Opc))
-      .addReg(SrcReg, false, false, isKill);
-    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-      MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
-        MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
-        MIB.addImm(MO.getImm());
-      else
-        MIB.addFrameIndex(MO.getIndex());
-    }
+    DebugLoc DL = DebugLoc::getUnknownLoc();
+    MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
+      .addReg(SrcReg, getKillRegState(isKill));
+    for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+      MIB.addOperand(Addr[i]);
     NewMIs.push_back(MIB);
   }
 }
@@ -309,50 +367,45 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         const TargetRegisterClass *RC) const
 {
   unsigned opc;
+  bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
   if (RC == SPU::GPRCRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr128
-      : SPU::LQXr128;
+    opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
   } else if (RC == SPU::R64CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr64
-      : SPU::LQXr64;
+    opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
   } else if (RC == SPU::R64FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr64
-      : SPU::LQXr64;
+    opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
   } else if (RC == SPU::R32CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr32
-      : SPU::LQXr32;
+    opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
   } else if (RC == SPU::R32FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr32
-      : SPU::LQXr32;
+    opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
   } else if (RC == SPU::R16CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr16
-      : SPU::LQXr16;
+    opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
+  } else if (RC == SPU::R8CRegisterClass) {
+    opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
+  } else if (RC == SPU::VECREGRegisterClass) {
+    opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
   } else {
     assert(0 && "Unknown regclass in loadRegFromStackSlot!");
     abort();
   }
 
-  addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (MI != MBB.end()) DL = MI->getDebugLoc();
+  addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
 }
 
 /*!
   \note We are really pessimistic here about what kind of a load we're doing.
  */
 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVectorImpl<MachineOperand> &Addr,
-                                      const TargetRegisterClass *RC,
-                                      SmallVectorImpl<MachineInstr*> &NewMIs)
+                                   SmallVectorImpl<MachineOperand> &Addr,
+                                   const TargetRegisterClass *RC,
+                                   SmallVectorImpl<MachineInstr*> &NewMIs)
     const {
   cerr << "loadRegToAddr() invoked!\n";
   abort();
 
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     /* do what loadRegFromStackSlot does here... */
   } else {
     unsigned Opc = 0;
@@ -374,56 +427,267 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
       assert(0 && "Unknown regclass!");
       abort();
     }
-    MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
-    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-      MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
-        MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
-        MIB.addImm(MO.getImm());
-      else
-        MIB.addFrameIndex(MO.getIndex());
-    }
+    DebugLoc DL = DebugLoc::getUnknownLoc();
+    MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
+    for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+      MIB.addOperand(Addr[i]);
     NewMIs.push_back(MIB);
   }
 }
 
+//! Return true if the specified load or store can be folded
+bool
+SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
+                                   const SmallVectorImpl<unsigned> &Ops) const {
+  if (Ops.size() != 1) return false;
+
+  // Make sure this is a reg-reg copy.
+  unsigned Opc = MI->getOpcode();
+
+  switch (Opc) {
+  case SPU::ORv16i8:
+  case SPU::ORv8i16:
+  case SPU::ORv4i32:
+  case SPU::ORv2i64:
+  case SPU::ORr8:
+  case SPU::ORr16:
+  case SPU::ORr32:
+  case SPU::ORr64:
+  case SPU::ORf32:
+  case SPU::ORf64:
+    if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
+      return true;
+    break;
+  }
+
+  return false;
+}
+
 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
 /// copy instructions, turning them into load/store instructions.
 MachineInstr *
-SPUInstrInfo::foldMemoryOperand(MachineInstr *MI,
-                                   SmallVectorImpl<unsigned> &Ops,
-                                   int FrameIndex) const
+SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
+                                    MachineInstr *MI,
+                                    const SmallVectorImpl<unsigned> &Ops,
+                                    int FrameIndex) const
 {
-#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
-  if (Ops.size() != 1) return NULL;
+  if (Ops.size() != 1) return 0;
 
   unsigned OpNum = Ops[0];
   unsigned Opc = MI->getOpcode();
   MachineInstr *NewMI = 0;
-  
-  if ((Opc == SPU::ORr32
-       || Opc == SPU::ORv4i32)
-       && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
+
+  switch (Opc) {
+  case SPU::ORv16i8:
+  case SPU::ORv8i16:
+  case SPU::ORv4i32:
+  case SPU::ORv2i64:
+  case SPU::ORr8:
+  case SPU::ORr16:
+  case SPU::ORr32:
+  case SPU::ORr64:
+  case SPU::ORf32:
+  case SPU::ORf64:
     if (OpNum == 0) {  // move -> store
       unsigned InReg = MI->getOperand(1).getReg();
+      bool isKill = MI->getOperand(1).isKill();
       if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
-	NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
-				  FrameIndex);
+        MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
+                                          get(SPU::STQDr32));
+
+        MIB.addReg(InReg, getKillRegState(isKill));
+        NewMI = addFrameReference(MIB, FrameIndex);
       }
     } else {           // move -> load
       unsigned OutReg = MI->getOperand(0).getReg();
-      Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
-      NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
+      bool isDead = MI->getOperand(0).isDead();
+      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
+
+      MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead));
+      Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
+        ? SPU::STQDr32 : SPU::STQXr32;
+      NewMI = addFrameReference(MIB, FrameIndex);
+    break;
+  }
+  }
+
+  return NewMI;
+}
+
+//! Branch analysis
+/*!
+  \note This code was kiped from PPC. There may be more branch analysis for
+  CellSPU than what's currently done here.
+ */
+bool
+SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+                            MachineBasicBlock *&FBB,
+                            SmallVectorImpl<MachineOperand> &Cond,
+                            bool AllowModify) const {
+  // If the block has no terminators, it just falls into the block after it.
+  MachineBasicBlock::iterator I = MBB.end();
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
+    return false;
+
+  // Get the last instruction in the block.
+  MachineInstr *LastInst = I;
+
+  // If there is only one terminator instruction, process it.
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
+    if (isUncondBranch(LastInst)) {
+      TBB = LastInst->getOperand(0).getMBB();
+      return false;
+    } else if (isCondBranch(LastInst)) {
+      // Block ends with fall-through condbranch.
+      TBB = LastInst->getOperand(1).getMBB();
+      DEBUG(cerr << "Pushing LastInst:               ");
+      DEBUG(LastInst->dump());
+      Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
+      Cond.push_back(LastInst->getOperand(0));
+      return false;
     }
+    // Otherwise, don't know what this is.
+    return true;
   }
 
-  if (NewMI)
-    NewMI->copyKillDeadInfo(MI);
+  // Get the instruction before it if it's a terminator.
+  MachineInstr *SecondLastInst = I;
 
-  return NewMI;
-#else
-  return 0;
-#endif
+  // If there are three terminators, we don't know what sort of block this is.
+  if (SecondLastInst && I != MBB.begin() &&
+      isUnpredicatedTerminator(--I))
+    return true;
+
+  // If the block ends with a conditional and unconditional branch, handle it.
+  if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
+    TBB =  SecondLastInst->getOperand(1).getMBB();
+    DEBUG(cerr << "Pushing SecondLastInst:         ");
+    DEBUG(SecondLastInst->dump());
+    Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
+    Cond.push_back(SecondLastInst->getOperand(0));
+    FBB = LastInst->getOperand(0).getMBB();
+    return false;
+  }
+
+  // If the block ends with two unconditional branches, handle it.  The second
+  // one is not executed, so remove it.
+  if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
+    TBB = SecondLastInst->getOperand(0).getMBB();
+    I = LastInst;
+    if (AllowModify)
+      I->eraseFromParent();
+    return false;
+  }
+
+  // Otherwise, can't handle this.
+  return true;
+}
+
+unsigned
+SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
+  MachineBasicBlock::iterator I = MBB.end();
+  if (I == MBB.begin())
+    return 0;
+  --I;
+  if (!isCondBranch(I) && !isUncondBranch(I))
+    return 0;
+
+  // Remove the first branch.
+  DEBUG(cerr << "Removing branch:                ");
+  DEBUG(I->dump());
+  I->eraseFromParent();
+  I = MBB.end();
+  if (I == MBB.begin())
+    return 1;
+
+  --I;
+  if (!(isCondBranch(I) || isUncondBranch(I)))
+    return 1;
+
+  // Remove the second branch.
+  DEBUG(cerr << "Removing second branch:         ");
+  DEBUG(I->dump());
+  I->eraseFromParent();
+  return 2;
 }
 
+unsigned
+SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                           MachineBasicBlock *FBB,
+                           const SmallVectorImpl<MachineOperand> &Cond) const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
+  // Shouldn't be a fall through.
+  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+  assert((Cond.size() == 2 || Cond.size() == 0) &&
+         "SPU branch conditions have two components!");
+
+  // One-way branch.
+  if (FBB == 0) {
+    if (Cond.empty()) {
+      // Unconditional branch
+      MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
+      MIB.addMBB(TBB);
+
+      DEBUG(cerr << "Inserted one-way uncond branch: ");
+      DEBUG((*MIB).dump());
+    } else {
+      // Conditional branch
+      MachineInstrBuilder  MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
+      MIB.addReg(Cond[1].getReg()).addMBB(TBB);
+
+      DEBUG(cerr << "Inserted one-way cond branch:   ");
+      DEBUG((*MIB).dump());
+    }
+    return 1;
+  } else {
+    MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
+    MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
+
+    // Two-way Conditional Branch.
+    MIB.addReg(Cond[1].getReg()).addMBB(TBB);
+    MIB2.addMBB(FBB);
+
+    DEBUG(cerr << "Inserted conditional branch:    ");
+    DEBUG((*MIB).dump());
+    DEBUG(cerr << "part 2: ");
+    DEBUG((*MIB2).dump());
+   return 2;
+  }
+}
+
+bool
+SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
+  return (!MBB.empty() && isUncondBranch(&MBB.back()));
+}
+//! Reverses a branch's condition, returning false on success.
+bool
+SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
+  const {
+  // Pretty brainless way of inverting the condition, but it works, considering
+  // there are only two conditions...
+  static struct {
+    unsigned Opc;               //! The incoming opcode
+    unsigned RevCondOpc;        //! The reversed condition opcode
+  } revconds[] = {
+    { SPU::BRNZr32, SPU::BRZr32 },
+    { SPU::BRNZv4i32, SPU::BRZv4i32 },
+    { SPU::BRZr32, SPU::BRNZr32 },
+    { SPU::BRZv4i32, SPU::BRNZv4i32 },
+    { SPU::BRHNZr16, SPU::BRHZr16 },
+    { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
+    { SPU::BRHZr16, SPU::BRHNZr16 },
+    { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
+  };
+
+  unsigned Opc = unsigned(Cond[0].getImm());
+  // Pretty dull mapping between the two conditions that SPU can generate:
+  for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
+    if (revconds[i].Opc == Opc) {
+      Cond[0].setImm(revconds[i].RevCondOpc);
+      return false;
+    }
+  }
+
+  return true;
+}