X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPUInstrInfo.td;h=25f6fd000b8ba4c139a117b03fb08bd5361c9a65;hb=1e09e5b979249ae08082569cbf0ab24d297ee0dd;hp=8b9ed31dfbe93b34850b6627d00ef89b502ae749;hpb=c8478d8b12c2d7e4cea32d0c9940f5cac2baa4dd;p=oota-llvm.git diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 8b9ed31dfbe..25f6fd000b8 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1,10 +1,10 @@ //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // Cell SPU Instructions: //===----------------------------------------------------------------------===// @@ -22,23 +22,14 @@ //===----------------------------------------------------------------------===// let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in { - def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), + def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt), "${:comment} ADJCALLSTACKDOWN", - [(callseq_start imm:$amt)]>; - def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt), + [(callseq_start timm:$amt)]>; + def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt), "${:comment} ADJCALLSTACKUP", - [(callseq_end imm:$amt)]>; + [(callseq_end timm:$amt)]>; } -//===----------------------------------------------------------------------===// -// DWARF debugging Pseudo Instructions -//===----------------------------------------------------------------------===// - -def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), - "${:comment} .loc $file, $line, $col", - [(dwarf_loc (i32 imm:$line), (i32 imm:$col), - (i32 imm:$file))]>; - //===----------------------------------------------------------------------===// // Loads: // NB: The ordering is actually important, since the instruction selection @@ -47,206 +38,110 @@ def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$fi // finally the X-form with the register-register. //===----------------------------------------------------------------------===// -let isLoad = 1 in { - def LQDv16i8: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v16i8 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDv8i16: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v8i16 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDv4i32: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v4i32 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDv2i64: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v2i64 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDv4f32: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v4f32 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDv2f64: - RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set (v2f64 VECREG:$rT), (load dform_addr:$src))]>; - - def LQDr128: - RI10Form<0b00101100, (outs GPRC:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set GPRC:$rT, (load dform_addr:$src))]>; - - def LQDr64: - RI10Form<0b00101100, (outs R64C:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R64C:$rT, (load dform_addr:$src))]>; - - def LQDr32: - RI10Form<0b00101100, (outs R32C:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R32C:$rT, (load dform_addr:$src))]>; - - // Floating Point - def LQDf32: - RI10Form<0b00101100, (outs R32FP:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R32FP:$rT, (load dform_addr:$src))]>; - - def LQDf64: - RI10Form<0b00101100, (outs R64FP:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R64FP:$rT, (load dform_addr:$src))]>; - // END Floating Point - - def LQDr16: - RI10Form<0b00101100, (outs R16C:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R16C:$rT, (load dform_addr:$src))]>; - - def LQDr8: - RI10Form<0b00101100, (outs R8C:$rT), (ins memri10:$src), - "lqd\t$rT, $src", LoadStore, - [(set R8C:$rT, (load dform_addr:$src))]>; - - def LQAv16i8: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v16i8 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAv8i16: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v8i16 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAv4i32: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v4i32 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAv2i64: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v2i64 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAv4f32: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v4f32 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAv2f64: - RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set (v2f64 VECREG:$rT), (load aform_addr:$src))]>; - - def LQAr128: - RI16Form<0b100001100, (outs GPRC:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set GPRC:$rT, (load aform_addr:$src))]>; - - def LQAr64: - RI16Form<0b100001100, (outs R64C:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R64C:$rT, (load aform_addr:$src))]>; - - def LQAr32: - RI16Form<0b100001100, (outs R32C:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R32C:$rT, (load aform_addr:$src))]>; - - def LQAf32: - RI16Form<0b100001100, (outs R32FP:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R32FP:$rT, (load aform_addr:$src))]>; - - def LQAf64: - RI16Form<0b100001100, (outs R64FP:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R64FP:$rT, (load aform_addr:$src))]>; - - def LQAr16: - RI16Form<0b100001100, (outs R16C:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R16C:$rT, (load aform_addr:$src))]>; - - def LQAr8: - RI16Form<0b100001100, (outs R8C:$rT), (ins addr256k:$src), - "lqa\t$rT, $src", LoadStore, - [(set R8C:$rT, (load aform_addr:$src))]>; - - def LQXv16i8: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v16i8 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXv8i16: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v8i16 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXv4i32: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v4i32 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXv2i64: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v2i64 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXv4f32: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v4f32 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXv2f64: - RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set (v2f64 VECREG:$rT), (load xform_addr:$src))]>; - - def LQXr128: - RRForm<0b00100011100, (outs GPRC:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set GPRC:$rT, (load xform_addr:$src))]>; - - def LQXr64: - RRForm<0b00100011100, (outs R64C:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R64C:$rT, (load xform_addr:$src))]>; - - def LQXr32: - RRForm<0b00100011100, (outs R32C:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R32C:$rT, (load xform_addr:$src))]>; - - def LQXf32: - RRForm<0b00100011100, (outs R32FP:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R32FP:$rT, (load xform_addr:$src))]>; - - def LQXf64: - RRForm<0b00100011100, (outs R64FP:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R64FP:$rT, (load xform_addr:$src))]>; - - def LQXr16: - RRForm<0b00100011100, (outs R16C:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R16C:$rT, (load xform_addr:$src))]>; - - def LQXr8: - RRForm<0b00100011100, (outs R8C:$rT), (ins memrr:$src), - "lqx\t$rT, $src", LoadStore, - [(set R8C:$rT, (load xform_addr:$src))]>; +let canFoldAsLoad = 1 in { + class LoadDFormVec + : RI10Form<0b00101100, (outs VECREG:$rT), (ins dformaddr:$src), + "lqd\t$rT, $src", + LoadStore, + [(set (vectype VECREG:$rT), (load dform_addr:$src))]> + { } + + class LoadDForm + : RI10Form<0b00101100, (outs rclass:$rT), (ins dformaddr:$src), + "lqd\t$rT, $src", + LoadStore, + [(set rclass:$rT, (load dform_addr:$src))]> + { } + + multiclass LoadDForms + { + def v16i8: LoadDFormVec; + def v8i16: LoadDFormVec; + def v4i32: LoadDFormVec; + def v2i64: LoadDFormVec; + def v4f32: LoadDFormVec; + def v2f64: LoadDFormVec; + + def r128: LoadDForm; + def r64: LoadDForm; + def r32: LoadDForm; + def f32: LoadDForm; + def f64: LoadDForm; + def r16: LoadDForm; + def r8: LoadDForm; + } + + class LoadAFormVec + : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src), + "lqa\t$rT, $src", + LoadStore, + [(set (vectype VECREG:$rT), (load aform_addr:$src))]> + { } + + class LoadAForm + : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src), + "lqa\t$rT, $src", + LoadStore, + [(set rclass:$rT, (load aform_addr:$src))]> + { } + + multiclass LoadAForms + { + def v16i8: LoadAFormVec; + def v8i16: LoadAFormVec; + def v4i32: LoadAFormVec; + def v2i64: LoadAFormVec; + def v4f32: LoadAFormVec; + def v2f64: LoadAFormVec; + + def r128: LoadAForm; + def r64: LoadAForm; + def r32: LoadAForm; + def f32: LoadAForm; + def f64: LoadAForm; + def r16: LoadAForm; + def r8: LoadAForm; + } + + class LoadXFormVec + : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src), + "lqx\t$rT, $src", + LoadStore, + [(set (vectype VECREG:$rT), (load xform_addr:$src))]> + { } + + class LoadXForm + : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src), + "lqx\t$rT, $src", + LoadStore, + [(set rclass:$rT, (load xform_addr:$src))]> + { } + + multiclass LoadXForms + { + def v16i8: LoadXFormVec; + def v8i16: LoadXFormVec; + def v4i32: LoadXFormVec; + def v2i64: LoadXFormVec; + def v4f32: LoadXFormVec; + def v2f64: LoadXFormVec; + + def r128: LoadXForm; + def r64: LoadXForm; + def r32: LoadXForm; + def f32: LoadXForm; + def f64: LoadXForm; + def r16: LoadXForm; + def r8: LoadXForm; + } + + defm LQA : LoadAForms; + defm LQD : LoadDForms; + defm LQX : LoadXForms; /* Load quadword, PC relative: Not much use at this point in time. - Might be of use later for relocatable code. + Might be of use later for relocatable code. It's effectively the + same as LQA, but uses PC-relative addressing. def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp), "lqr\t$rT, $disp", LoadStore, [(set VECREG:$rT, (load iaddr:$disp))]>; @@ -256,174 +151,106 @@ let isLoad = 1 in { //===----------------------------------------------------------------------===// // Stores: //===----------------------------------------------------------------------===// +class StoreDFormVec + : RI10Form<0b00100100, (outs), (ins VECREG:$rT, dformaddr:$src), + "stqd\t$rT, $src", + LoadStore, + [(store (vectype VECREG:$rT), dform_addr:$src)]> +{ } + +class StoreDForm + : RI10Form<0b00100100, (outs), (ins rclass:$rT, dformaddr:$src), + "stqd\t$rT, $src", + LoadStore, + [(store rclass:$rT, dform_addr:$src)]> +{ } + +multiclass StoreDForms +{ + def v16i8: StoreDFormVec; + def v8i16: StoreDFormVec; + def v4i32: StoreDFormVec; + def v2i64: StoreDFormVec; + def v4f32: StoreDFormVec; + def v2f64: StoreDFormVec; + + def r128: StoreDForm; + def r64: StoreDForm; + def r32: StoreDForm; + def f32: StoreDForm; + def f64: StoreDForm; + def r16: StoreDForm; + def r8: StoreDForm; +} -def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v16i8 VECREG:$rT), dform_addr:$src)]>; - -def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v8i16 VECREG:$rT), dform_addr:$src)]>; - -def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v4i32 VECREG:$rT), dform_addr:$src)]>; - -def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v2i64 VECREG:$rT), dform_addr:$src)]>; - -def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v4f32 VECREG:$rT), dform_addr:$src)]>; - -def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store (v2f64 VECREG:$rT), dform_addr:$src)]>; - -def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store GPRC:$rT, dform_addr:$src)]>; - -def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R64C:$rT, dform_addr:$src)]>; - -def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R32C:$rT, dform_addr:$src)]>; - -// Floating Point -def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R32FP:$rT, dform_addr:$src)]>; +class StoreAFormVec + : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src), + "stqa\t$rT, $src", + LoadStore, + [(store (vectype VECREG:$rT), aform_addr:$src)]>; + +class StoreAForm + : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src), + "stqa\t$rT, $src", + LoadStore, + [(store rclass:$rT, aform_addr:$src)]>; + +multiclass StoreAForms +{ + def v16i8: StoreAFormVec; + def v8i16: StoreAFormVec; + def v4i32: StoreAFormVec; + def v2i64: StoreAFormVec; + def v4f32: StoreAFormVec; + def v2f64: StoreAFormVec; + + def r128: StoreAForm; + def r64: StoreAForm; + def r32: StoreAForm; + def f32: StoreAForm; + def f64: StoreAForm; + def r16: StoreAForm; + def r8: StoreAForm; +} -def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R64FP:$rT, dform_addr:$src)]>; +class StoreXFormVec + : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), + "stqx\t$rT, $src", + LoadStore, + [(store (vectype VECREG:$rT), xform_addr:$src)]> +{ } + +class StoreXForm + : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src), + "stqx\t$rT, $src", + LoadStore, + [(store rclass:$rT, xform_addr:$src)]> +{ } + +multiclass StoreXForms +{ + def v16i8: StoreXFormVec; + def v8i16: StoreXFormVec; + def v4i32: StoreXFormVec; + def v2i64: StoreXFormVec; + def v4f32: StoreXFormVec; + def v2f64: StoreXFormVec; + + def r128: StoreXForm; + def r64: StoreXForm; + def r32: StoreXForm; + def f32: StoreXForm; + def f64: StoreXForm; + def r16: StoreXForm; + def r8: StoreXForm; +} -def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R16C:$rT, dform_addr:$src)]>; - -def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src), - "stqd\t$rT, $src", LoadStore, - [(store R8C:$rT, dform_addr:$src)]>; - -def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v16i8 VECREG:$rT), aform_addr:$src)]>; - -def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v8i16 VECREG:$rT), aform_addr:$src)]>; - -def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v4i32 VECREG:$rT), aform_addr:$src)]>; - -def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v2i64 VECREG:$rT), aform_addr:$src)]>; - -def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v4f32 VECREG:$rT), aform_addr:$src)]>; - -def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store (v2f64 VECREG:$rT), aform_addr:$src)]>; - -def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store GPRC:$rT, aform_addr:$src)]>; - -def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R64C:$rT, aform_addr:$src)]>; - -def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R32C:$rT, aform_addr:$src)]>; - -// Floating Point -def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R32FP:$rT, aform_addr:$src)]>; - -def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R64FP:$rT, aform_addr:$src)]>; - -def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R16C:$rT, aform_addr:$src)]>; - -def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src), - "stqa\t$rT, $src", LoadStore, - [(store R8C:$rT, aform_addr:$src)]>; - -def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v16i8 VECREG:$rT), xform_addr:$src)]>; - -def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v8i16 VECREG:$rT), xform_addr:$src)]>; - -def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v4i32 VECREG:$rT), xform_addr:$src)]>; - -def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v2i64 VECREG:$rT), xform_addr:$src)]>; - -def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v4f32 VECREG:$rT), xform_addr:$src)]>; - -def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store (v2f64 VECREG:$rT), xform_addr:$src)]>; - -def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store GPRC:$rT, xform_addr:$src)]>; - -def STQXr64: - RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R64C:$rT, xform_addr:$src)]>; - -def STQXr32: - RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R32C:$rT, xform_addr:$src)]>; - -// Floating Point -def STQXf32: - RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R32FP:$rT, xform_addr:$src)]>; - -def STQXf64: - RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R64FP:$rT, xform_addr:$src)]>; - -def STQXr16: - RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R16C:$rT, xform_addr:$src)]>; - -def STQXr8: - RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src), - "stqx\t$rT, $src", LoadStore, - [(store R8C:$rT, xform_addr:$src)]>; +defm STQD : StoreDForms; +defm STQA : StoreAForms; +defm STQX : StoreXForms; /* Store quadword, PC relative: Not much use at this point in time. Might - be useful for relocatable code. + be useful for relocatable code. def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp), "stqr\t$rT, $disp", LoadStore, [(store VECREG:$rT, iaddr:$disp)]>; @@ -433,38 +260,53 @@ def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp), // Generate Controls for Insertion: //===----------------------------------------------------------------------===// -def CBD : - RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src), - "cbd\t$rT, $src", ShuffleOp, - [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>; +def CBD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src), + "cbd\t$rT, $src", ShuffleOp, + [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; -def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src), +def CBX: RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src), "cbx\t$rT, $src", ShuffleOp, - [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>; + [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; -def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src), +def CHD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src), "chd\t$rT, $src", ShuffleOp, - [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>; + [(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; -def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src), +def CHX: RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src), "chx\t$rT, $src", ShuffleOp, - [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>; + [(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; -def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src), +def CWD: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src), "cwd\t$rT, $src", ShuffleOp, - [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>; + [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; -def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src), +def CWX: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src), "cwx\t$rT, $src", ShuffleOp, - [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>; + [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; + +def CWDf32: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src), + "cwd\t$rT, $src", ShuffleOp, + [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; + +def CWXf32: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src), + "cwx\t$rT, $src", ShuffleOp, + [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; + +def CDD: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src), + "cdd\t$rT, $src", ShuffleOp, + [(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; + +def CDX: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src), + "cdx\t$rT, $src", ShuffleOp, + [(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; -def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src), +def CDDf64: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src), "cdd\t$rT, $src", ShuffleOp, - [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>; + [(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>; -def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src), +def CDXf64: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src), "cdx\t$rT, $src", ShuffleOp, - [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>; + [(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>; //===----------------------------------------------------------------------===// // Constant formation: @@ -488,142 +330,223 @@ def ILHr8: [(set R8C:$rT, immSExt8:$val)]>; // IL does sign extension! -def ILr64: - RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val), - "il\t$rT, $val", ImmLoad, - [(set R64C:$rT, immSExt16:$val)]>; - -def ILv2i64: - RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val), - "il\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>; - -def ILv4i32: - RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val), - "il\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>; - -def ILr32: - RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val), - "il\t$rT, $val", ImmLoad, - [(set R32C:$rT, immSExt16:$val)]>; - -def ILf32: - RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val), - "il\t$rT, $val", ImmLoad, - [(set R32FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>; - -def ILf64: - RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val), - "il\t$rT, $val", ImmLoad, - [(set R64FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>; - -def ILHUv4i32: - RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v4i32 immILHUvec:$val))]>; - -def ILHUr32: - RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32C:$rT, hi16:$val)]>; - -// ILHUf32: Used to custom lower float constant loads -def ILHUf32: - RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32FP:$rT, (SPUFPconstant hi16_f32:$val))]>; - -// ILHUhi: Used for loading high portion of an address. Note the symbolHi -// printer used for the operand. -def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32C:$rT, hi16:$val)]>; + +class ILInst pattern>: + RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val", + ImmLoad, pattern>; + +class ILVecInst: + ILInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILRegInst: + ILInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + +multiclass ImmediateLoad +{ + def v2i64: ILVecInst; + def v4i32: ILVecInst; + + // TODO: Need v2f64, v4f32 + + def r64: ILRegInst; + def r32: ILRegInst; + def f32: ILRegInst; + def f64: ILRegInst; +} + +defm IL : ImmediateLoad; + +class ILHUInst pattern>: + RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val", + ImmLoad, pattern>; + +class ILHUVecInst: + ILHUInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILHURegInst: + ILHUInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + +multiclass ImmLoadHalfwordUpper +{ + def v2i64: ILHUVecInst; + def v4i32: ILHUVecInst; + + def r64: ILHURegInst; + def r32: ILHURegInst; + + // Loads the high portion of an address + def hi: ILHURegInst; + + // Used in custom lowering constant SFP loads: + def f32: ILHURegInst; +} + +defm ILHU : ImmLoadHalfwordUpper; // Immediate load address (can also be used to load 18-bit unsigned constants, // see the zext 16->32 pattern) -def ILAr64: - RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val), - "ila\t$rT, $val", LoadNOP, - [(set R64C:$rT, imm18:$val)]>; - -// TODO: ILAv2i64 - -def ILAv2i64: - RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>; - -def ILAv4i32: - RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>; - -def ILAr32: - RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set R32C:$rT, imm18:$val)]>; - -def ILAf32: - RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set R32FP:$rT, (SPUFPconstant fpimm18:$val))]>; - -def ILAf64: - RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val), - "ila\t$rT, $val", LoadNOP, - [(set R64FP:$rT, (SPUFPconstant fpimm18:$val))]>; - -def ILAlo: - RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val), - "ila\t$rT, $val", ImmLoad, - [(set R32C:$rT, imm18:$val)]>; - -def ILAlsa: - RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val), - "ila\t$rT, $val", ImmLoad, - [/* no pattern */]>; + +class ILAInst pattern>: + RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val", + LoadNOP, pattern>; + +class ILAVecInst: + ILAInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILARegInst: + ILAInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + +multiclass ImmLoadAddress +{ + def v2i64: ILAVecInst; + def v4i32: ILAVecInst; + + def r64: ILARegInst; + def r32: ILARegInst; + def f32: ILARegInst; + def f64: ILARegInst; + + def hi: ILARegInst; + def lo: ILARegInst; + + def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val), + [(set R32C:$rT, imm18:$val)]>; +} + +defm ILA : ImmLoadAddress; // Immediate OR, Halfword Lower: The "other" part of loading large constants // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...> // Note that these are really two operand instructions, but they're encoded // as three operands with the first two arguments tied-to each other. -def IOHLvec: - RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; - -def IOHLr32: - RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; - -def IOHLf32: - RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; +class IOHLInst pattern>: + RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val", + ImmLoad, pattern>, + RegConstraint<"$rS = $rT">, + NoEncode<"$rS">; + +class IOHLVecInst: + IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val), + [/* no pattern */]>; + +class IOHLRegInst: + IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val), + [/* no pattern */]>; + +multiclass ImmOrHalfwordLower +{ + def v2i64: IOHLVecInst; + def v4i32: IOHLVecInst; + + def r32: IOHLRegInst; + def f32: IOHLRegInst; + + def lo: IOHLRegInst; +} + +defm IOHL: ImmOrHalfwordLower; // Form select mask for bytes using immediate, used in conjunction with the // SELB instruction: -def FSMBIv16i8 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), - "fsmbi\t$rT, $val", SelectOp, - [(set (v16i8 VECREG:$rT), (SPUfsmbi_v16i8 immU16:$val))]>; +class FSMBIVec: + RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), + "fsmbi\t$rT, $val", + SelectOp, + [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>; + +multiclass FormSelectMaskBytesImm +{ + def v16i8: FSMBIVec; + def v8i16: FSMBIVec; + def v4i32: FSMBIVec; + def v2i64: FSMBIVec; +} + +defm FSMBI : FormSelectMaskBytesImm; + +// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits +class FSMBInst pattern>: + RRForm_1<0b01101101100, OOL, IOL, "fsmb\t$rT, $rA", SelectOp, + pattern>; + +class FSMBRegInst: + FSMBInst<(outs VECREG:$rT), (ins rclass:$rA), + [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>; + +class FSMBVecInst: + FSMBInst<(outs VECREG:$rT), (ins VECREG:$rA), + [(set (vectype VECREG:$rT), + (SPUselmask (vectype VECREG:$rA)))]>; + +multiclass FormSelectMaskBits { + def v16i8_r16: FSMBRegInst; + def v16i8: FSMBVecInst; +} + +defm FSMB: FormSelectMaskBits; + +// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is +// only 8-bits wide (even though it's input as 16-bits here) + +class FSMHInst pattern>: + RRForm_1<0b10101101100, OOL, IOL, "fsmh\t$rT, $rA", SelectOp, + pattern>; + +class FSMHRegInst: + FSMHInst<(outs VECREG:$rT), (ins rclass:$rA), + [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>; + +class FSMHVecInst: + FSMHInst<(outs VECREG:$rT), (ins VECREG:$rA), + [(set (vectype VECREG:$rT), + (SPUselmask (vectype VECREG:$rA)))]>; + +multiclass FormSelectMaskHalfword { + def v8i16_r16: FSMHRegInst; + def v8i16: FSMHVecInst; +} + +defm FSMH: FormSelectMaskHalfword; + +// fsm: Form select mask for words. Like the other fsm* instructions, +// only the lower 4 bits of $rA are significant. + +class FSMInst pattern>: + RRForm_1<0b00101101100, OOL, IOL, "fsm\t$rT, $rA", SelectOp, + pattern>; + +class FSMRegInst: + FSMInst<(outs VECREG:$rT), (ins rclass:$rA), + [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>; + +class FSMVecInst: + FSMInst<(outs VECREG:$rT), (ins VECREG:$rA), + [(set (vectype VECREG:$rT), (SPUselmask (vectype VECREG:$rA)))]>; + +multiclass FormSelectMaskWord { + def v4i32: FSMVecInst; -def FSMBIv8i16 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), - "fsmbi\t$rT, $val", SelectOp, - [(set (v8i16 VECREG:$rT), (SPUfsmbi_v8i16 immU16:$val))]>; + def r32 : FSMRegInst; + def r16 : FSMRegInst; +} + +defm FSM : FormSelectMaskWord; + +// Special case when used for i64 math operations +multiclass FormSelectMaskWord64 { + def r32 : FSMRegInst; + def r16 : FSMRegInst; +} -def FSMBIvecv4i32 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), - "fsmbi\t$rT, $val", SelectOp, - [(set (v4i32 VECREG:$rT), (SPUfsmbi_v4i32 immU16:$val))]>; +defm FSM64 : FormSelectMaskWord64; //===----------------------------------------------------------------------===// // Integer and Logical Operations: @@ -637,8 +560,6 @@ def AHv8i16: def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)), (AHv8i16 VECREG:$rA, VECREG:$rB)>; -// [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; - def AHr16: RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), "ah\t$rT, $rA, $rB", IntegerOp, @@ -650,36 +571,67 @@ def AHIvec: [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; -def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "ahi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>; +def AHIr16: + RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + "ahi\t$rT, $rA, $val", IntegerOp, + [(set R16C:$rT, (add R16C:$rA, i16ImmSExt10:$val))]>; + +// v4i32, i32 add instruction: + +class AInst pattern>: + RRForm<0b00000011000, OOL, IOL, + "a\t$rT, $rA, $rB", IntegerOp, + pattern>; + +class AVecInst: + AInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; + +class ARegInst: + AInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (add rclass:$rA, rclass:$rB))]>; + +multiclass AddInstruction { + def v4i32: AVecInst; + def v16i8: AVecInst; + def r32: ARegInst; +} + +defm A : AddInstruction; + +class AIInst pattern>: + RI10Form<0b00111000, OOL, IOL, + "ai\t$rT, $rA, $val", IntegerOp, + pattern>; -def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "a\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; +class AIVecInst: + AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>; -def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)), - (Avec VECREG:$rA, VECREG:$rB)>; +class AIFPVecInst: + AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [/* no pattern */]>; -def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "a\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>; +class AIRegInst: + AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val), + [(set rclass:$rT, (add rclass:$rA, immpred:$val))]>; -def Ar8: - RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "a\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>; +// This is used to add epsilons to floating point numbers in the f32 fdiv code: +class AIFPInst: + AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val), + [/* no pattern */]>; -def AIvec: - RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "ai\t$rT, $rA, $val", IntegerOp, - [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), - v4i32SExt10Imm:$val))]>; +multiclass AddImmediate { + def v4i32: AIVecInst; -def AIr32: - RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), - "ai\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>; + def r32: AIRegInst; + + def v4f32: AIFPVecInst; + def f32: AIFPInst; +} + +defm AI : AddImmediate; def SFHvec: RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), @@ -690,7 +642,7 @@ def SFHvec: def SFHr16: RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), "sfh\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>; + [(set R16C:$rT, (sub R16C:$rB, R16C:$rA))]>; def SFHIvec: RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), @@ -705,11 +657,12 @@ def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), def SFvec : RRForm<0b00000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), "sf\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rB), (v4i32 VECREG:$rA)))]>; + def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), "sf\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>; + [(set R32C:$rT, (sub R32C:$rB, R32C:$rA))]>; def SFIvec: RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), @@ -723,45 +676,118 @@ def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT), [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>; // ADDX: only available in vector form, doesn't match a pattern. -def ADDXvec: - RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "addx\t$rT, $rA, $rB", IntegerOp, - []>, +class ADDXInst pattern>: + RRForm<0b00000010110, OOL, IOL, + "addx\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ADDXVecInst: + ADDXInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry), + [/* no pattern */]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// CG: only available in vector form, doesn't match a pattern. -def CGvec: - RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "cg\t$rT, $rA, $rB", IntegerOp, - []>, +class ADDXRegInst: + ADDXInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB, rclass:$rCarry), + [/* no pattern */]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// SFX: only available in vector form, doesn't match a pattern -def SFXvec: - RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "sfx\t$rT, $rA, $rB", IntegerOp, - []>, +multiclass AddExtended { + def v2i64 : ADDXVecInst; + def v4i32 : ADDXVecInst; + def r64 : ADDXRegInst; + def r32 : ADDXRegInst; +} + +defm ADDX : AddExtended; + +// CG: Generate carry for add +class CGInst pattern>: + RRForm<0b01000011000, OOL, IOL, + "cg\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class CGVecInst: + CGInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB), + [/* no pattern */]>; + +class CGRegInst: + CGInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB), + [/* no pattern */]>; + +multiclass CarryGenerate { + def v2i64 : CGVecInst; + def v4i32 : CGVecInst; + def r64 : CGRegInst; + def r32 : CGRegInst; +} + +defm CG : CarryGenerate; + +// SFX: Subract from, extended. This is used in conjunction with BG to subtract +// with carry (borrow, in this case) +class SFXInst pattern>: + RRForm<0b10000010110, OOL, IOL, + "sfx\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class SFXVecInst: + SFXInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry), + [/* no pattern */]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// BG: only available in vector form, doesn't match a pattern. -def BGvec: - RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "bg\t$rT, $rA, $rB", IntegerOp, - []>, +class SFXRegInst: + SFXInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB, rclass:$rCarry), + [/* no pattern */]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// BGX: only available in vector form, doesn't match a pattern. +multiclass SubtractExtended { + def v2i64 : SFXVecInst; + def v4i32 : SFXVecInst; + def r64 : SFXRegInst; + def r32 : SFXRegInst; +} + +defm SFX : SubtractExtended; + +// BG: only available in vector form, doesn't match a pattern. +class BGInst pattern>: + RRForm<0b01000010000, OOL, IOL, + "bg\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class BGVecInst: + BGInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB), + [/* no pattern */]>; + +class BGRegInst: + BGInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB), + [/* no pattern */]>; + +multiclass BorrowGenerate { + def v4i32 : BGVecInst; + def v2i64 : BGVecInst; + def r64 : BGRegInst; + def r32 : BGRegInst; +} + +defm BG : BorrowGenerate; + +// BGX: Borrow generate, extended. def BGXvec: RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), + VECREG:$rCarry), "bgx\t$rT, $rA, $rB", IntegerOp, []>, RegConstraint<"$rCarry = $rT">, @@ -773,225 +799,303 @@ def BGXvec: def MPYv8i16: RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), "mpy\t$rT, $rA, $rB", IntegerMulDiv, - [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)))]>; + [/* no pattern */]>; def MPYr16: RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), "mpy\t$rT, $rA, $rB", IntegerMulDiv, [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>; +// Unsigned 16-bit multiply: + +class MPYUInst pattern>: + RRForm<0b00110011110, OOL, IOL, + "mpyu\t$rT, $rA, $rB", IntegerMulDiv, + pattern>; + def MPYUv4i32: - RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "mpyu\t$rT, $rA, $rB", IntegerMulDiv, - [(set (v4i32 VECREG:$rT), - (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + MPYUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern */]>; def MPYUr16: - RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB), - "mpyu\t$rT, $rA, $rB", IntegerMulDiv, - [(set R32C:$rT, (mul (zext R16C:$rA), - (zext R16C:$rB)))]>; + MPYUInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R32C:$rT, (mul (zext R16C:$rA), (zext R16C:$rB)))]>; def MPYUr32: - RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyu\t$rT, $rA, $rB", IntegerMulDiv, - [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>; + MPYUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [/* no pattern */]>; -// mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result, -// this only produces the lower 16 bits) -def MPYIvec: - RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), +// mpyi: multiply 16 x s10imm -> 32 result. + +class MPYIInst pattern>: + RI10Form<0b00101110, OOL, IOL, "mpyi\t$rT, $rA, $val", IntegerMulDiv, - [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; + pattern>; + +def MPYIvec: + MPYIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; def MPYIr16: - RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "mpyi\t$rT, $rA, $val", IntegerMulDiv, - [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>; + MPYIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>; // mpyui: same issues as other multiplies, plus, this doesn't match a // pattern... but may be used during target DAG selection or lowering + +class MPYUIInst pattern>: + RI10Form<0b10101110, OOL, IOL, + "mpyui\t$rT, $rA, $val", IntegerMulDiv, + pattern>; + def MPYUIvec: - RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "mpyui\t$rT, $rA, $val", IntegerMulDiv, - []>; + MPYUIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + []>; def MPYUIr16: - RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "mpyui\t$rT, $rA, $val", IntegerMulDiv, - []>; + MPYUIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + []>; // mpya: 16 x 16 + 16 -> 32 bit result -def MPYAvec: - RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv, - [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)))), - (v4i32 VECREG:$rC)))]>; +class MPYAInst pattern>: + RRRForm<0b0011, OOL, IOL, + "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv, + pattern>; + +def MPYAv4i32: + MPYAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (v4i32 VECREG:$rT), + (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))), + (v4i32 VECREG:$rC)))]>; def MPYAr32: - RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC), - "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv, - [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)), - R32C:$rC))]>; - -def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC), - (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>; + MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC), + [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)), + R32C:$rC))]>; + +def MPYAr32_sext: + MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC), + [(set R32C:$rT, (add (mul (sext R16C:$rA), (sext R16C:$rB)), + R32C:$rC))]>; def MPYAr32_sextinreg: - RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC), - "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv, - [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16), - (sext_inreg R32C:$rB, i16)), - R32C:$rC))]>; - -//def MPYAr32: -// RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC), -// "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv, -// [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)), -// R32C:$rC))]>; + MPYAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC), + [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16), + (sext_inreg R32C:$rB, i16)), + R32C:$rC))]>; // mpyh: multiply high, used to synthesize 32-bit multiplies +class MPYHInst pattern>: + RRForm<0b10100011110, OOL, IOL, + "mpyh\t$rT, $rA, $rB", IntegerMulDiv, + pattern>; + def MPYHv4i32: - RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "mpyh\t$rT, $rA, $rB", IntegerMulDiv, - [(set (v4i32 VECREG:$rT), - (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + MPYHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern */]>; def MPYHr32: - RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyh\t$rT, $rA, $rB", IntegerMulDiv, - [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>; + MPYHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [/* no pattern */]>; // mpys: multiply high and shift right (returns the top half of // a 16-bit multiply, sign extended to 32 bits.) -def MPYSvec: - RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + +class MPYSInst: + RRForm<0b11100011110, OOL, IOL, "mpys\t$rT, $rA, $rB", IntegerMulDiv, - []>; + [/* no pattern */]>; +def MPYSv4i32: + MPYSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>; + def MPYSr16: - RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB), - "mpys\t$rT, $rA, $rB", IntegerMulDiv, - []>; + MPYSInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB)>; // mpyhh: multiply high-high (returns the 32-bit result from multiplying // the top 16 bits of the $rA, $rB) + +class MPYHHInst: + RRForm<0b01100011110, OOL, IOL, + "mpyhh\t$rT, $rA, $rB", IntegerMulDiv, + [/* no pattern */]>; + def MPYHHv8i16: - RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "mpyhh\t$rT, $rA, $rB", IntegerMulDiv, - [(set (v8i16 VECREG:$rT), - (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; + MPYHHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>; def MPYHHr32: - RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyhh\t$rT, $rA, $rB", IntegerMulDiv, - []>; + MPYHHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>; // mpyhha: Multiply high-high, add to $rT: -def MPYHHAvec: - RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + +class MPYHHAInst: + RRForm<0b01100010110, OOL, IOL, "mpyhha\t$rT, $rA, $rB", IntegerMulDiv, - []>; + [/* no pattern */]>; +def MPYHHAvec: + MPYHHAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>; + def MPYHHAr32: - RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyhha\t$rT, $rA, $rB", IntegerMulDiv, - []>; + MPYHHAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>; + +// mpyhhu: Multiply high-high, unsigned, e.g.: +// +// +-------+-------+ +-------+-------+ +---------+ +// | a0 . a1 | x | b0 . b1 | = | a0 x b0 | +// +-------+-------+ +-------+-------+ +---------+ +// +// where a0, b0 are the upper 16 bits of the 32-bit word -// mpyhhu: Multiply high-high, unsigned -def MPYHHUvec: - RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), +class MPYHHUInst: + RRForm<0b01110011110, OOL, IOL, "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv, - []>; + [/* no pattern */]>; +def MPYHHUv4i32: + MPYHHUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>; + def MPYHHUr32: - RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv, - []>; + MPYHHUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>; // mpyhhau: Multiply high-high, unsigned -def MPYHHAUvec: - RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + +class MPYHHAUInst: + RRForm<0b01110010110, OOL, IOL, "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv, - []>; + [/* no pattern */]>; +def MPYHHAUvec: + MPYHHAUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>; + def MPYHHAUr32: - RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv, - []>; + MPYHHAUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // clz: Count leading zeroes -def CLZv4i32: - RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA), - "clz\t$rT, $rA", IntegerOp, - [/* intrinsic */]>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +class CLZInst pattern>: + RRForm_1<0b10100101010, OOL, IOL, "clz\t$rT, $rA", + IntegerOp, pattern>; + +class CLZRegInst: + CLZInst<(outs rclass:$rT), (ins rclass:$rA), + [(set rclass:$rT, (ctlz rclass:$rA))]>; + +class CLZVecInst: + CLZInst<(outs VECREG:$rT), (ins VECREG:$rA), + [(set (vectype VECREG:$rT), (ctlz (vectype VECREG:$rA)))]>; + +multiclass CountLeadingZeroes { + def v4i32 : CLZVecInst; + def r32 : CLZRegInst; +} -def CLZr32: - RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA), - "clz\t$rT, $rA", IntegerOp, - [(set R32C:$rT, (ctlz R32C:$rA))]>; +defm CLZ : CountLeadingZeroes; // cntb: Count ones in bytes (aka "population count") +// // NOTE: This instruction is really a vector instruction, but the custom // lowering code uses it in unorthodox ways to support CTPOP for other // data types! + def CNTBv16i8: RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>; + [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>; def CNTBv8i16 : RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>; + [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>; def CNTBv4i32 : RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>; + [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>; -// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits -def FSMB: - RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsmb\t$rT, $rA", SelectOp, - []>; +// gbb: Gather the low order bits from each byte in $rA into a single 16-bit +// quantity stored into $rT's slot 0, upper 16 bits are zeroed, as are +// slots 1-3. +// +// Note: This instruction "pairs" with the fsmb instruction for all of the +// various types defined here. +// +// Note 2: The "VecInst" and "RegInst" forms refer to the result being either +// a vector or register. -// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is -// only 8-bits wide (even though it's input as 16-bits here) -def FSMH: - RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsmh\t$rT, $rA", SelectOp, - []>; +class GBBInst pattern>: + RRForm_1<0b01001101100, OOL, IOL, "gbb\t$rT, $rA", GatherOp, pattern>; -// fsm: Form select mask for words. Like the other fsm* instructions, -// only the lower 4 bits of $rA are significant. -def FSM: - RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsm\t$rT, $rA", SelectOp, - []>; +class GBBRegInst: + GBBInst<(outs rclass:$rT), (ins VECREG:$rA), + [/* no pattern */]>; -// gbb: Gather all low order bits from each byte in $rA into a single 16-bit -// quantity stored into $rT -def GBB: - RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA), - "gbb\t$rT, $rA", GatherOp, - []>; +class GBBVecInst: + GBBInst<(outs VECREG:$rT), (ins VECREG:$rA), + [/* no pattern */]>; + +multiclass GatherBitsFromBytes { + def v16i8_r32: GBBRegInst; + def v16i8_r16: GBBRegInst; + def v16i8: GBBVecInst; +} + +defm GBB: GatherBitsFromBytes; // gbh: Gather all low order bits from each halfword in $rA into a single -// 8-bit quantity stored in $rT -def GBH: - RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA), - "gbh\t$rT, $rA", GatherOp, - []>; +// 8-bit quantity stored in $rT's slot 0, with the upper bits of $rT set to 0 +// and slots 1-3 also set to 0. +// +// See notes for GBBInst, above. + +class GBHInst pattern>: + RRForm_1<0b10001101100, OOL, IOL, "gbh\t$rT, $rA", GatherOp, + pattern>; + +class GBHRegInst: + GBHInst<(outs rclass:$rT), (ins VECREG:$rA), + [/* no pattern */]>; + +class GBHVecInst: + GBHInst<(outs VECREG:$rT), (ins VECREG:$rA), + [/* no pattern */]>; + +multiclass GatherBitsHalfword { + def v8i16_r32: GBHRegInst; + def v8i16_r16: GBHRegInst; + def v8i16: GBHVecInst; +} + +defm GBH: GatherBitsHalfword; // gb: Gather all low order bits from each word in $rA into a single -// 4-bit quantity stored in $rT -def GB: - RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA), - "gb\t$rT, $rA", GatherOp, - []>; +// 4-bit quantity stored in $rT's slot 0, upper bits in $rT set to 0, +// as well as slots 1-3. +// +// See notes for gbb, above. + +class GBInst pattern>: + RRForm_1<0b00001101100, OOL, IOL, "gb\t$rT, $rA", GatherOp, + pattern>; + +class GBRegInst: + GBInst<(outs rclass:$rT), (ins VECREG:$rA), + [/* no pattern */]>; + +class GBVecInst: + GBInst<(outs VECREG:$rT), (ins VECREG:$rA), + [/* no pattern */]>; + +multiclass GatherBitsWord { + def v4i32_r32: GBRegInst; + def v4i32_r16: GBRegInst; + def v4i32: GBVecInst; +} + +defm GB: GatherBitsWord; // avgb: average bytes def AVGB: @@ -1012,497 +1116,501 @@ def SUMB: []>; // Sign extension operations: -def XSBHvec: - RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>; - -// Ordinary form for XSBH -def XSBHr16: - RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>; - -def XSBHr8: - RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R16C:$rDst, (sext R8C:$rSrc))]>; - -// 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit -// quantities to 32-bit quantities via a 32-bit register (see the sext 8->32 -// pattern below). Intentionally doesn't match a pattern because we want the -// sext 8->32 pattern to do the work for us, namely because we need the extra -// XSHWr32. -def XSBHr32: - RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>; - -// Sign extend halfwords to words: -def XSHWvec: - RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc), - "xshw\t$rDest, $rSrc", IntegerOp, - [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>; - -def XSHWr32: - RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc), - "xshw\t$rDst, $rSrc", IntegerOp, - [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>; - -def XSHWr16: - RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc), - "xshw\t$rDst, $rSrc", IntegerOp, - [(set R32C:$rDst, (sext R16C:$rSrc))]>; - -def XSWDvec: - RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc), - "xswd\t$rDst, $rSrc", IntegerOp, - [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>; - -def XSWDr64: - RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc), - "xswd\t$rDst, $rSrc", IntegerOp, - [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>; - -def XSWDr32: - RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc), - "xswd\t$rDst, $rSrc", IntegerOp, - [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>; - -def : Pat<(sext R32C:$inp), - (XSWDr32 R32C:$inp)>; +class XSBHInst pattern>: + RRForm_1<0b01101101010, OOL, IOL, + "xsbh\t$rDst, $rSrc", + IntegerOp, pattern>; + +class XSBHInRegInst pattern>: + XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc), + pattern>; + +multiclass ExtendByteHalfword { + def v16i8: XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), + [ + /*(set (v8i16 VECREG:$rDst), (sext (v8i16 VECREG:$rSrc)))*/]>; + def r8: XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc), + [(set R16C:$rDst, (sext R8C:$rSrc))]>; + def r16: XSBHInRegInst; + + // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit + // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32 + // pattern below). Intentionally doesn't match a pattern because we want the + // sext 8->32 pattern to do the work for us, namely because we need the extra + // XSHWr32. + def r32: XSBHInRegInst; + + // Same as the 32-bit version, but for i64 + def r64: XSBHInRegInst; +} -// AND operations -def ANDv16i8: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB)))]>; - -def ANDv8i16: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)))]>; +defm XSBH : ExtendByteHalfword; -def ANDv4i32: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB)))]>; - -def ANDr32: - RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>; - -//===--------------------------------------------- -// Special instructions to perform the fabs instruction -def ANDfabs32: - RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -def ANDfabs64: - RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -// Could use ANDv4i32, but won't for clarity -def ANDfabsvec: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -//===--------------------------------------------- - -def ANDr16: - RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>; - -def ANDr8: - RRForm<0b10000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>; - -// Hacked form of AND to zero-extend 16-bit quantities to 32-bit -// quantities -- see 16->32 zext pattern. -// -// This pattern is somewhat artificial, since it might match some -// compiler generated pattern but it is unlikely to do so. -def AND2To4: - RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>; - -// N.B.: vnot_conv is one of those special target selection pattern fragments, -// in which we expect there to be a bit_convert on the constant. Bear in mind -// that llvm translates "not " to "xor , -1" (or in this case, a -// constant -1 vector.) -def ANDCv16i8: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA), - (vnot (v16i8 VECREG:$rB))))]>; - -def ANDCv8i16: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA), - (vnot (v8i16 VECREG:$rB))))]>; - -def ANDCv4i32: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA), - (vnot (v4i32 VECREG:$rB))))]>; - -def ANDCr32: - RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>; - -def ANDCr16: - RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>; - -def ANDCr8: - RRForm<0b10000011010, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, (not R8C:$rB)))]>; - -def ANDBIv16i8: - RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "andbi\t$rT, $rA, $val", IntegerOp, - [(set (v16i8 VECREG:$rT), - (and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>; - -def ANDBIr8: - RI10Form<0b01101000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), - "andbi\t$rT, $rA, $val", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>; - -def ANDHIv8i16: - RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set (v8i16 VECREG:$rT), - (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; +// Sign extend halfwords to words: -def ANDHIr16: - RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>; +class XSHWInst pattern>: + RRForm_1<0b01101101010, OOL, IOL, "xshw\t$rDest, $rSrc", + IntegerOp, pattern>; -def ANDHI1To2: - RI10Form<0b10101000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (and (zext R8C:$rA), i16ImmSExt10:$val))]>; +class XSHWVecInst: + XSHWInst<(outs VECREG:$rDest), (ins VECREG:$rSrc), + [(set (out_vectype VECREG:$rDest), + (sext (in_vectype VECREG:$rSrc)))]>; -def ANDIv4i32: - RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set (v4i32 VECREG:$rT), - (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>; - -def ANDIr32: - RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>; - -// Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32 -// pattern below. -def ANDI1To4: - RI10Form<0b10101000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and (zext R8C:$rA), i32ImmSExt10:$val))]>; - -// Hacked form of ANDI to zero-extend i16 quantities to i32. See the -// zext 16->32 pattern below. -// -// Note that this pattern is somewhat artificial, since it might match -// something the compiler generates but is unlikely to occur in practice. -def ANDI2To4: - RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>; +class XSHWInRegInst pattern>: + XSHWInst<(outs rclass:$rDest), (ins rclass:$rSrc), + pattern>; + +class XSHWRegInst: + XSHWInst<(outs rclass:$rDest), (ins R16C:$rSrc), + [(set rclass:$rDest, (sext R16C:$rSrc))]>; -// Bitwise OR group: -// Bitwise "or" (N.B.: These are also register-register copy instructions...) -def ORv16i8: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; - -def ORv8i16: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; - -def ORv4i32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; - -def ORv4f32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v4f32 VECREG:$rT), - (v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>; - -def ORv2f64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v2f64 VECREG:$rT), - (v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>; - -def ORgprc: - RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>; - -def ORr64: - RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>; - -def ORr32: - RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>; - -def ORr16: - RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>; - -def ORr8: - RRForm<0b10000010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>; - -// OR instruction forms that are used to copy f32 and f64 registers. -// They do not match patterns. -def ORf32: - RRForm<0b10000010000, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +multiclass ExtendHalfwordWord { + def v4i32: XSHWVecInst; -def ORf64: - RRForm<0b10000010000, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; + def r16: XSHWRegInst; -// ORv*_*: Used in scalar->vector promotions: -def ORv16i8_i8: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; + def r32: XSHWInRegInst; + def r64: XSHWInRegInst; +} -def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)), - (ORv16i8_i8 R8C:$rA, R8C:$rA)>; +defm XSHW : ExtendHalfwordWord; + +// Sign-extend words to doublewords (32->64 bits) + +class XSWDInst pattern>: + RRForm_1<0b01100101010, OOL, IOL, "xswd\t$rDst, $rSrc", + IntegerOp, pattern>; + +class XSWDVecInst: + XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), + [/*(set (out_vectype VECREG:$rDst), + (sext (out_vectype VECREG:$rSrc)))*/]>; + +class XSWDRegInst: + XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc), + [(set out_rclass:$rDst, (sext in_rclass:$rSrc))]>; + +multiclass ExtendWordToDoubleWord { + def v2i64: XSWDVecInst; + def r64: XSWDRegInst; + + def r64_inreg: XSWDInst<(outs R64C:$rDst), (ins R64C:$rSrc), + [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>; +} -def ORv8i16_i16: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +defm XSWD : ExtendWordToDoubleWord; -def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)), - (ORv8i16_i16 R16C:$rA, R16C:$rA)>; +// AND operations -def ORv4i32_i32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +class ANDInst pattern> : + RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ANDVecInst: + ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; + +class ANDRegInst: + ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>; + +multiclass BitwiseAnd +{ + def v16i8: ANDVecInst; + def v8i16: ANDVecInst; + def v4i32: ANDVecInst; + def v2i64: ANDVecInst; + + def r128: ANDRegInst; + def r64: ANDRegInst; + def r32: ANDRegInst; + def r16: ANDRegInst; + def r8: ANDRegInst; + + //===--------------------------------------------- + // Special instructions to perform the fabs instruction + def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), + [/* Intentionally does not match a pattern */]>; + + def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB), + [/* Intentionally does not match a pattern */]>; + + def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* Intentionally does not match a pattern */]>; + + //===--------------------------------------------- + + // Hacked form of AND to zero-extend 16-bit quantities to 32-bit + // quantities -- see 16->32 zext pattern. + // + // This pattern is somewhat artificial, since it might match some + // compiler generated pattern but it is unlikely to do so. + + def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB), + [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>; +} -def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)), - (ORv4i32_i32 R32C:$rA, R32C:$rA)>; +defm AND : BitwiseAnd; -def ORv2i64_i64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; -def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)), - (ORv2i64_i64 R64C:$rA, R64C:$rA)>; +def vnot_cell_conv : PatFrag<(ops node:$in), + (xor node:$in, (bitconvert (v4i32 immAllOnesV)))>; -def ORv4f32_f32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +// N.B.: vnot_cell_conv is one of those special target selection pattern +// fragments, +// in which we expect there to be a bit_convert on the constant. Bear in mind +// that llvm translates "not " to "xor , -1" (or in this case, a +// constant -1 vector.) -def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)), - (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>; +class ANDCInst pattern>: + RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ANDCVecInst: + ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (and (vectype VECREG:$rA), + (vnot_frag (vectype VECREG:$rB))))]>; + +class ANDCRegInst: + ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>; + +multiclass AndComplement +{ + def v16i8: ANDCVecInst; + def v8i16: ANDCVecInst; + def v4i32: ANDCVecInst; + def v2i64: ANDCVecInst; + + def r128: ANDCRegInst; + def r64: ANDCRegInst; + def r32: ANDCRegInst; + def r16: ANDCRegInst; + def r8: ANDCRegInst; + + // Sometimes, the xor pattern has a bitcast constant: + def v16i8_conv: ANDCVecInst; +} -def ORv2f64_f64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +defm ANDC : AndComplement; -def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)), - (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>; +class ANDBIInst pattern>: + RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val", + ByteOp, pattern>; -// ORi*_v*: Used to extract vector element 0 (the preferred slot) -def ORi8_v16i8: - RRForm<0b10000010000, (outs R8C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +multiclass AndByteImm +{ + def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (v16i8 VECREG:$rT), + (and (v16i8 VECREG:$rA), + (v16i8 v16i8U8Imm:$val)))]>; -def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)), - (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>; + def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), + [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>; +} -def ORi16_v8i16: - RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +defm ANDBI : AndByteImm; -def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)), - (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>; +class ANDHIInst pattern> : + RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val", + ByteOp, pattern>; -def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)), - (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>; +multiclass AndHalfwordImm +{ + def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; -def ORi32_v4i32: - RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; + def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val), + [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>; -def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)), - (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>; + // Zero-extend i8 to i16: + def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val), + [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>; +} -def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)), - (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>; +defm ANDHI : AndHalfwordImm; + +class ANDIInst pattern> : + RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val", + IntegerOp, pattern>; + +multiclass AndWordImm +{ + def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>; + + def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>; + + // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32 + // pattern below. + def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), + [(set R32C:$rT, + (and (zext R8C:$rA), i32ImmSExt10:$val))]>; + + // Hacked form of ANDI to zero-extend i16 quantities to i32. See the + // zext 16->32 pattern below. + // + // Note that this pattern is somewhat artificial, since it might match + // something the compiler generates but is unlikely to occur in practice. + def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), + [(set R32C:$rT, + (and (zext R16C:$rA), i32ImmSExt10:$val))]>; +} -def ORi64_v2i64: - RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +defm ANDI : AndWordImm; -def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)), - (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Bitwise OR group: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ -def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)), - (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>; +// Bitwise "or" (N.B.: These are also register-register copy instructions...) +class ORInst pattern>: + RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ORVecInst: + ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; + +class ORRegInst: + ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>; + + +multiclass BitwiseOr +{ + def v16i8: ORVecInst; + def v8i16: ORVecInst; + def v4i32: ORVecInst; + def v2i64: ORVecInst; + + def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v4f32 VECREG:$rT), + (v4f32 (bitconvert (or (v4i32 VECREG:$rA), + (v4i32 VECREG:$rB)))))]>; + + def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v2f64 VECREG:$rT), + (v2f64 (bitconvert (or (v2i64 VECREG:$rA), + (v2i64 VECREG:$rB)))))]>; + + def r128: ORRegInst; + def r64: ORRegInst; + def r32: ORRegInst; + def r16: ORRegInst; + def r8: ORRegInst; + + // OR instructions used to copy f32 and f64 registers. + def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [/* no pattern */]>; + + def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), + [/* no pattern */]>; +} -def ORf32_v4f32: - RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +defm OR : BitwiseOr; -def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)), - (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>; +//===----------------------------------------------------------------------===// +// SPU::PREFSLOT2VEC and VEC2PREFSLOT re-interpretations of registers +//===----------------------------------------------------------------------===// +def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)), + (COPY_TO_REGCLASS R8C:$rA, VECREG)>; -def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)), - (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>; +def : Pat<(v8i16 (SPUprefslot2vec R16C:$rA)), + (COPY_TO_REGCLASS R16C:$rA, VECREG)>; -def ORf64_v2f64: - RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +def : Pat<(v4i32 (SPUprefslot2vec R32C:$rA)), + (COPY_TO_REGCLASS R32C:$rA, VECREG)>; -def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)), - (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>; +def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)), + (COPY_TO_REGCLASS R64C:$rA, VECREG)>; -def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)), - (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>; +def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)), + (COPY_TO_REGCLASS R32FP:$rA, VECREG)>; -// ORC: Bitwise "or" with complement (match before ORvec, ORr32) -def ORCv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), - (vnot (v16i8 VECREG:$rB))))]>; +def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)), + (COPY_TO_REGCLASS R64FP:$rA, VECREG)>; + +def : Pat<(i8 (SPUvec2prefslot (v16i8 VECREG:$rA))), + (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>; + +def : Pat<(i16 (SPUvec2prefslot (v8i16 VECREG:$rA))), + (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>; + +def : Pat<(i32 (SPUvec2prefslot (v4i32 VECREG:$rA))), + (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>; + +def : Pat<(i64 (SPUvec2prefslot (v2i64 VECREG:$rA))), + (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>; + +def : Pat<(f32 (SPUvec2prefslot (v4f32 VECREG:$rA))), + (COPY_TO_REGCLASS (v4f32 VECREG:$rA), R32FP)>; + +def : Pat<(f64 (SPUvec2prefslot (v2f64 VECREG:$rA))), + (COPY_TO_REGCLASS (v2f64 VECREG:$rA), R64FP)>; + +// Load Register: This is an assembler alias for a bitwise OR of a register +// against itself. It's here because it brings some clarity to assembly +// language output. + +let hasCtrlDep = 1 in { + class LRInst + : SPUInstr { + bits<7> RA; + bits<7> RT; + + let Pattern = [/*no pattern*/]; + + let Inst{0-10} = 0b10000010000; /* It's an OR operation */ + let Inst{11-17} = RA; + let Inst{18-24} = RA; + let Inst{25-31} = RT; + } + + class LRVecInst: + LRInst<(outs VECREG:$rT), (ins VECREG:$rA)>; + + class LRRegInst: + LRInst<(outs rclass:$rT), (ins rclass:$rA)>; + + multiclass LoadRegister { + def v2i64: LRVecInst; + def v2f64: LRVecInst; + def v4i32: LRVecInst; + def v4f32: LRVecInst; + def v8i16: LRVecInst; + def v16i8: LRVecInst; + + def r128: LRRegInst; + def r64: LRRegInst; + def f64: LRRegInst; + def r32: LRRegInst; + def f32: LRRegInst; + def r16: LRRegInst; + def r8: LRRegInst; + } + + defm LR: LoadRegister; +} -def ORCv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), - (vnot (v8i16 VECREG:$rB))))]>; +// ORC: Bitwise "or" with complement (c = a | ~b) + +class ORCInst pattern>: + RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ORCVecInst: + ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + (vnot (vectype VECREG:$rB))))]>; + +class ORCRegInst: + ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>; + +multiclass BitwiseOrComplement +{ + def v16i8: ORCVecInst; + def v8i16: ORCVecInst; + def v4i32: ORCVecInst; + def v2i64: ORCVecInst; + + def r128: ORCRegInst; + def r64: ORCRegInst; + def r32: ORCRegInst; + def r16: ORCRegInst; + def r8: ORCRegInst; +} -def ORCv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), - (vnot (v4i32 VECREG:$rB))))]>; +defm ORC : BitwiseOrComplement; -def ORCr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>; +// OR byte immediate +class ORBIInst pattern>: + RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val", + IntegerOp, pattern>; -def ORCr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>; +class ORBIVecInst: + ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA), + (vectype immpred:$val)))]>; -def ORCr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, (not R8C:$rB)))]>; +multiclass BitwiseOrByteImm +{ + def v16i8: ORBIVecInst; -// OR byte immediate -def ORBIv16i8: - RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "orbi\t$rT, $rA, $val", IntegerOp, - [(set (v16i8 VECREG:$rT), - (or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>; + def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), + [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>; +} -def ORBIr8: - RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), - "orbi\t$rT, $rA, $val", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>; +defm ORBI : BitwiseOrByteImm; // OR halfword immediate -def ORHIv8i16: - RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), - v8i16Uns10Imm:$val))]>; +class ORHIInst pattern>: + RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val", + IntegerOp, pattern>; + +class ORHIVecInst: + ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + immpred:$val))]>; + +multiclass BitwiseOrHalfwordImm +{ + def v8i16: ORHIVecInst; + + def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val), + [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>; + + // Specialized ORHI form used to promote 8-bit registers to 16-bit + def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val), + [(set R16C:$rT, (or (anyext R8C:$rA), + i16ImmSExt10:$val))]>; +} + +defm ORHI : BitwiseOrHalfwordImm; -def ORHIr16: - RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, u10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>; +class ORIInst pattern>: + RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val", + IntegerOp, pattern>; -// Hacked form of ORHI used to promote 8-bit registers to 16-bit -def ORHI1To2: - RI10Form<0b10100000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (or (anyext R8C:$rA), i16ImmSExt10:$val))]>; +class ORIVecInst: + ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + immpred:$val))]>; // Bitwise "or" with immediate -def ORIv4i32: - RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), - v4i32Uns10Imm:$val))]>; - -def ORIr32: - RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>; - -def ORIr64: - RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [/* no pattern */]>; +multiclass BitwiseOrImm +{ + def v4i32: ORIVecInst; + + def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val), + [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>; + + // i16i32: hacked version of the ori instruction to extend 16-bit quantities + // to 32-bit quantities. used exclusively to match "anyext" conversions (vide + // infra "anyext 16->32" pattern.) + def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (or (anyext R16C:$rA), + i32ImmSExt10:$val))]>; + + // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities + // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide + // infra "anyext 16->32" pattern.) + def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (or (anyext R8C:$rA), + i32ImmSExt10:$val))]>; +} -// ORI2To4: hacked version of the ori instruction to extend 16-bit quantities -// to 32-bit quantities. used exclusively to match "anyext" conversions (vide -// infra "anyext 16->32" pattern.) -def ORI2To4: - RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>; - -// ORI1To4: Hacked version of the ORI instruction to extend 16-bit quantities -// to 32-bit quantities. Used exclusively to match "anyext" conversions (vide -// infra "anyext 16->32" pattern.) -def ORI1To4: - RI10Form<0b00100000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (or (anyext R8C:$rA), i32ImmSExt10:$val))]>; +defm ORI : BitwiseOrImm; // ORX: "or" across the vector: or's $rA's word slots leaving the result in // $rT[0], slots 1-3 are zeroed. @@ -1514,74 +1622,68 @@ def ORXv4i32: []>; // XOR: -def XORv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; -def XORv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; +class XORInst pattern> : + RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB", + IntegerOp, pattern>; -def XORv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; +class XORVecInst: + XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; -def XORr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>; +class XORRegInst: + XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>; -//==---------------------------------------------------------- -// Special forms for floating point instructions. -// Bitwise ORs and ANDs don't make sense for normal floating -// point numbers. These operations (fneg and fabs), however, -// require bitwise logical ops to manipulate the sign bit. -def XORfneg32: - RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg32 */]>; - -// KLUDGY! Better way to do this without a VECREG? bitconvert? -// VECREG is assumed to contain two identical 64-bit masks, so -// it doesn't matter which word we select for the xor -def XORfneg64: - RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg64 */]>; - -// Could use XORv4i32, but will use this for clarity -def XORfnegvec: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg{32,64} */]>; +multiclass BitwiseExclusiveOr +{ + def v16i8: XORVecInst; + def v8i16: XORVecInst; + def v4i32: XORVecInst; + def v2i64: XORVecInst; + + def r128: XORRegInst; + def r64: XORRegInst; + def r32: XORRegInst; + def r16: XORRegInst; + def r8: XORRegInst; + + // XOR instructions used to negate f32 and f64 quantities. + + def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), + [/* no pattern */]>; + + def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB), + [/* no pattern */]>; + + def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern, see fneg{32,64} */]>; +} + +defm XOR : BitwiseExclusiveOr; //==---------------------------------------------------------- -def XORr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>; +class XORBIInst pattern>: + RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val", + IntegerOp, pattern>; -def XORr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>; +multiclass XorByteImm +{ + def v16i8: + XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>; -def XORBIv16i8: - RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "xorbi\t$rT, $rA, $val", IntegerOp, - [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>; + def r8: + XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), + [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>; +} -def XORBIr8: - RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), - "xorbi\t$rT, $rA, $val", IntegerOp, - [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>; +defm XORBI : XorByteImm; def XORHIv8i16: - RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), "xorhi\t$rT, $rA, $val", IntegerOp, [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; @@ -1592,7 +1694,7 @@ def XORHIr16: [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>; def XORIv4i32: - RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val), "xori\t$rT, $rA, $val", IntegerOp, [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>; @@ -1603,721 +1705,615 @@ def XORIr32: [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>; // NAND: -def NANDv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB))))]>; - -def NANDv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB))))]>; - -def NANDv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB))))]>; -def NANDr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>; - -def NANDr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>; +class NANDInst pattern>: + RRForm<0b10010011000, OOL, IOL, "nand\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class NANDVecInst: + NANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (vnot (and (vectype VECREG:$rA), + (vectype VECREG:$rB))))]>; +class NANDRegInst: + NANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (not (and rclass:$rA, rclass:$rB)))]>; + +multiclass BitwiseNand +{ + def v16i8: NANDVecInst; + def v8i16: NANDVecInst; + def v4i32: NANDVecInst; + def v2i64: NANDVecInst; + + def r128: NANDRegInst; + def r64: NANDRegInst; + def r32: NANDRegInst; + def r16: NANDRegInst; + def r8: NANDRegInst; +} -def NANDr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "nand\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>; +defm NAND : BitwiseNand; // NOR: -def NORv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB))))]>; - -def NORv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB))))]>; - -def NORv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB))))]>; - -def NORr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>; - -def NORr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>; - -def NORr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "nor\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>; - -// EQV: Equivalence (1 for each same bit, otherwise 0) -def EQVv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB)), - (and (vnot (v16i8 VECREG:$rA)), - (vnot (v16i8 VECREG:$rB)))))]>; - -def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def EQVv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)), - (and (vnot (v8i16 VECREG:$rA)), - (vnot (v8i16 VECREG:$rB)))))]>; - -def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def EQVv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB)), - (and (vnot (v4i32 VECREG:$rA)), - (vnot (v4i32 VECREG:$rB)))))]>; - -def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def EQVr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or (and R32C:$rA, R32C:$rB), - (and (not R32C:$rA), (not R32C:$rB))))]>; - -def : Pat<(xor R32C:$rA, (not R32C:$rB)), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def : Pat<(xor (not R32C:$rA), R32C:$rB), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def EQVr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or (and R16C:$rA, R16C:$rB), - (and (not R16C:$rA), (not R16C:$rB))))]>; - -def : Pat<(xor R16C:$rA, (not R16C:$rB)), - (EQVr16 R16C:$rA, R16C:$rB)>; - -def : Pat<(xor (not R16C:$rA), R16C:$rB), - (EQVr16 R16C:$rA, R16C:$rB)>; - -def EQVr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or (and R8C:$rA, R8C:$rB), - (and (not R8C:$rA), (not R8C:$rB))))]>; - -def : Pat<(xor R8C:$rA, (not R8C:$rB)), - (EQVr8 R8C:$rA, R8C:$rB)>; -def : Pat<(xor (not R8C:$rA), R8C:$rB), - (EQVr8 R8C:$rA, R8C:$rB)>; - -// gcc optimizes (p & q) | (~p & ~q) -> ~(p | q) | (p & q), so match that -// pattern also: -def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))), - (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))), - (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))), - (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)), - (EQVr16 R16C:$rA, R16C:$rB)>; +class NORInst pattern>: + RRForm<0b10010010000, OOL, IOL, "nor\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class NORVecInst: + NORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (vnot (or (vectype VECREG:$rA), + (vectype VECREG:$rB))))]>; +class NORRegInst: + NORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (not (or rclass:$rA, rclass:$rB)))]>; + +multiclass BitwiseNor +{ + def v16i8: NORVecInst; + def v8i16: NORVecInst; + def v4i32: NORVecInst; + def v2i64: NORVecInst; + + def r128: NORRegInst; + def r64: NORRegInst; + def r32: NORRegInst; + def r16: NORRegInst; + def r8: NORRegInst; +} -def : Pat<(or (not (or R8C:$rA, R8C:$rB)), (and R8C:$rA, R8C:$rB)), - (EQVr8 R8C:$rA, R8C:$rB)>; +defm NOR : BitwiseNor; // Select bits: -def SELBv16i8: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v16i8 VECREG:$rT), - (SPUselb_v16i8 (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), - (v16i8 VECREG:$rC)))]>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBv8i16: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v8i16 VECREG:$rT), - (SPUselb_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), - (v8i16 VECREG:$rC)))]>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBv4i32: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v4i32 VECREG:$rT), - (SPUselb_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), - (v4i32 VECREG:$rC)))]>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBr32: - RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; - -// And the various patterns that can be matched... (all 8 of them :-) -def : Pat<(or (and R32C:$rA, R32C:$rC), - (and R32C:$rB, (not R32C:$rC))), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rC, R32C:$rA), - (and R32C:$rB, (not R32C:$rC))), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rA, R32C:$rC), - (and (not R32C:$rC), R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rC, R32C:$rA), - (and (not R32C:$rC), R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; +class SELBInst pattern>: + RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC", + IntegerOp, pattern>; + +class SELBVecInst: + SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)), + (and (vnot_frag (vectype VECREG:$rC)), + (vectype VECREG:$rA))))]>; + +class SELBVecVCondInst: + SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (vectype VECREG:$rT), + (select (vectype VECREG:$rC), + (vectype VECREG:$rB), + (vectype VECREG:$rA)))]>; + +class SELBVecCondInst: + SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, R32C:$rC), + [(set (vectype VECREG:$rT), + (select R32C:$rC, + (vectype VECREG:$rB), + (vectype VECREG:$rA)))]>; + +class SELBRegInst: + SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC), + [(set rclass:$rT, + (or (and rclass:$rB, rclass:$rC), + (and rclass:$rA, (not rclass:$rC))))]>; + +class SELBRegCondInst: + SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rcond:$rC), + [(set rclass:$rT, + (select rcond:$rC, rclass:$rB, rclass:$rA))]>; + +multiclass SelectBits +{ + def v16i8: SELBVecInst; + def v8i16: SELBVecInst; + def v4i32: SELBVecInst; + def v2i64: SELBVecInst; + + def r128: SELBRegInst; + def r64: SELBRegInst; + def r32: SELBRegInst; + def r16: SELBRegInst; + def r8: SELBRegInst; + + def v16i8_cond: SELBVecCondInst; + def v8i16_cond: SELBVecCondInst; + def v4i32_cond: SELBVecCondInst; + def v2i64_cond: SELBVecCondInst; + + def v16i8_vcond: SELBVecCondInst; + def v8i16_vcond: SELBVecCondInst; + def v4i32_vcond: SELBVecCondInst; + def v2i64_vcond: SELBVecCondInst; + + def v4f32_cond: + SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (v4f32 VECREG:$rT), + (select (v4i32 VECREG:$rC), + (v4f32 VECREG:$rB), + (v4f32 VECREG:$rA)))]>; + + // SELBr64_cond is defined in SPU64InstrInfo.td + def r32_cond: SELBRegCondInst; + def f32_cond: SELBRegCondInst; + def r16_cond: SELBRegCondInst; + def r8_cond: SELBRegCondInst; +} -def : Pat<(or (and R32C:$rA, (not R32C:$rC)), - (and R32C:$rB, R32C:$rC)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; +defm SELB : SelectBits; -def : Pat<(or (and R32C:$rA, (not R32C:$rC)), - (and R32C:$rC, R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; +class SPUselbPatVec: + Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)), + (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>; -def : Pat<(or (and (not R32C:$rC), R32C:$rA), - (and R32C:$rB, R32C:$rC)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; +def : SPUselbPatVec; +def : SPUselbPatVec; +def : SPUselbPatVec; +def : SPUselbPatVec; -def : Pat<(or (and (not R32C:$rC), R32C:$rA), - (and R32C:$rC, R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; +class SPUselbPatReg: + Pat<(SPUselb rclass:$rA, rclass:$rB, rclass:$rC), + (inst rclass:$rA, rclass:$rB, rclass:$rC)>; -def SELBr16: - RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; +def : SPUselbPatReg; +def : SPUselbPatReg; +def : SPUselbPatReg; +def : SPUselbPatReg; -def : Pat<(or (and R16C:$rA, R16C:$rC), - (and R16C:$rB, (not R16C:$rC))), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rC, R16C:$rA), - (and R16C:$rB, (not R16C:$rC))), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +// EQV: Equivalence (1 for each same bit, otherwise 0) +// +// Note: There are a lot of ways to match this bit operator and these patterns +// attempt to be as exhaustive as possible. + +class EQVInst pattern>: + RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class EQVVecInst: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)), + (and (vnot (vectype VECREG:$rA)), + (vnot (vectype VECREG:$rB)))))]>; + +class EQVRegInst: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB), + (and (not rclass:$rA), (not rclass:$rB))))]>; + +class EQVVecPattern1: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>; + +class EQVRegPattern1: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>; + +class EQVVecPattern2: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)), + (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>; + +class EQVRegPattern2: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, + (or (and rclass:$rA, rclass:$rB), + (not (or rclass:$rA, rclass:$rB))))]>; + +class EQVVecPattern3: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>; + +class EQVRegPattern3: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>; + +multiclass BitEquivalence +{ + def v16i8: EQVVecInst; + def v8i16: EQVVecInst; + def v4i32: EQVVecInst; + def v2i64: EQVVecInst; + + def v16i8_1: EQVVecPattern1; + def v8i16_1: EQVVecPattern1; + def v4i32_1: EQVVecPattern1; + def v2i64_1: EQVVecPattern1; + + def v16i8_2: EQVVecPattern2; + def v8i16_2: EQVVecPattern2; + def v4i32_2: EQVVecPattern2; + def v2i64_2: EQVVecPattern2; + + def v16i8_3: EQVVecPattern3; + def v8i16_3: EQVVecPattern3; + def v4i32_3: EQVVecPattern3; + def v2i64_3: EQVVecPattern3; + + def r128: EQVRegInst; + def r64: EQVRegInst; + def r32: EQVRegInst; + def r16: EQVRegInst; + def r8: EQVRegInst; + + def r128_1: EQVRegPattern1; + def r64_1: EQVRegPattern1; + def r32_1: EQVRegPattern1; + def r16_1: EQVRegPattern1; + def r8_1: EQVRegPattern1; + + def r128_2: EQVRegPattern2; + def r64_2: EQVRegPattern2; + def r32_2: EQVRegPattern2; + def r16_2: EQVRegPattern2; + def r8_2: EQVRegPattern2; + + def r128_3: EQVRegPattern3; + def r64_3: EQVRegPattern3; + def r32_3: EQVRegPattern3; + def r16_3: EQVRegPattern3; + def r8_3: EQVRegPattern3; +} -def : Pat<(or (and R16C:$rA, R16C:$rC), - (and (not R16C:$rC), R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +defm EQV: BitEquivalence; -def : Pat<(or (and R16C:$rC, R16C:$rA), - (and (not R16C:$rC), R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +//===----------------------------------------------------------------------===// +// Vector shuffle... +//===----------------------------------------------------------------------===// +// SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB. +// See the SPUshuffle SDNode operand above, which sets up the DAG pattern +// matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with +// the SPUISD::SHUFB opcode. +//===----------------------------------------------------------------------===// -def : Pat<(or (and R16C:$rA, (not R16C:$rC)), - (and R16C:$rB, R16C:$rC)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +class SHUFBInst pattern>: + RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC", + ShuffleOp, pattern>; + +class SHUFBVecInst: + SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (resultvec VECREG:$rT), + (SPUshuffle (resultvec VECREG:$rA), + (resultvec VECREG:$rB), + (maskvec VECREG:$rC)))]>; + +class SHUFBGPRCInst: + SHUFBInst<(outs VECREG:$rT), (ins GPRC:$rA, GPRC:$rB, VECREG:$rC), + [/* no pattern */]>; + +multiclass ShuffleBytes +{ + def v16i8 : SHUFBVecInst; + def v16i8_m32 : SHUFBVecInst; + def v8i16 : SHUFBVecInst; + def v8i16_m32 : SHUFBVecInst; + def v4i32 : SHUFBVecInst; + def v4i32_m32 : SHUFBVecInst; + def v2i64 : SHUFBVecInst; + def v2i64_m32 : SHUFBVecInst; + + def v4f32 : SHUFBVecInst; + def v4f32_m32 : SHUFBVecInst; + + def v2f64 : SHUFBVecInst; + def v2f64_m32 : SHUFBVecInst; + + def gprc : SHUFBGPRCInst; +} -def : Pat<(or (and R16C:$rA, (not R16C:$rC)), - (and R16C:$rC, R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +defm SHUFB : ShuffleBytes; -def : Pat<(or (and (not R16C:$rC), R16C:$rA), - (and R16C:$rB, R16C:$rC)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; +//===----------------------------------------------------------------------===// +// Shift and rotate group: +//===----------------------------------------------------------------------===// -def : Pat<(or (and (not R16C:$rC), R16C:$rA), - (and R16C:$rC, R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def SELBr8: - RRRForm<0b1000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB, R8C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; +class SHLHInst pattern>: + RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB", + RotShiftVec, pattern>; + +class SHLHVecInst: + SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB), + [(set (vectype VECREG:$rT), + (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>; + +multiclass ShiftLeftHalfword +{ + def v8i16: SHLHVecInst; + def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>; + def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB), + [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>; +} -def : Pat<(or (and R8C:$rA, R8C:$rC), - (and R8C:$rB, (not R8C:$rC))), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +defm SHLH : ShiftLeftHalfword; -def : Pat<(or (and R8C:$rC, R8C:$rA), - (and R8C:$rB, (not R8C:$rC))), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +//===----------------------------------------------------------------------===// -def : Pat<(or (and R8C:$rA, R8C:$rC), - (and (not R8C:$rC), R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +class SHLHIInst pattern>: + RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val", + RotShiftVec, pattern>; -def : Pat<(or (and R8C:$rC, R8C:$rA), - (and (not R8C:$rC), R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +class SHLHIVecInst: + SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), + [(set (vectype VECREG:$rT), + (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>; -def : Pat<(or (and R8C:$rA, (not R8C:$rC)), - (and R8C:$rB, R8C:$rC)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +multiclass ShiftLeftHalfwordImm +{ + def v8i16: SHLHIVecInst; + def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val), + [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>; +} -def : Pat<(or (and R8C:$rA, (not R8C:$rC)), - (and R8C:$rC, R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +defm SHLHI : ShiftLeftHalfwordImm; -def : Pat<(or (and (not R8C:$rC), R8C:$rA), - (and R8C:$rB, R8C:$rC)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)), + (SHLHIv8i16 VECREG:$rA, (TO_IMM16 uimm7:$val))>; -def : Pat<(or (and (not R8C:$rC), R8C:$rA), - (and R8C:$rC, R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +def : Pat<(shl R16C:$rA, (i32 uimm7:$val)), + (SHLHIr16 R16C:$rA, (TO_IMM16 uimm7:$val))>; //===----------------------------------------------------------------------===// -// Vector shuffle... -//===----------------------------------------------------------------------===// -def SHUFB: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "shufb\t$rT, $rA, $rB, $rC", IntegerOp, - [/* no pattern */]>; +class SHLInst pattern>: + RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB", + RotShiftVec, pattern>; + +multiclass ShiftLeftWord +{ + def v4i32: + SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB), + [(set (v4i32 VECREG:$rT), + (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>; + def r32: + SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>; +} -// SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB. -// See the SPUshuffle SDNode operand above, which sets up the DAG pattern -// matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with -// the SPUISD::SHUFB opcode. -def : Pat<(SPUshuffle (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +defm SHL: ShiftLeftWord; -def : Pat<(SPUshuffle (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +//===----------------------------------------------------------------------===// -def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +class SHLIInst pattern>: + RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val", + RotShiftVec, pattern>; -def : Pat<(SPUshuffle (v4f32 VECREG:$rA), (v4f32 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +multiclass ShiftLeftWordImm +{ + def v4i32: + SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val), + [(set (v4i32 VECREG:$rT), + (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>; -def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; + def r32: + SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val), + [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>; +} -def : Pat<(SPUshuffle (v2f64 VECREG:$rA), (v2f64 VECREG:$rB), VECREG:$rC), - (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +defm SHLI : ShiftLeftWordImm; //===----------------------------------------------------------------------===// -// Shift and rotate group: -//===----------------------------------------------------------------------===// - -def SHLHv8i16: - RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB), - "shlh\t$rT, $rA, $rB", RotateShift, - [(set (v8i16 VECREG:$rT), - (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), R16C:$rB))]>; - -// $rB gets promoted to 32-bit register type when confronted with -// this llvm assembly code: +// SHLQBI vec form: Note that this will shift the entire vector (the 128-bit +// register) to the left. Vector form is here to ensure type correctness. // -// define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) { -// %A = shl i16 %arg1, %arg2 -// ret i16 %A -// } +// The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift +// of 7 bits is actually possible. // -// However, we will generate this code when lowering 8-bit shifts and rotates. - -def SHLHr16: - RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "shlh\t$rT, $rA, $rB", RotateShift, - [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>; - -def SHLHr16_r32: - RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB), - "shlh\t$rT, $rA, $rB", RotateShift, - [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>; - -def SHLHIv8i16: - RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val), - "shlhi\t$rT, $rA, $val", RotateShift, - [(set (v8i16 VECREG:$rT), - (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)))]>; - -def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)), - (SHLHIv8i16 VECREG:$rA, imm:$val)>; +// Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI +// to shift i64 and i128. SHLQBI is the residual left over after shifting by +// bytes with SHLQBY. + +class SHLQBIInst pattern>: + RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class SHLQBIVecInst: + SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [(set (vectype VECREG:$rT), + (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>; + +class SHLQBIRegInst: + SHLQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [/* no pattern */]>; + +multiclass ShiftLeftQuadByBits +{ + def v16i8: SHLQBIVecInst; + def v8i16: SHLQBIVecInst; + def v4i32: SHLQBIVecInst; + def v4f32: SHLQBIVecInst; + def v2i64: SHLQBIVecInst; + def v2f64: SHLQBIVecInst; + + def r128: SHLQBIRegInst; +} -def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)), - (SHLHIv8i16 VECREG:$rA, imm:$val)>; +defm SHLQBI : ShiftLeftQuadByBits; + +// See note above on SHLQBI. In this case, the predicate actually does then +// enforcement, whereas with SHLQBI, we have to "take it on faith." +class SHLQBIIInst pattern>: + RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class SHLQBIIVecInst: + SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val), + [(set (vectype VECREG:$rT), + (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>; + +multiclass ShiftLeftQuadByBitsImm +{ + def v16i8 : SHLQBIIVecInst; + def v8i16 : SHLQBIIVecInst; + def v4i32 : SHLQBIIVecInst; + def v4f32 : SHLQBIIVecInst; + def v2i64 : SHLQBIIVecInst; + def v2f64 : SHLQBIIVecInst; +} -def SHLHIr16: - RI7Form<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val), - "shlhi\t$rT, $rA, $val", RotateShift, - [(set R16C:$rT, (shl R16C:$rA, (i32 uimm7:$val)))]>; - -def : Pat<(shl R16C:$rA, (i8 uimm7:$val)), - (SHLHIr16 R16C:$rA, uimm7:$val)>; +defm SHLQBII : ShiftLeftQuadByBitsImm; -def : Pat<(shl R16C:$rA, (i16 uimm7:$val)), - (SHLHIr16 R16C:$rA, uimm7:$val)>; +// SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes, +// not by bits. See notes above on SHLQBI. + +class SHLQBYInst pattern>: + RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class SHLQBYVecInst: + SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [(set (vectype VECREG:$rT), + (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>; + +multiclass ShiftLeftQuadBytes +{ + def v16i8: SHLQBYVecInst; + def v8i16: SHLQBYVecInst; + def v4i32: SHLQBYVecInst; + def v4f32: SHLQBYVecInst; + def v2i64: SHLQBYVecInst; + def v2f64: SHLQBYVecInst; + def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB), + [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>; +} -def SHLv4i32: - RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB), - "shl\t$rT, $rA, $rB", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), R16C:$rB))]>; +defm SHLQBY: ShiftLeftQuadBytes; + +class SHLQBYIInst pattern>: + RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class SHLQBYIVecInst: + SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val), + [(set (vectype VECREG:$rT), + (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>; + +multiclass ShiftLeftQuadBytesImm +{ + def v16i8: SHLQBYIVecInst; + def v8i16: SHLQBYIVecInst; + def v4i32: SHLQBYIVecInst; + def v4f32: SHLQBYIVecInst; + def v2i64: SHLQBYIVecInst; + def v2f64: SHLQBYIVecInst; + def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val), + [(set GPRC:$rT, + (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>; +} -def SHLr32: - RRForm<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "shl\t$rT, $rA, $rB", RotateShift, - [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>; +defm SHLQBYI : ShiftLeftQuadBytesImm; -def SHLIv4i32: - RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val), - "shli\t$rT, $rA, $val", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)))]>; +class SHLQBYBIInst pattern>: + RRForm<0b00111001111, OOL, IOL, "shlqbybi\t$rT, $rA, $rB", + RotShiftQuad, pattern>; -def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)), - (SHLIv4i32 VECREG:$rA, uimm7:$val)>; +class SHLQBYBIVecInst: + SHLQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* no pattern */]>; -def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)), - (SHLIv4i32 VECREG:$rA, uimm7:$val)>; +class SHLQBYBIRegInst: + SHLQBYBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [/* no pattern */]>; -def SHLIr32: - RI7Form<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val), - "shli\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>; +multiclass ShiftLeftQuadBytesBitCount +{ + def v16i8: SHLQBYBIVecInst; + def v8i16: SHLQBYBIVecInst; + def v4i32: SHLQBYBIVecInst; + def v4f32: SHLQBYBIVecInst; + def v2i64: SHLQBYBIVecInst; + def v2f64: SHLQBYBIVecInst; -def : Pat<(shl R32C:$rA, (i16 uimm7:$val)), - (SHLIr32 R32C:$rA, uimm7:$val)>; + def r128: SHLQBYBIRegInst; +} -def : Pat<(shl R32C:$rA, (i8 uimm7:$val)), - (SHLIr32 R32C:$rA, uimm7:$val)>; +defm SHLQBYBI : ShiftLeftQuadBytesBitCount; -// SHLQBI vec form: Note that this will shift the entire vector (the 128-bit -// register) to the left. Vector form is here to ensure type correctness. -def SHLQBIvec: - RRForm<0b11011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "shlqbi\t$rT, $rA, $rB", RotateShift, - [/* intrinsic */]>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate halfword: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +class ROTHInst pattern>: + RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB", + RotShiftVec, pattern>; -// See note above on SHLQBI. -def SHLQBIIvec: - RI7Form<0b11011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - "shlqbii\t$rT, $rA, $val", RotateShift, - [/* intrinsic */]>; +class ROTHVecInst: + ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (SPUvec_rotl VECREG:$rA, (v8i16 VECREG:$rB)))]>; -// SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes, -// not by bits. -def SHLQBYvec: - RI7Form<0b11111011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "shlqbyi\t$rT, $rA, $rB", RotateShift, - [/* intrinsic */]>; - -def SHLQBYIvec: - RI7Form<0b11111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - "shlqbyi\t$rT, $rA, $val", RotateShift, - [/* intrinsic */]>; - -// ROTH v8i16 form: -def ROTHv8i16: - RRForm<0b00111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "roth\t$rT, $rA, $rB", RotateShift, - [(set (v8i16 VECREG:$rT), - (SPUvec_rotl_v8i16 VECREG:$rA, VECREG:$rB))]>; +class ROTHRegInst: + ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>; -def ROTHr16: - RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "roth\t$rT, $rA, $rB", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, R16C:$rB))]>; +multiclass RotateLeftHalfword +{ + def v8i16: ROTHVecInst; + def r16: ROTHRegInst; +} -def ROTHr16_r32: - RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB), - "roth\t$rT, $rA, $rB", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>; +defm ROTH: RotateLeftHalfword; + +def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB), + [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate halfword, immediate: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +class ROTHIInst pattern>: + RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val", + RotShiftVec, pattern>; + +class ROTHIVecInst: + ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), + [(set (vectype VECREG:$rT), + (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>; + +multiclass RotateLeftHalfwordImm +{ + def v8i16: ROTHIVecInst; + def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val), + [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>; + def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val), + [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>; +} -// The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or -// 32-bit register -def ROTHr16_r8: - RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R8C:$rB), - "roth\t$rT, $rA, $rB", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, (i32 (zext R8C:$rB))))]>; +defm ROTHI: RotateLeftHalfwordImm; -def : Pat<(rotl R16C:$rA, (i32 (sext R8C:$rB))), - (ROTHr16_r8 R16C:$rA, R8C:$rB)>; +def : Pat<(SPUvec_rotl (v8i16 VECREG:$rA), (i32 uimm7:$val)), + (ROTHIv8i16 VECREG:$rA, (TO_IMM16 imm:$val))>; -def : Pat<(rotl R16C:$rA, (i32 (zext R8C:$rB))), - (ROTHr16_r8 R16C:$rA, R8C:$rB)>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate word: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ -def : Pat<(rotl R16C:$rA, (i32 (anyext R8C:$rB))), - (ROTHr16_r8 R16C:$rA, R8C:$rB)>; +class ROTInst pattern>: + RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB", + RotShiftVec, pattern>; -def ROTHIv8i16: - RI7Form<0b00111110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val), - "rothi\t$rT, $rA, $val", RotateShift, - [(set (v8i16 VECREG:$rT), - (SPUvec_rotl_v8i16 VECREG:$rA, (i8 uimm7:$val)))]>; +class ROTVecInst: + ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [(set (vectype VECREG:$rT), + (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>; -def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)), - (ROTHIv8i16 VECREG:$rA, imm:$val)>; +class ROTRegInst: + ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [(set rclass:$rT, + (rotl rclass:$rA, R32C:$rB))]>; -def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i32 uimm7:$val)), - (ROTHIv8i16 VECREG:$rA, imm:$val)>; - -def ROTHIr16: - RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm:$val), - "rothi\t$rT, $rA, $val", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>; - -def ROTHIr16_i32: - RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val), - "rothi\t$rT, $rA, $val", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>; - -def ROTHIr16_i8: - RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i8:$val), - "rothi\t$rT, $rA, $val", RotateShift, - [(set R16C:$rT, (rotl R16C:$rA, (i8 uimm7:$val)))]>; - -def ROTv4i32: - RRForm<0b00011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rot\t$rT, $rA, $rB", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), R32C:$rB))]>; +multiclass RotateLeftWord +{ + def v4i32: ROTVecInst; + def r32: ROTRegInst; +} -def ROTr32: - RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "rot\t$rT, $rA, $rB", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, R32C:$rB))]>; +defm ROT: RotateLeftWord; // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or // 32-bit register def ROTr32_r16_anyext: - RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R16C:$rB), - "rot\t$rT, $rA, $rB", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>; + ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB), + [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>; def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))), (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>; @@ -2326,9 +2322,8 @@ def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))), (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>; def ROTr32_r8_anyext: - RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R8C:$rB), - "rot\t$rT, $rA, $rB", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>; + ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB), + [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>; def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))), (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>; @@ -2336,103 +2331,207 @@ def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))), def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))), (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>; -def ROTIv4i32: - RI7Form<0b00011110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val), - "roti\t$rT, $rA, $val", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>; - -def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)), - (ROTIv4i32 VECREG:$rA, imm:$val)>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate word, immediate +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ -def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)), - (ROTIv4i32 VECREG:$rA, imm:$val)>; +class ROTIInst pattern>: + RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val", + RotShiftVec, pattern>; -def ROTIr32: - RI7Form<0b00011110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val), - "roti\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, (i32 uimm7:$val)))]>; +class ROTIVecInst: + ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val), + [(set (vectype VECREG:$rT), + (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>; -def ROTIr32_i16: - RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm:$val), - "roti\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, (i16 uimm7:$val)))]>; +class ROTIRegInst: + ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val), + [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>; -def ROTIr32_i8: - RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i8:$val), - "roti\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (rotl R32C:$rA, (i8 uimm7:$val)))]>; +multiclass RotateLeftWordImm +{ + def v4i32: ROTIVecInst; + def v4i32_i16: ROTIVecInst; + def v4i32_i8: ROTIVecInst; -// ROTQBY* vector forms: This rotates the entire vector, but vector registers -// are used here for type checking (instances where ROTQBI is used actually -// use vector registers) -def ROTQBYvec: - RRForm<0b00111011100, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB), - "rotqby\t$rT, $rA, $rB", RotateShift, - [(set (v16i8 VECREG:$rT), (SPUrotbytes_left (v16i8 VECREG:$rA), R16C:$rB))]>; + def r32: ROTIRegInst; + def r32_i16: ROTIRegInst; + def r32_i8: ROTIRegInst; +} -def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R16C:$rB), - (ROTQBYvec VECREG:$rA, R16C:$rB)>; +defm ROTI : RotateLeftWordImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate quad by byte (count) +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQBYInst pattern>: + RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class ROTQBYGenInst: + ROTQBYInst<(outs rc:$rT), (ins rc:$rA, R32C:$rB), + [(set (type rc:$rT), + (SPUrotbytes_left (type rc:$rA), R32C:$rB))]>; + +class ROTQBYVecInst: + ROTQBYGenInst; + +multiclass RotateQuadLeftByBytes +{ + def v16i8: ROTQBYVecInst; + def v8i16: ROTQBYVecInst; + def v4i32: ROTQBYVecInst; + def v4f32: ROTQBYVecInst; + def v2i64: ROTQBYVecInst; + def v2f64: ROTQBYVecInst; + def i128: ROTQBYGenInst; +} -// See ROTQBY note above. -def ROTQBYIvec: - RI7Form<0b00111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - "rotqbyi\t$rT, $rA, $val", RotateShift, - [(set (v16i8 VECREG:$rT), - (SPUrotbytes_left (v16i8 VECREG:$rA), (i16 uimm7:$val)))]>; +defm ROTQBY: RotateQuadLeftByBytes; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate quad by byte (count), immediate +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQBYIInst pattern>: + RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class ROTQBYIGenInst: + ROTQBYIInst<(outs rclass:$rT), (ins rclass:$rA, u7imm:$val), + [(set (type rclass:$rT), + (SPUrotbytes_left (type rclass:$rA), (i16 uimm7:$val)))]>; + +class ROTQBYIVecInst: + ROTQBYIGenInst; + +multiclass RotateQuadByBytesImm +{ + def v16i8: ROTQBYIVecInst; + def v8i16: ROTQBYIVecInst; + def v4i32: ROTQBYIVecInst; + def v4f32: ROTQBYIVecInst; + def v2i64: ROTQBYIVecInst; + def vfi64: ROTQBYIVecInst; + def i128: ROTQBYIGenInst; +} -def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)), - (ROTQBYIvec VECREG:$rA, uimm7:$val)>; +defm ROTQBYI: RotateQuadByBytesImm; // See ROTQBY note above. -def ROTQBYBIvec: - RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - "rotqbybi\t$rT, $rA, $val", RotateShift, - [/* intrinsic */]>; +class ROTQBYBIInst pattern>: + RI7Form<0b00110011100, OOL, IOL, + "rotqbybi\t$rT, $rA, $shift", + RotShiftQuad, pattern>; + +class ROTQBYBIVecInst: + ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift), + [(set (vectype VECREG:$rT), + (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>; + +multiclass RotateQuadByBytesByBitshift { + def v16i8_r32: ROTQBYBIVecInst; + def v8i16_r32: ROTQBYBIVecInst; + def v4i32_r32: ROTQBYBIVecInst; + def v2i64_r32: ROTQBYBIVecInst; +} + +defm ROTQBYBI : RotateQuadByBytesByBitshift; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // See ROTQBY note above. // // Assume that the user of this instruction knows to shift the rotate count // into bit 29 -def ROTQBIvec: - RRForm<0b00011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "rotqbi\t$rT, $rA, $rB", RotateShift, - [/* insert intrinsic here */]>; +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ -// See ROTQBY note above. -def ROTQBIIvec: - RI7Form<0b00011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val), - "rotqbii\t$rT, $rA, $val", RotateShift, - [/* insert intrinsic here */]>; +class ROTQBIInst pattern>: + RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class ROTQBIVecInst: + ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* no pattern yet */]>; +class ROTQBIRegInst: + ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [/* no pattern yet */]>; + +multiclass RotateQuadByBitCount +{ + def v16i8: ROTQBIVecInst; + def v8i16: ROTQBIVecInst; + def v4i32: ROTQBIVecInst; + def v2i64: ROTQBIVecInst; + + def r128: ROTQBIRegInst; + def r64: ROTQBIRegInst; +} + +defm ROTQBI: RotateQuadByBitCount; + +class ROTQBIIInst pattern>: + RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class ROTQBIIVecInst: + ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val), + [/* no pattern yet */]>; + +class ROTQBIIRegInst: + ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val), + [/* no pattern yet */]>; + +multiclass RotateQuadByBitCountImm +{ + def v16i8: ROTQBIIVecInst; + def v8i16: ROTQBIIVecInst; + def v4i32: ROTQBIIVecInst; + def v2i64: ROTQBIIVecInst; + + def r128: ROTQBIIRegInst; + def r64: ROTQBIIRegInst; +} + +defm ROTQBII : RotateQuadByBitCountImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // ROTHM v8i16 form: // NOTE(1): No vector rotate is generated by the C/C++ frontend (today), // so this only matches a synthetically generated/lowered code // fragment. // NOTE(2): $rB must be negated before the right rotate! +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTHMInst pattern>: + RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB", + RotShiftVec, pattern>; + def ROTHMv8i16: - RRForm<0b10111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rothm\t$rT, $rA, $rB", RotateShift, - [/* see patterns below - $rB must be negated */]>; + ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R32C:$rB), +def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB), (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R16C:$rB), +def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB), (ROTHMv8i16 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R8C:$rB), +def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB), (ROTHMv8i16 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>; // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left // Note: This instruction doesn't match a pattern because rB must be negated // for the instruction to work. Thus, the pattern below the instruction! + def ROTHMr16: - RRForm<0b10111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB), - "rothm\t$rT, $rA, $rB", RotateShift, - [/* see patterns below - $rB must be negated! */]>; + ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB), + [/* see patterns below - $rB must be negated! */]>; def : Pat<(srl R16C:$rA, R32C:$rB), (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>; @@ -2448,50 +2547,60 @@ def : Pat<(srl R16C:$rA, R8C:$rB), // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is // that the immediate can be complemented, so that the user doesn't have to // worry about it. + +class ROTHMIInst pattern>: + RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val", + RotShiftVec, pattern>; + def ROTHMIv8i16: - RI7Form<0b10111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val), - "rothmi\t$rT, $rA, $val", RotateShift, - [(set (v8i16 VECREG:$rT), - (SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i32 imm:$val)))]>; + ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val), + [/* no pattern */]>; -def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i16 imm:$val)), - (ROTHMIv8i16 VECREG:$rA, imm:$val)>; - -def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i8 imm:$val)), - (ROTHMIv8i16 VECREG:$rA, imm:$val)>; +def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)), + (ROTHMIv8i16 VECREG:$rA, imm:$val)>; + +def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)), + (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>; + +def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)), + (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>; def ROTHMIr16: - RI7Form<0b10111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val), - "rothmi\t$rT, $rA, $val", RotateShift, - [(set R16C:$rT, (srl R16C:$rA, (i32 uimm7:$val)))]>; + ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val), + [/* no pattern */]>; -def: Pat<(srl R16C:$rA, (i16 uimm7:$val)), +def: Pat<(srl R16C:$rA, (i32 uimm7:$val)), (ROTHMIr16 R16C:$rA, uimm7:$val)>; +def: Pat<(srl R16C:$rA, (i16 uimm7:$val)), + (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; + def: Pat<(srl R16C:$rA, (i8 uimm7:$val)), - (ROTHMIr16 R16C:$rA, uimm7:$val)>; + (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; // ROTM v4i32 form: See the ROTHM v8i16 comments. +class ROTMInst pattern>: + RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB", + RotShiftVec, pattern>; + def ROTMv4i32: - RRForm<0b10011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rotm\t$rT, $rA, $rB", RotateShift, - [/* see patterns below - $rB must be negated */]>; + ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R32C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB), (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R16C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB), (ROTMv4i32 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, /* R8C */ R16C:$rB), +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB), (ROTMv4i32 VECREG:$rA, - (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /*)*/, 0))>; + (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; def ROTMr32: - RRForm<0b10011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "rotm\t$rT, $rA, $rB", RotateShift, - [/* see patterns below - $rB must be negated */]>; + ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [/* see patterns below - $rB must be negated */]>; def : Pat<(srl R32C:$rA, R32C:$rB), (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>; @@ -2507,80 +2616,210 @@ def : Pat<(srl R32C:$rA, R8C:$rB), // ROTMI v4i32 form: See the comment for ROTHM v8i16. def ROTMIv4i32: RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), - "rotmi\t$rT, $rA, $val", RotateShift, + "rotmi\t$rT, $rA, $val", RotShiftVec, [(set (v4i32 VECREG:$rT), - (SPUvec_srl_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>; + (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>; -def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i16 uimm7:$val)), - (ROTMIv4i32 VECREG:$rA, uimm7:$val)>; - -def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i8 uimm7:$val)), - (ROTMIv4i32 VECREG:$rA, uimm7:$val)>; +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i16 uimm7:$val)), + (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>; + +def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i8 uimm7:$val)), + (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>; // ROTMI r32 form: know how to complement the immediate value. def ROTMIr32: RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val), - "rotmi\t$rT, $rA, $val", RotateShift, + "rotmi\t$rT, $rA, $val", RotShiftVec, [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>; def : Pat<(srl R32C:$rA, (i16 imm:$val)), - (ROTMIr32 R32C:$rA, uimm7:$val)>; + (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>; def : Pat<(srl R32C:$rA, (i8 imm:$val)), - (ROTMIr32 R32C:$rA, uimm7:$val)>; + (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>; -// ROTQMBYvec: This is a vector form merely so that when used in an +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// ROTQMBY: This is a vector form merely so that when used in an // instruction pattern, type checking will succeed. This instruction assumes -// that the user knew to complement $rB. -def ROTQMBYvec: - RRForm<0b10111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rotqmby\t$rT, $rA, $rB", RotateShift, - [(set (v16i8 VECREG:$rT), - (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), R32C:$rB))]>; - -def ROTQMBYIvec: - RI7Form<0b10111111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), - "rotqmbyi\t$rT, $rA, $val", RotateShift, - [(set (v16i8 VECREG:$rT), - (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), (i32 uimm7:$val)))]>; - -def : Pat<(SPUrotbytes_right_zfill VECREG:$rA, (i16 uimm7:$val)), - (ROTQMBYIvec VECREG:$rA, uimm7:$val)>; - -def ROTQMBYBIvec: - RRForm<0b10110011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "rotqmbybi\t$rT, $rA, $rB", RotateShift, - [/* intrinsic */]>; - -def ROTQMBIvec: - RRForm<0b10011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "rotqmbi\t$rT, $rA, $rB", RotateShift, - [/* intrinsic */]>; - -def ROTQMBIIvec: - RI7Form<0b10011111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), - "rotqmbii\t$rT, $rA, $val", RotateShift, - [/* intrinsic */]>; +// that the user knew to negate $rB. +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQMBYInst pattern>: + RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class ROTQMBYVecInst: + ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* no pattern, $rB must be negated */]>; + +class ROTQMBYRegInst: + ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [/* no pattern */]>; + +multiclass RotateQuadBytes +{ + def v16i8: ROTQMBYVecInst; + def v8i16: ROTQMBYVecInst; + def v4i32: ROTQMBYVecInst; + def v2i64: ROTQMBYVecInst; + + def r128: ROTQMBYRegInst; + def r64: ROTQMBYRegInst; +} + +defm ROTQMBY : RotateQuadBytes; + +def : Pat<(SPUsrl_bytes GPRC:$rA, R32C:$rB), + (ROTQMBYr128 GPRC:$rA, + (SFIr32 R32C:$rB, 0))>; + +class ROTQMBYIInst pattern>: + RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class ROTQMBYIVecInst: + ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), + [/* no pattern */]>; + +class ROTQMBYIRegInst: + ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val), + [/* no pattern */]>; + +// 128-bit zero extension form: +class ROTQMBYIZExtInst: + ROTQMBYIInst<(outs GPRC:$rT), (ins rclass:$rA, optype:$val), + [/* no pattern */]>; + +multiclass RotateQuadBytesImm +{ + def v16i8: ROTQMBYIVecInst; + def v8i16: ROTQMBYIVecInst; + def v4i32: ROTQMBYIVecInst; + def v2i64: ROTQMBYIVecInst; + + def r128: ROTQMBYIRegInst; + def r64: ROTQMBYIRegInst; + + def r128_zext_r8: ROTQMBYIZExtInst; + def r128_zext_r16: ROTQMBYIZExtInst; + def r128_zext_r32: ROTQMBYIZExtInst; + def r128_zext_r64: ROTQMBYIZExtInst; +} + +defm ROTQMBYI : RotateQuadBytesImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate right and mask by bit count +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQMBYBIInst pattern>: + RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class ROTQMBYBIVecInst: + ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* no pattern, */]>; + +multiclass RotateMaskQuadByBitCount +{ + def v16i8: ROTQMBYBIVecInst; + def v8i16: ROTQMBYBIVecInst; + def v4i32: ROTQMBYBIVecInst; + def v2i64: ROTQMBYBIVecInst; + def r128: ROTQMBYBIInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB), + [/*no pattern*/]>; +} + +defm ROTQMBYBI: RotateMaskQuadByBitCount; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate quad and mask by bits +// Note that the rotate amount has to be negated +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQMBIInst pattern>: + RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB", + RotShiftQuad, pattern>; + +class ROTQMBIVecInst: + ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), + [/* no pattern */]>; + +class ROTQMBIRegInst: + ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB), + [/* no pattern */]>; + +multiclass RotateMaskQuadByBits +{ + def v16i8: ROTQMBIVecInst; + def v8i16: ROTQMBIVecInst; + def v4i32: ROTQMBIVecInst; + def v2i64: ROTQMBIVecInst; + + def r128: ROTQMBIRegInst; + def r64: ROTQMBIRegInst; +} + +defm ROTQMBI: RotateMaskQuadByBits; + +def : Pat<(srl GPRC:$rA, R32C:$rB), + (ROTQMBYBIr128 (ROTQMBIr128 GPRC:$rA, + (SFIr32 R32C:$rB, 0)), + (SFIr32 R32C:$rB, 0))>; + + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Rotate quad and mask by bits, immediate +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class ROTQMBIIInst pattern>: + RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val", + RotShiftQuad, pattern>; + +class ROTQMBIIVecInst: + ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), + [/* no pattern */]>; + +class ROTQMBIIRegInst: + ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val), + [/* no pattern */]>; + +multiclass RotateMaskQuadByBitsImm +{ + def v16i8: ROTQMBIIVecInst; + def v8i16: ROTQMBIIVecInst; + def v4i32: ROTQMBIIVecInst; + def v2i64: ROTQMBIIVecInst; + + def r128: ROTQMBIIRegInst; + def r64: ROTQMBIIRegInst; +} + +defm ROTQMBII: RotateMaskQuadByBitsImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ def ROTMAHv8i16: RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rotmah\t$rT, $rA, $rB", RotateShift, + "rotmah\t$rT, $rA, $rB", RotShiftVec, [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R32C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R16C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R8C:$rB), +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB), (ROTMAHv8i16 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; def ROTMAHr16: RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB), - "rotmah\t$rT, $rA, $rB", RotateShift, + "rotmah\t$rT, $rA, $rB", RotShiftVec, [/* see patterns below - $rB must be negated */]>; def : Pat<(sra R16C:$rA, R32C:$rB), @@ -2596,46 +2835,46 @@ def : Pat<(sra R16C:$rA, R8C:$rB), def ROTMAHIv8i16: RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val), - "rotmahi\t$rT, $rA, $val", RotateShift, + "rotmahi\t$rT, $rA, $val", RotShiftVec, [(set (v8i16 VECREG:$rT), - (SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>; + (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>; -def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)), - (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>; +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)), + (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>; -def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)), - (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>; +def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)), + (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>; def ROTMAHIr16: RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val), - "rotmahi\t$rT, $rA, $val", RotateShift, + "rotmahi\t$rT, $rA, $val", RotShiftVec, [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>; def : Pat<(sra R16C:$rA, (i32 imm:$val)), - (ROTMAHIr16 R16C:$rA, uimm7:$val)>; + (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; def : Pat<(sra R16C:$rA, (i8 imm:$val)), - (ROTMAHIr16 R16C:$rA, uimm7:$val)>; + (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>; def ROTMAv4i32: RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - "rotma\t$rT, $rA, $rB", RotateShift, + "rotma\t$rT, $rA, $rB", RotShiftVec, [/* see patterns below - $rB must be negated */]>; -def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R32C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>; +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>; -def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R16C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 (XSHWr16 R16C:$rB), 0))>; -def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R8C:$rB), - (ROTMAv4i32 (v4i32 VECREG:$rA), +def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB), + (ROTMAv4i32 VECREG:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; def ROTMAr32: RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "rotma\t$rT, $rA, $rB", RotateShift, + "rotma\t$rT, $rA, $rB", RotShiftVec, [/* see patterns below - $rB must be negated */]>; def : Pat<(sra R32C:$rA, R32C:$rB), @@ -2649,25 +2888,28 @@ def : Pat<(sra R32C:$rA, R8C:$rB), (ROTMAr32 R32C:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; -def ROTMAIv4i32: - RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), - "rotmai\t$rT, $rA, $val", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_sra_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>; - -def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, (i16 uimm7:$val)), - (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>; - -def ROTMAIr32: - RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val), - "rotmai\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>; - -def : Pat<(sra R32C:$rA, (i16 uimm7:$val)), - (ROTMAIr32 R32C:$rA, uimm7:$val)>; +class ROTMAIInst pattern>: + RRForm<0b01011110000, OOL, IOL, + "rotmai\t$rT, $rA, $val", + RotShiftVec, pattern>; + +class ROTMAIVecInst: + ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val), + [(set (vectype VECREG:$rT), + (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>; + +class ROTMAIRegInst: + ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val), + [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>; + +multiclass RotateMaskAlgebraicImm { + def v2i64_i32 : ROTMAIVecInst; + def v4i32_i32 : ROTMAIVecInst; + def r64_i32 : ROTMAIRegInst; + def r32_i32 : ROTMAIRegInst; +} -def : Pat<(sra R32C:$rA, (i8 uimm7:$val)), - (ROTMAIr32 R32C:$rA, uimm7:$val)>; +defm ROTMAI : RotateMaskAlgebraicImm; //===----------------------------------------------------------------------===// // Branch and conditionals: @@ -2685,89 +2927,514 @@ let isTerminator = 1, isBarrier = 1 in { "heqi\t$rA, $val", BranchResolv, [/* no pattern to match */]>; - // HGT/HGTI: These instructions use signed arithmetic for the comparison, - // contrasting with HLGT/HLGTI, which use unsigned comparison: - def HGTr32: - RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB), - "hgt\t$rA, $rB", BranchResolv, - [/* no pattern to match */]>; + // HGT/HGTI: These instructions use signed arithmetic for the comparison, + // contrasting with HLGT/HLGTI, which use unsigned comparison: + def HGTr32: + RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB), + "hgt\t$rA, $rB", BranchResolv, + [/* no pattern to match */]>; + + def HGTIr32: + RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val), + "hgti\t$rA, $val", BranchResolv, + [/* no pattern to match */]>; + + def HLGTr32: + RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB), + "hlgt\t$rA, $rB", BranchResolv, + [/* no pattern to match */]>; + + def HLGTIr32: + RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val), + "hlgti\t$rA, $val", BranchResolv, + [/* no pattern to match */]>; +} + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// Comparison operators for i8, i16 and i32: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class CEQBInst pattern> : + RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpEqualByte +{ + def v16i8 : + CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r8 : + CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), + [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>; +} + +class CEQBIInst pattern> : + RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpEqualByteImm +{ + def v16i8 : + CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val), + [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA), + v16i8SExt8Imm:$val))]>; + def r8: + CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val), + [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>; +} + +class CEQHInst pattern> : + RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpEqualHalfword +{ + def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>; +} + +class CEQHIInst pattern> : + RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpEqualHalfwordImm +{ + def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (seteq (v8i16 VECREG:$rA), + (v8i16 v8i16SExt10Imm:$val)))]>; + def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>; +} + +class CEQInst pattern> : + RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpEqualWord +{ + def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v4i32 VECREG:$rT), + (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + + def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>; +} + +class CEQIInst pattern> : + RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpEqualWordImm +{ + def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (seteq (v4i32 VECREG:$rA), + (v4i32 v4i32SExt16Imm:$val)))]>; + + def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>; +} + +class CGTBInst pattern> : + RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpGtrByte +{ + def v16i8 : + CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r8 : + CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), + [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>; +} + +class CGTBIInst pattern> : + RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpGtrByteImm +{ + def v16i8 : + CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val), + [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA), + v16i8SExt8Imm:$val))]>; + def r8: + CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val), + [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>; +} + +class CGTHInst pattern> : + RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpGtrHalfword +{ + def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>; +} + +class CGTHIInst pattern> : + RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpGtrHalfwordImm +{ + def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (setgt (v8i16 VECREG:$rA), + (v8i16 v8i16SExt10Imm:$val)))]>; + def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>; +} + +class CGTInst pattern> : + RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpGtrWord +{ + def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v4i32 VECREG:$rT), + (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + + def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>; +} + +class CGTIInst pattern> : + RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpGtrWordImm +{ + def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (setgt (v4i32 VECREG:$rA), + (v4i32 v4i32SExt16Imm:$val)))]>; + + def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>; + + // CGTIv4f32, CGTIf32: These are used in the f32 fdiv instruction sequence: + def v4f32: CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (setgt (v4i32 (bitconvert (v4f32 VECREG:$rA))), + (v4i32 v4i32SExt16Imm:$val)))]>; + + def f32: CGTIInst<(outs R32C:$rT), (ins R32FP:$rA, s10imm_i32:$val), + [/* no pattern */]>; +} + +class CLGTBInst pattern> : + RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpLGtrByte +{ + def v16i8 : + CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r8 : + CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), + [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>; +} + +class CLGTBIInst pattern> : + RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpLGtrByteImm +{ + def v16i8 : + CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val), + [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA), + v16i8SExt8Imm:$val))]>; + def r8: + CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val), + [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>; +} + +class CLGTHInst pattern> : + RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpLGtrHalfword +{ + def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]>; + + def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>; +} + +class CLGTHIInst pattern> : + RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val", + ByteOp, pattern>; + +multiclass CmpLGtrHalfwordImm +{ + def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (setugt (v8i16 VECREG:$rA), + (v8i16 v8i16SExt10Imm:$val)))]>; + def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>; +} + +class CLGTInst pattern> : + RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB", + ByteOp, pattern>; + +multiclass CmpLGtrWord +{ + def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v4i32 VECREG:$rT), + (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + + def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>; +} - def HGTIr32: - RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val), - "hgti\t$rA, $val", BranchResolv, - [/* no pattern to match */]>; +class CLGTIInst pattern> : + RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val", + ByteOp, pattern>; - def HLGTr32: - RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB), - "hlgt\t$rA, $rB", BranchResolv, - [/* no pattern to match */]>; +multiclass CmpLGtrWordImm +{ + def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (setugt (v4i32 VECREG:$rA), + (v4i32 v4i32SExt16Imm:$val)))]>; - def HLGTIr32: - RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val), - "hlgti\t$rA, $val", BranchResolv, - [/* no pattern to match */]>; + def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>; } -// Comparison operators: -def CEQBr8: - RRForm<0b00001011110, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "ceqb\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match */]>; - -def CEQBv16i8: - RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "ceqb\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQBIr8: - RI10Form<0b01111110, (outs R8C:$rT), (ins R8C:$rA, s7imm:$val), - "ceqbi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQBIv16i8: - RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, s7imm:$val), - "ceqbi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQHr16: - RRForm<0b00010011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "ceqh\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match */]>; - -def CEQHv8i16: - RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "ceqh\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQHIr16: - RI10Form<0b10111110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "ceqhi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQHIv8i16: - RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "ceqhi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQr32: - RRForm<0b00000011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "ceq\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQv4i32: - RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "ceq\t$rT, $rA, $rB", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQIr32: - RI10Form<0b00111110, (outs R32C:$rT), (ins R32C:$rA, s10imm:$val), - "ceqi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; - -def CEQIv4i32: - RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "ceqi\t$rT, $rA, $val", ByteOp, - [/* no pattern to match: intrinsic */]>; +defm CEQB : CmpEqualByte; +defm CEQBI : CmpEqualByteImm; +defm CEQH : CmpEqualHalfword; +defm CEQHI : CmpEqualHalfwordImm; +defm CEQ : CmpEqualWord; +defm CEQI : CmpEqualWordImm; +defm CGTB : CmpGtrByte; +defm CGTBI : CmpGtrByteImm; +defm CGTH : CmpGtrHalfword; +defm CGTHI : CmpGtrHalfwordImm; +defm CGT : CmpGtrWord; +defm CGTI : CmpGtrWordImm; +defm CLGTB : CmpLGtrByte; +defm CLGTBI : CmpLGtrByteImm; +defm CLGTH : CmpLGtrHalfword; +defm CLGTHI : CmpLGtrHalfwordImm; +defm CLGT : CmpLGtrWord; +defm CLGTI : CmpLGtrWordImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// For SETCC primitives not supported above (setlt, setle, setge, etc.) +// define a pattern to generate the right code, as a binary operator +// (in a manner of speaking.) +// +// Notes: +// 1. This only matches the setcc set of conditionals. Special pattern +// matching is used for select conditionals. +// +// 2. The "DAG" versions of these classes is almost exclusively used for +// i64 comparisons. See the tblgen fundamentals documentation for what +// ".ResultInstrs[0]" means; see TargetSelectionDAG.td and the Pattern +// class for where ResultInstrs originates. +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class SETCCNegCondReg: + Pat<(cond rclass:$rA, rclass:$rB), + (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>; + +class SETCCNegCondImm: + Pat<(cond rclass:$rA, (inttype immpred:$imm)), + (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>; + +def : SETCCNegCondReg; +def : SETCCNegCondImm; + +def : SETCCNegCondReg; +def : SETCCNegCondImm; + +def : SETCCNegCondReg; +def : SETCCNegCondImm; + +class SETCCBinOpReg: + Pat<(cond rclass:$rA, rclass:$rB), + (binop (cmpOp1 rclass:$rA, rclass:$rB), + (cmpOp2 rclass:$rA, rclass:$rB))>; + +class SETCCBinOpImm: + Pat<(cond rclass:$rA, (immtype immpred:$imm)), + (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)), + (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setle R8C:$rA, R8C:$rB), + (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>; +def : Pat<(setle R8C:$rA, immU8:$imm), + (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setle R16C:$rA, R16C:$rB), + (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>; +def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm), + (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setle R32C:$rA, R32C:$rB), + (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>; +def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm), + (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setule R8C:$rA, R8C:$rB), + (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>; +def : Pat<(setule R8C:$rA, immU8:$imm), + (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setule R16C:$rA, R16C:$rB), + (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>; +def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm), + (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>; + +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : SETCCBinOpReg; +def : SETCCBinOpImm; +def : Pat<(setule R32C:$rA, R32C:$rB), + (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>; +def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm), + (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +// select conditional patterns: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +class SELECTNegCondReg: + Pat<(select (inttype (cond rclass:$rA, rclass:$rB)), + rclass:$rTrue, rclass:$rFalse), + (selinstr rclass:$rTrue, rclass:$rFalse, + (cmpare rclass:$rA, rclass:$rB))>; + +class SELECTNegCondImm: + Pat<(select (inttype (cond rclass:$rA, immpred:$imm)), + rclass:$rTrue, rclass:$rFalse), + (selinstr rclass:$rTrue, rclass:$rFalse, + (cmpare rclass:$rA, immpred:$imm))>; + +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; + +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; + +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; +def : SELECTNegCondReg; +def : SELECTNegCondImm; + +class SELECTBinOpReg: + Pat<(select (inttype (cond rclass:$rA, rclass:$rB)), + rclass:$rTrue, rclass:$rFalse), + (selinstr rclass:$rFalse, rclass:$rTrue, + (binop (cmpOp1 rclass:$rA, rclass:$rB), + (cmpOp2 rclass:$rA, rclass:$rB)))>; + +class SELECTBinOpImm: + Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))), + rclass:$rTrue, rclass:$rFalse), + (selinstr rclass:$rFalse, rclass:$rTrue, + (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)), + (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +def : SELECTBinOpReg; +def : SELECTBinOpImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ let isCall = 1, // All calls clobber the non-callee-saved registers: @@ -2793,7 +3460,7 @@ let isCall = 1, def BRASL: BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops), "brasl\t$$lr, $func", - [(SPUcall tglobaladdr:$func)]>; + [(SPUcall (SPUaform tglobaladdr:$func, 0))]>; // Branch indirect and set link if external data. These instructions are not // actually generated, matched by an intrinsic: @@ -2808,68 +3475,264 @@ let isCall = 1, BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>; } +// Support calls to external symbols: +def : Pat<(SPUcall (SPUpcrel texternalsym:$func, 0)), + (BRSL texternalsym:$func)>; + +def : Pat<(SPUcall (SPUaform texternalsym:$func, 0)), + (BRASL texternalsym:$func)>; + // Unconditional branches: -let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { - def BR : - UncondBranch<0b001001100, (outs), (ins brtarget:$dest), - "br\t$dest", - [(br bb:$dest)]>; - - // Unconditional, absolute address branch - def BRA: - UncondBranch<0b001100000, (outs), (ins brtarget:$dest), - "bra\t$dest", - [/* no pattern */]>; +let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { + let isBarrier = 1 in { + def BR : + UncondBranch<0b001001100, (outs), (ins brtarget:$dest), + "br\t$dest", + [(br bb:$dest)]>; + + // Unconditional, absolute address branch + def BRA: + UncondBranch<0b001100000, (outs), (ins brtarget:$dest), + "bra\t$dest", + [/* no pattern */]>; + + // Indirect branch + def BI: + BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>; + } - // Indirect branch - def BI: - BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>; - - // Various branches: - def BRNZ: - RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest), - "brnz\t$rCond,$dest", - BranchResolv, - [(brcond R32C:$rCond, bb:$dest)]>; - - def BRZ: - RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest), - "brz\t$rT,$dest", - BranchResolv, - [/* no pattern */]>; + // Conditional branches: + class BRNZInst pattern>: + RI16Form<0b010000100, (outs), IOL, "brnz\t$rCond,$dest", + BranchResolv, pattern>; - def BRHNZ: - RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest), - "brhnz\t$rCond,$dest", - BranchResolv, - [(brcond R16C:$rCond, bb:$dest)]>; + class BRNZRegInst: + BRNZInst<(ins rclass:$rCond, brtarget:$dest), + [(brcond rclass:$rCond, bb:$dest)]>; - def BRHZ: - RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest), - "brhz\t$rT,$dest", - BranchResolv, - [/* no pattern */]>; - -/* - def BINZ: - BICondForm<0b10010100100, "binz\t$rA, $func", - [(SPUbinz R32C:$rA, R32C:$func)]>; - - def BIZ: - BICondForm<0b00010100100, "biz\t$rA, $func", - [(SPUbiz R32C:$rA, R32C:$func)]>; -*/ + class BRNZVecInst: + BRNZInst<(ins VECREG:$rCond, brtarget:$dest), + [(brcond (vectype VECREG:$rCond), bb:$dest)]>; + + multiclass BranchNotZero { + def v4i32 : BRNZVecInst; + def r32 : BRNZRegInst; + } + + defm BRNZ : BranchNotZero; + + class BRZInst pattern>: + RI16Form<0b000000100, (outs), IOL, "brz\t$rT,$dest", + BranchResolv, pattern>; + + class BRZRegInst: + BRZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>; + + class BRZVecInst: + BRZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>; + + multiclass BranchZero { + def v4i32: BRZVecInst; + def r32: BRZRegInst; + } + + defm BRZ: BranchZero; + + // Note: LLVM doesn't do branch conditional, indirect. Otherwise these would + // be useful: + /* + class BINZInst pattern>: + BICondForm<0b10010100100, (outs), IOL, "binz\t$rA, $dest", pattern>; + + class BINZRegInst: + BINZInst<(ins rclass:$rA, brtarget:$dest), + [(brcond rclass:$rA, R32C:$dest)]>; + + class BINZVecInst: + BINZInst<(ins VECREG:$rA, R32C:$dest), + [(brcond (vectype VECREG:$rA), R32C:$dest)]>; + + multiclass BranchNotZeroIndirect { + def v4i32: BINZVecInst; + def r32: BINZRegInst; + } + + defm BINZ: BranchNotZeroIndirect; + + class BIZInst pattern>: + BICondForm<0b00010100100, (outs), IOL, "biz\t$rA, $func", pattern>; + + class BIZRegInst: + BIZInst<(ins rclass:$rA, R32C:$func), [/* no pattern */]>; + + class BIZVecInst: + BIZInst<(ins VECREG:$rA, R32C:$func), [/* no pattern */]>; + + multiclass BranchZeroIndirect { + def v4i32: BIZVecInst; + def r32: BIZRegInst; + } + + defm BIZ: BranchZeroIndirect; + */ + + class BRHNZInst pattern>: + RI16Form<0b011000100, (outs), IOL, "brhnz\t$rCond,$dest", BranchResolv, + pattern>; + + class BRHNZRegInst: + BRHNZInst<(ins rclass:$rCond, brtarget:$dest), + [(brcond rclass:$rCond, bb:$dest)]>; + + class BRHNZVecInst: + BRHNZInst<(ins VECREG:$rCond, brtarget:$dest), [/* no pattern */]>; + + multiclass BranchNotZeroHalfword { + def v8i16: BRHNZVecInst; + def r16: BRHNZRegInst; + } + + defm BRHNZ: BranchNotZeroHalfword; + + class BRHZInst pattern>: + RI16Form<0b001000100, (outs), IOL, "brhz\t$rT,$dest", BranchResolv, + pattern>; + + class BRHZRegInst: + BRHZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>; + + class BRHZVecInst: + BRHZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>; + + multiclass BranchZeroHalfword { + def v8i16: BRHZVecInst; + def r16: BRHZRegInst; + } + + defm BRHZ: BranchZeroHalfword; +} + +//===----------------------------------------------------------------------===// +// setcc and brcond patterns: +//===----------------------------------------------------------------------===// + +def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest), + (BRHZr16 R16C:$rA, bb:$dest)>; +def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest), + (BRHNZr16 R16C:$rA, bb:$dest)>; + +def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest), + (BRZr32 R32C:$rA, bb:$dest)>; +def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest), + (BRNZr32 R32C:$rA, bb:$dest)>; + +multiclass BranchCondEQ +{ + def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest), + (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>; + + def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest), + (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>; + + def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest), + (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>; + + def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest), + (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>; +} + +defm BRCONDeq : BranchCondEQ; +defm BRCONDne : BranchCondEQ; + +multiclass BranchCondLGT +{ + def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest), + (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>; + + def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest), + (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>; + + def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest), + (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>; + + def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest), + (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>; +} + +defm BRCONDugt : BranchCondLGT; +defm BRCONDule : BranchCondLGT; + +multiclass BranchCondLGTEQ +{ + def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest), + (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), + (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)), + bb:$dest)>; + + def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest), + (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB), + (CEQHr16 R16C:$rA, R16:$rB)), + bb:$dest)>; + + def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest), + (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), + (CEQIr32 R32C:$rA, i32ImmSExt10:$val)), + bb:$dest)>; + + def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest), + (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB), + (CEQr32 R32C:$rA, R32C:$rB)), + bb:$dest)>; +} + +defm BRCONDuge : BranchCondLGTEQ; +defm BRCONDult : BranchCondLGTEQ; + +multiclass BranchCondGT +{ + def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest), + (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>; + + def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest), + (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>; + + def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest), + (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>; + + def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest), + (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>; } -def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest), - (BRHZ R16C:$rA, bb:$dest)>; -def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest), - (BRHNZ R16C:$rA, bb:$dest)>; +defm BRCONDgt : BranchCondGT; +defm BRCONDle : BranchCondGT; + +multiclass BranchCondGTEQ +{ + def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest), + (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), + (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)), + bb:$dest)>; + + def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest), + (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB), + (CEQHr16 R16C:$rA, R16:$rB)), + bb:$dest)>; + + def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest), + (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), + (CEQIr32 R32C:$rA, i32ImmSExt10:$val)), + bb:$dest)>; + + def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest), + (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB), + (CEQr32 R32C:$rA, R32C:$rB)), + bb:$dest)>; +} -def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest), - (BRZ R32C:$rA, bb:$dest)>; -def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest), - (BRZ R32C:$rA, bb:$dest)>; +defm BRCONDge : BranchCondGTEQ; +defm BRCONDlt : BranchCondGTEQ; let isTerminator = 1, isBarrier = 1 in { let isReturn = 1 in { @@ -2879,89 +3742,198 @@ let isTerminator = 1, isBarrier = 1 in { } //===----------------------------------------------------------------------===// -// Various brcond predicates: +// Single precision floating point instructions //===----------------------------------------------------------------------===// -/* -def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest), - (BRZ R32C:$rA, bb:$dest)>; -def : Pat<(brcond (i32 (seteq R32C:$rA, R32C:$rB)), bb:$dest), - (BRNZ (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>; +class FAInst pattern>: + RRForm<0b01011000100, OOL, IOL, "fa\t$rT, $rA, $rB", + SPrecFP, pattern>; -def : Pat<(brcond (i16 (seteq R16C:$rA, i16ImmSExt10:$val)), bb:$dest), - (BRHNZ (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>; +class FAVecInst: + FAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (fadd (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; -def : Pat<(brcond (i16 (seteq R16C:$rA, R16C:$rB)), bb:$dest), - (BRHNZ (CEQHr16 R16C:$rA, R16C:$rB), bb:$dest)>; -*/ +multiclass SFPAdd +{ + def v4f32: FAVecInst; + def f32: FAInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>; +} -//===----------------------------------------------------------------------===// -// Single precision floating point instructions -//===----------------------------------------------------------------------===// +defm FA : SFPAdd; -def FAv4f32: - RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "fa\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>; +class FSInst pattern>: + RRForm<0b01011000100, OOL, IOL, "fs\t$rT, $rA, $rB", + SPrecFP, pattern>; + +class FSVecInst: + FSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (fsub (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; + +multiclass SFPSub +{ + def v4f32: FSVecInst; + def f32: FSInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>; +} + +defm FS : SFPSub; + +class FMInst pattern>: + RRForm<0b01100011010, OOL, IOL, + "fm\t$rT, $rA, $rB", SPrecFP, + pattern>; + +class FMVecInst: + FMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (type VECREG:$rT), + (fmul (type VECREG:$rA), (type VECREG:$rB)))]>; + +multiclass SFPMul +{ + def v4f32: FMVecInst; + def f32: FMInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>; +} + +defm FM : SFPMul; + +// Floating point multiply and add +// e.g. d = c + (a * b) +def FMAv4f32: + RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + "fma\t$rT, $rA, $rB, $rC", SPrecFP, + [(set (v4f32 VECREG:$rT), + (fadd (v4f32 VECREG:$rC), + (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>; + +def FMAf32: + RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), + "fma\t$rT, $rA, $rB, $rC", SPrecFP, + [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>; + +// FP multiply and subtract +// Subtracts value in rC from product +// res = a * b - c +def FMSv4f32 : + RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + "fms\t$rT, $rA, $rB, $rC", SPrecFP, + [(set (v4f32 VECREG:$rT), + (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)), + (v4f32 VECREG:$rC)))]>; + +def FMSf32 : + RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), + "fms\t$rT, $rA, $rB, $rC", SPrecFP, + [(set R32FP:$rT, + (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>; + +// Floating Negative Mulitply and Subtract +// Subtracts product from value in rC +// res = fneg(fms a b c) +// = - (a * b - c) +// = c - a * b +// NOTE: subtraction order +// fsub a b = a - b +// fs a b = b - a? +def FNMSf32 : + RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), + "fnms\t$rT, $rA, $rB, $rC", SPrecFP, + [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>; + +def FNMSv4f32 : + RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + "fnms\t$rT, $rA, $rB, $rC", SPrecFP, + [(set (v4f32 VECREG:$rT), + (fsub (v4f32 VECREG:$rC), + (fmul (v4f32 VECREG:$rA), + (v4f32 VECREG:$rB))))]>; -def FAf32 : - RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "fa\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>; -def FSv4f32: - RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "fs\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>; -def FSf32 : - RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "fs\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>; // Floating point reciprocal estimate -def FREv4f32 : - RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA), - "frest\t$rT, $rA", SPrecFP, - [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>; -def FREf32 : - RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA), - "frest\t$rT, $rA", SPrecFP, - [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>; +class FRESTInst: + RRForm_1<0b00110111000, OOL, IOL, + "frest\t$rT, $rA", SPrecFP, + [/* no pattern */]>; + +def FRESTv4f32 : + FRESTInst<(outs VECREG:$rT), (ins VECREG:$rA)>; + +def FRESTf32 : + FRESTInst<(outs R32FP:$rT), (ins R32FP:$rA)>; // Floating point interpolate (used in conjunction with reciprocal estimate) def FIv4f32 : RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), "fi\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA), - (v4f32 VECREG:$rB)))]>; + [/* no pattern */]>; def FIf32 : RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), "fi\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>; + [/* no pattern */]>; + +//-------------------------------------------------------------------------- +// Basic single precision floating point comparisons: +// +// Note: There is no support on SPU for single precision NaN. Consequently, +// ordered and unordered comparisons are the same. +//-------------------------------------------------------------------------- -// Floating Compare Equal def FCEQf32 : RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB), "fceq\t$rT, $rA, $rB", SPrecFP, - [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>; + [(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>; + +def : Pat<(setoeq R32FP:$rA, R32FP:$rB), + (FCEQf32 R32FP:$rA, R32FP:$rB)>; def FCMEQf32 : RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB), "fcmeq\t$rT, $rA, $rB", SPrecFP, - [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>; + [(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>; + +def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)), + (FCMEQf32 R32FP:$rA, R32FP:$rB)>; def FCGTf32 : RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB), "fcgt\t$rT, $rA, $rB", SPrecFP, - [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>; + [(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>; + +def : Pat<(setogt R32FP:$rA, R32FP:$rB), + (FCGTf32 R32FP:$rA, R32FP:$rB)>; def FCMGTf32 : RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB), "fcmgt\t$rT, $rA, $rB", SPrecFP, - [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>; + [(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>; + +def : Pat<(setogt (fabs R32FP:$rA), (fabs R32FP:$rB)), + (FCMGTf32 R32FP:$rA, R32FP:$rB)>; + +//-------------------------------------------------------------------------- +// Single precision floating point comparisons and SETCC equivalents: +//-------------------------------------------------------------------------- + +def : SETCCNegCondReg; +def : SETCCNegCondReg; + +def : SETCCBinOpReg; +def : SETCCBinOpReg; + +def : SETCCBinOpReg; +def : SETCCBinOpReg; + +def : Pat<(setule R32FP:$rA, R32FP:$rB), + (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>; +def : Pat<(setole R32FP:$rA, R32FP:$rB), + (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>; // FP Status and Control Register Write // Why isn't rT a don't care in the ISA? @@ -3003,75 +3975,9 @@ def FSCRRf32 : // floating reciprocal absolute square root estimate (frsqest) // The following are probably just intrinsics -// status and control register write +// status and control register write // status and control register read -//-------------------------------------- -// Floating point multiply instructions -//-------------------------------------- - -def FMv4f32: - RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "fm\t$rT, $rA, $rB", SPrecFP, - [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA), - (v4f32 VECREG:$rB)))]>; - -def FMf32 : - RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "fm\t$rT, $rA, $rB", SPrecFP, - [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>; - -// Floating point multiply and add -// e.g. d = c + (a * b) -def FMAv4f32: - RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "fma\t$rT, $rA, $rB, $rC", SPrecFP, - [(set (v4f32 VECREG:$rT), - (fadd (v4f32 VECREG:$rC), - (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>; - -def FMAf32: - RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), - "fma\t$rT, $rA, $rB, $rC", SPrecFP, - [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>; - -// FP multiply and subtract -// Subtracts value in rC from product -// res = a * b - c -def FMSv4f32 : - RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "fms\t$rT, $rA, $rB, $rC", SPrecFP, - [(set (v4f32 VECREG:$rT), - (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)), - (v4f32 VECREG:$rC)))]>; - -def FMSf32 : - RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), - "fms\t$rT, $rA, $rB, $rC", SPrecFP, - [(set R32FP:$rT, - (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>; - -// Floating Negative Mulitply and Subtract -// Subtracts product from value in rC -// res = fneg(fms a b c) -// = - (a * b - c) -// = c - a * b -// NOTE: subtraction order -// fsub a b = a - b -// fs a b = b - a? -def FNMSf32 : - RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC), - "fnms\t$rT, $rA, $rB, $rC", SPrecFP, - [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>; - -def FNMSv4f32 : - RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "fnms\t$rT, $rA, $rB, $rC", SPrecFP, - [(set (v4f32 VECREG:$rT), - (fsub (v4f32 VECREG:$rC), - (fmul (v4f32 VECREG:$rA), - (v4f32 VECREG:$rB))))]>; - //-------------------------------------- // Floating Point Conversions // Signed conversions: @@ -3080,7 +3986,7 @@ def CSiFv4f32: "csflt\t$rT, $rA, 0", SPrecFP, [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>; -// Convert signed integer to floating point +// Convert signed integer to floating point def CSiFf32 : CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA), "csflt\t$rT, $rA, 0", SPrecFP, @@ -3097,7 +4003,7 @@ def CUiFf32 : "cuflt\t$rT, $rA, 0", SPrecFP, [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>; -// Convert float to unsigned int +// Convert float to unsigned int // Assume that scale = 0 def CFUiv4f32 : @@ -3110,7 +4016,7 @@ def CFUif32 : "cfltu\t$rT, $rA, 0", SPrecFP, [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>; -// Convert float to signed int +// Convert float to signed int // Assume that scale = 0 def CFSiv4f32 : @@ -3137,7 +4043,7 @@ def CFSif32 : def FESDvec : RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA), "fesd\t$rT, $rA", SPrecFP, - [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>; + [/*(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))*/]>; def FESDf32 : RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA), @@ -3226,33 +4132,36 @@ def FMSv2f64 : (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)), (v2f64 VECREG:$rC)))]>; -// FNMS: - (a * b - c) +// DFNMS: - (a * b - c) // - (a * b) + c => c - (a * b) -def FNMSf64 : - RRForm<0b01111010110, (outs R64FP:$rT), - (ins R64FP:$rA, R64FP:$rB, R64FP:$rC), - "dfnms\t$rT, $rA, $rB", DPrecFP, - [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>, + +class DFNMSInst pattern>: + RRForm<0b01111010110, OOL, IOL, "dfnms\t$rT, $rA, $rB", + DPrecFP, pattern>, RegConstraint<"$rC = $rT">, NoEncode<"$rC">; -def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)), - (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>; +class DFNMSVecInst pattern>: + DFNMSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + pattern>; -def FNMSv2f64 : - RRForm<0b01111010110, (outs VECREG:$rT), - (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "dfnms\t$rT, $rA, $rB", DPrecFP, - [(set (v2f64 VECREG:$rT), - (fsub (v2f64 VECREG:$rC), - (fmul (v2f64 VECREG:$rA), - (v2f64 VECREG:$rB))))]>, - RegConstraint<"$rC = $rT">, - NoEncode<"$rC">; +class DFNMSRegInst pattern>: + DFNMSInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB, R64FP:$rC), + pattern>; + +multiclass DFMultiplySubtract +{ + def v2f64 : DFNMSVecInst<[(set (v2f64 VECREG:$rT), + (fsub (v2f64 VECREG:$rC), + (fmul (v2f64 VECREG:$rA), + (v2f64 VECREG:$rB))))]>; + + def f64 : DFNMSRegInst<[(set R64FP:$rT, + (fsub R64FP:$rC, + (fmul R64FP:$rA, R64FP:$rB)))]>; +} -def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)), - (v2f64 VECREG:$rC))), - (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; +defm DFNMS : DFMultiplySubtract; // - (a * b + c) // - (a * b) - c @@ -3268,9 +4177,9 @@ def FNMAv2f64 : RRForm<0b11111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), "dfnma\t$rT, $rA, $rB", DPrecFP, - [(set (v2f64 VECREG:$rT), - (fneg (fadd (v2f64 VECREG:$rC), - (fmul (v2f64 VECREG:$rA), + [(set (v2f64 VECREG:$rT), + (fneg (fadd (v2f64 VECREG:$rC), + (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))))]>, RegConstraint<"$rC = $rT">, NoEncode<"$rC">; @@ -3280,42 +4189,34 @@ def FNMAv2f64 : //===----------------------------------------------------------------------==// def : Pat<(fneg (v4f32 VECREG:$rA)), - (XORfnegvec (v4f32 VECREG:$rA), + (XORfnegvec (v4f32 VECREG:$rA), (v4f32 (ILHUv4i32 0x8000)))>; def : Pat<(fneg R32FP:$rA), (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>; -def : Pat<(fneg (v2f64 VECREG:$rA)), - (XORfnegvec (v2f64 VECREG:$rA), - (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>; - -def : Pat<(fneg R64FP:$rA), - (XORfneg64 R64FP:$rA, - (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>; - // Floating point absolute value +// Note: f64 fabs is custom-selected. def : Pat<(fabs R32FP:$rA), (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>; def : Pat<(fabs (v4f32 VECREG:$rA)), (ANDfabsvec (v4f32 VECREG:$rA), - (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>; + (IOHLv4i32 (ILHUv4i32 0x7fff), 0xffff))>; -def : Pat<(fabs R64FP:$rA), - (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>; +//===----------------------------------------------------------------------===// +// Hint for branch instructions: +//===----------------------------------------------------------------------===// -def : Pat<(fabs (v2f64 VECREG:$rA)), - (ANDfabsvec (v2f64 VECREG:$rA), - (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>; +/* def HBR : SPUInstr<(outs), (ins), "hbr\t" */ //===----------------------------------------------------------------------===// // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong // in the odd pipeline) //===----------------------------------------------------------------------===// -def ENOP : I<(outs), (ins), "enop", ExecNOP> { +def ENOP : SPUInstr<(outs), (ins), "nop", ExecNOP> { let Pattern = []; let Inst{0-10} = 0b10000000010; @@ -3324,7 +4225,7 @@ def ENOP : I<(outs), (ins), "enop", ExecNOP> { let Inst{25-31} = 0; } -def LNOP : I<(outs), (ins), "lnop", LoadNOP> { +def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> { let Pattern = []; let Inst{0-10} = 0b10000000000; @@ -3335,8 +4236,7 @@ def LNOP : I<(outs), (ins), "lnop", LoadNOP> { //===----------------------------------------------------------------------===// // Bit conversions (type conversions between vector/packed types) -// NOTE: Promotions are handled using the XS* instructions. Truncation -// is not handled. +// NOTE: Promotions are handled using the XS* instructions. //===----------------------------------------------------------------------===// def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>; def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>; @@ -3372,10 +4272,46 @@ def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>; def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>; def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>; def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>; -def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>; +def : Pat<(v2f64 (bitconvert (v4f32 VECREG:$src))), (v2f64 VECREG:$src)>; + +def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; +def : Pat<(i128 (bitconvert (v8i16 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; +def : Pat<(i128 (bitconvert (v4i32 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; +def : Pat<(i128 (bitconvert (v2i64 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; +def : Pat<(i128 (bitconvert (v4f32 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; +def : Pat<(i128 (bitconvert (v2f64 VECREG:$src))), + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; + +def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))), + (v16i8 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; +def : Pat<(v8i16 (bitconvert (i128 GPRC:$src))), + (v8i16 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; +def : Pat<(v4i32 (bitconvert (i128 GPRC:$src))), + (v4i32 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; +def : Pat<(v2i64 (bitconvert (i128 GPRC:$src))), + (v2i64 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; +def : Pat<(v4f32 (bitconvert (i128 GPRC:$src))), + (v4f32 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; +def : Pat<(v2f64 (bitconvert (i128 GPRC:$src))), + (v2f64 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; + +def : Pat<(i32 (bitconvert R32FP:$rA)), + (COPY_TO_REGCLASS R32FP:$rA, R32C)>; + +def : Pat<(f32 (bitconvert R32C:$rA)), + (COPY_TO_REGCLASS R32C:$rA, R32FP)>; + +def : Pat<(i64 (bitconvert R64FP:$rA)), + (COPY_TO_REGCLASS R64FP:$rA, R64C)>; + +def : Pat<(f64 (bitconvert R64C:$rA)), + (COPY_TO_REGCLASS R64C:$rA, R64FP)>; -def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>; -def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>; //===----------------------------------------------------------------------===// // Instruction patterns: @@ -3386,33 +4322,22 @@ def : Pat<(i32 imm:$imm), (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>; // Single precision float constants: -def : Pat<(SPUFPconstant (f32 fpimm:$imm)), +def : Pat<(f32 fpimm:$imm), (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>; // General constant 32-bit vectors def : Pat<(v4i32 v4i32Imm:$imm), - (IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))), - (LO16_vec v4i32Imm:$imm))>; - + (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))), + (LO16_vec v4i32Imm:$imm))>; + // 8-bit constants def : Pat<(i8 imm:$imm), (ILHr8 imm:$imm)>; -//===----------------------------------------------------------------------===// -// Call instruction patterns: -//===----------------------------------------------------------------------===// -// Return void -def : Pat<(ret), - (RET)>; - //===----------------------------------------------------------------------===// // Zero/Any/Sign extensions //===----------------------------------------------------------------------===// -// zext 1->32: Zero extend i1 to i32 -def : Pat<(SPUextract_i1_zext R32C:$rSrc), - (ANDIr32 R32C:$rSrc, 0x1)>; - // sext 8->32: Sign extend bytes to words def : Pat<(sext_inreg R32C:$rSrc, i8), (XSHWr32 (XSBHr32 R32C:$rSrc))>; @@ -3420,68 +4345,168 @@ def : Pat<(sext_inreg R32C:$rSrc, i8), def : Pat<(i32 (sext R8C:$rSrc)), (XSHWr16 (XSBHr8 R8C:$rSrc))>; -def : Pat<(SPUextract_i8_sext VECREG:$rSrc), - (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), - (v4i32 VECREG:$rSrc))))>; +// sext 8->64: Sign extend bytes to double word +def : Pat<(sext_inreg R64C:$rSrc, i8), + (XSWDr64_inreg (XSHWr64 (XSBHr64 R64C:$rSrc)))>; + +def : Pat<(i64 (sext R8C:$rSrc)), + (XSWDr64 (XSHWr16 (XSBHr8 R8C:$rSrc)))>; // zext 8->16: Zero extend bytes to halfwords def : Pat<(i16 (zext R8C:$rSrc)), - (ANDHI1To2 R8C:$rSrc, 0xff)>; - -// zext 8->32 from preferred slot in load/store -def : Pat<(SPUextract_i8_zext VECREG:$rSrc), - (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)), - 0xff)>; + (ANDHIi8i16 R8C:$rSrc, 0xff)>; // zext 8->32: Zero extend bytes to words def : Pat<(i32 (zext R8C:$rSrc)), - (ANDI1To4 R8C:$rSrc, 0xff)>; - -// anyext 8->16: Extend 8->16 bits, irrespective of sign + (ANDIi8i32 R8C:$rSrc, 0xff)>; + +// zext 8->64: Zero extend bytes to double words +def : Pat<(i64 (zext R8C:$rSrc)), + (COPY_TO_REGCLASS (SELBv4i32 (ROTQMBYv4i32 + (COPY_TO_REGCLASS + (ANDIi8i32 R8C:$rSrc,0xff), VECREG), + 0x4), + (ILv4i32 0x0), + (FSMBIv4i32 0x0f0f)), R64C)>; + +// anyext 8->16: Extend 8->16 bits, irrespective of sign, preserves high bits def : Pat<(i16 (anyext R8C:$rSrc)), - (ORHI1To2 R8C:$rSrc, 0)>; + (ORHIi8i16 R8C:$rSrc, 0)>; -// anyext 8->32: Extend 8->32 bits, irrespective of sign +// anyext 8->32: Extend 8->32 bits, irrespective of sign, preserves high bits def : Pat<(i32 (anyext R8C:$rSrc)), - (ORI1To4 R8C:$rSrc, 0)>; + (COPY_TO_REGCLASS R8C:$rSrc, R32C)>; -// zext 16->32: Zero extend halfwords to words (note that we have to juggle the -// 0xffff constant since it will not fit into an immediate.) +// sext 16->64: Sign extend halfword to double word +def : Pat<(sext_inreg R64C:$rSrc, i16), + (XSWDr64_inreg (XSHWr64 R64C:$rSrc))>; + +def : Pat<(sext R16C:$rSrc), + (XSWDr64 (XSHWr16 R16C:$rSrc))>; + +// zext 16->32: Zero extend halfwords to words def : Pat<(i32 (zext R16C:$rSrc)), - (AND2To4 R16C:$rSrc, (ILAr32 0xffff))>; + (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>; def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))), - (ANDI2To4 R16C:$rSrc, 0xf)>; + (ANDIi16i32 R16C:$rSrc, 0xf)>; def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))), - (ANDI2To4 R16C:$rSrc, 0xff)>; + (ANDIi16i32 R16C:$rSrc, 0xff)>; def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))), - (ANDI2To4 R16C:$rSrc, 0xfff)>; + (ANDIi16i32 R16C:$rSrc, 0xfff)>; // anyext 16->32: Extend 16->32 bits, irrespective of sign def : Pat<(i32 (anyext R16C:$rSrc)), - (ORI2To4 R16C:$rSrc, 0)>; + (COPY_TO_REGCLASS R16C:$rSrc, R32C)>; + +//===----------------------------------------------------------------------===// +// Truncates: +// These truncates are for the SPU's supported types (i8, i16, i32). i64 and +// above are custom lowered. +//===----------------------------------------------------------------------===// + +def : Pat<(i8 (trunc GPRC:$src)), + (COPY_TO_REGCLASS + (SHUFBgprc GPRC:$src, GPRC:$src, + (IOHLv4i32 (ILHUv4i32 0x0f0f), 0x0f0f)), R8C)>; + +def : Pat<(i8 (trunc R64C:$src)), + (COPY_TO_REGCLASS + (SHUFBv2i64_m32 + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0707), 0x0707)), R8C)>; + +def : Pat<(i8 (trunc R32C:$src)), + (COPY_TO_REGCLASS + (SHUFBv4i32_m32 + (COPY_TO_REGCLASS R32C:$src, VECREG), + (COPY_TO_REGCLASS R32C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)), R8C)>; + +def : Pat<(i8 (trunc R16C:$src)), + (COPY_TO_REGCLASS + (SHUFBv4i32_m32 + (COPY_TO_REGCLASS R16C:$src, VECREG), + (COPY_TO_REGCLASS R16C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)), R8C)>; + +def : Pat<(i16 (trunc GPRC:$src)), + (COPY_TO_REGCLASS + (SHUFBgprc GPRC:$src, GPRC:$src, + (IOHLv4i32 (ILHUv4i32 0x0e0f), 0x0e0f)), R16C)>; + +def : Pat<(i16 (trunc R64C:$src)), + (COPY_TO_REGCLASS + (SHUFBv2i64_m32 + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0607), 0x0607)), R16C)>; + +def : Pat<(i16 (trunc R32C:$src)), + (COPY_TO_REGCLASS + (SHUFBv4i32_m32 + (COPY_TO_REGCLASS R32C:$src, VECREG), + (COPY_TO_REGCLASS R32C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0203), 0x0203)), R16C)>; + +def : Pat<(i32 (trunc GPRC:$src)), + (COPY_TO_REGCLASS + (SHUFBgprc GPRC:$src, GPRC:$src, + (IOHLv4i32 (ILHUv4i32 0x0c0d), 0x0e0f)), R32C)>; + +def : Pat<(i32 (trunc R64C:$src)), + (COPY_TO_REGCLASS + (SHUFBv2i64_m32 + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0405), 0x0607)), R32C)>; //===----------------------------------------------------------------------===// -// Address translation: SPU, like PPC, has to split addresses into high and +// Address generation: SPU, like PPC, has to split addresses into high and // low parts in order to load them into a register. //===----------------------------------------------------------------------===// -def : Pat<(SPUhi tglobaladdr:$in, 0), (ILHUhi tglobaladdr:$in)>; -def : Pat<(SPUlo tglobaladdr:$in, 0), (ILAlo tglobaladdr:$in)>; -def : Pat<(SPUdform tglobaladdr:$in, imm:$imm), (ILAlsa tglobaladdr:$in)>; -def : Pat<(SPUhi tconstpool:$in , 0), (ILHUhi tconstpool:$in)>; -def : Pat<(SPUlo tconstpool:$in , 0), (ILAlo tconstpool:$in)>; -def : Pat<(SPUdform tconstpool:$in, imm:$imm), (ILAlsa tconstpool:$in)>; -def : Pat<(SPUhi tjumptable:$in, 0), (ILHUhi tjumptable:$in)>; -def : Pat<(SPUlo tjumptable:$in, 0), (ILAlo tjumptable:$in)>; -def : Pat<(SPUdform tjumptable:$in, imm:$imm), (ILAlsa tjumptable:$in)>; - -// Force load of global address to a register. These forms show up in -// SPUISD::DFormAddr pseudo instructions: -def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>; -def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>; -def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>; -// Instrinsics: +def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>; +def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>; +def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>; +def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>; + +def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0), + (SPUlo tglobaladdr:$in, 0)), + (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>; + +def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0), + (SPUlo texternalsym:$in, 0)), + (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>; + +def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0), + (SPUlo tjumptable:$in, 0)), + (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>; + +def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0), + (SPUlo tconstpool:$in, 0)), + (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>; + +def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)), + (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>; + +def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)), + (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>; + +def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)), + (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>; + +def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)), + (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>; + +// Intrinsics: include "CellSDKIntrinsics.td" +// Various math operator instruction sequences +include "SPUMathInstr.td" +// 64-bit "instructions"/support +include "SPU64InstrInfo.td" +// 128-bit "instructions"/support +include "SPU128InstrInfo.td"