X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPUOperands.td;h=6f8deef5530f54fa9bd25205d67b590cec41c852;hb=fef904d0e824a2c587f8c1063b6c4fbf47fec898;hp=afe815c3c438a8afe26299af4b3fd01c4ac8910c;hpb=ba36cb5242eb02b12b277f82b9efe497f7da4d7f;p=oota-llvm.git

diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index afe815c3c43..6f8deef5530 100644
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -1,16 +1,27 @@
-//===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
-// 
+//===-- SPUOperands.td - Cell SPU Instruction Operands -----*- tablegen -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 // Cell SPU Instruction Operands:
 //===----------------------------------------------------------------------===//
 
+// TO_IMM32 - Convert an i8/i16 to i32.
+def TO_IMM32 : SDNodeXForm<imm, [{
+  return getI32Imm(N->getZExtValue());
+}]>;
+
+// TO_IMM16 - Convert an i8/i32 to i16.
+def TO_IMM16 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i16);
+}]>;
+
+
 def LO16 : SDNodeXForm<imm, [{
-  unsigned val = N->getValue();
+  unsigned val = N->getZExtValue();
   // Transformation function: get the low 16 bits.
   return getI32Imm(val & 0xffff);
 }]>;
@@ -24,7 +35,8 @@ def LO16_vec : SDNodeXForm<scalar_to_vector, [{
          && "LO16_vec got something other than a BUILD_VECTOR");
 
   // Get first constant operand...
-  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
+  for (unsigned i = 0, e = N->getNumOperands();
+       OpVal.getNode() == 0 && i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
     if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
@@ -32,12 +44,12 @@ def LO16_vec : SDNodeXForm<scalar_to_vector, [{
   
   assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
-  return getI32Imm((unsigned)CN->getValue() & 0xffff);
+  return getI32Imm((unsigned)CN->getZExtValue() & 0xffff);
 }]>;
 
 // Transform an immediate, returning the high 16 bits shifted down:
 def HI16 : SDNodeXForm<imm, [{
-  return getI32Imm((unsigned)N->getValue() >> 16);
+  return getI32Imm((unsigned)N->getZExtValue() >> 16);
 }]>;
 
 // Transformation function: shift the high 16 bit immediate from a build_vector
@@ -49,7 +61,8 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
          && "HI16_vec got something other than a BUILD_VECTOR");
   
   // Get first constant operand...
-  for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
+  for (unsigned i = 0, e = N->getNumOperands();
+       OpVal.getNode() == 0 && i != e; ++i) {
     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
     if (OpVal.getNode() == 0)
       OpVal = N->getOperand(i);
@@ -57,38 +70,32 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
   
   assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
   ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
-  return getI32Imm((unsigned)CN->getValue() >> 16);
+  return getI32Imm((unsigned)CN->getZExtValue() >> 16);
 }]>;
 
 // simm7 predicate - True if the immediate fits in an 7-bit signed
 // field.
 def simm7: PatLeaf<(imm), [{
-  int sextVal = int(N->getSignExtended());
+  int sextVal = int(N->getSExtValue());
   return (sextVal >= -64 && sextVal <= 63);
 }]>;
 
 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
 // field.
 def uimm7: PatLeaf<(imm), [{
-  return (N->getValue() <= 0x7f);
+  return (N->getZExtValue() <= 0x7f);
 }]>;
 
 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
 // field.
 def immSExt8  : PatLeaf<(imm), [{
-  int Value = int(N->getSignExtended());
+  int Value = int(N->getSExtValue());
   return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
 }]>;
 
 // immU8: immediate, unsigned 8-bit quantity
 def immU8 : PatLeaf<(imm), [{
-  return (N->getValue() <= 0xff);
-}]>;
-
-// i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
-// extended field.  Used by RI10Form instructions like 'ldq'.
-def i64ImmSExt10  : PatLeaf<(imm), [{
-  return isI64IntS10Immediate(N);
+  return (N->getZExtValue() <= 0xff);
 }]>;
 
 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
@@ -125,25 +132,25 @@ def immSExt16  : PatLeaf<(imm), [{
 def immZExt16  : PatLeaf<(imm), [{
   // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
   // field.
-  return (uint64_t)N->getValue() == (unsigned short)N->getValue();
+  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
 
 def immU16 : PatLeaf<(imm), [{
   // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
-  return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
+  return (uint64_t)N->getZExtValue() == (N->getZExtValue() & 0xffff);
 }]>;
 
 def imm18  : PatLeaf<(imm), [{
   // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
-  int Value = (int) N->getValue();
-  return ((Value & ((1 << 19) - 1)) == Value);
+  int Value = (int) N->getZExtValue();
+  return isUInt<18>(Value); 
 }]>;
 
 def lo16 : PatLeaf<(imm), [{
   // lo16 predicate - returns true if the immediate has all zeros in the
   // low order bits and is a 32-bit constant:
   if (N->getValueType(0) == MVT::i32) {
-    uint32_t val = N->getValue();
+    uint32_t val = N->getZExtValue();
     return ((val & 0x0000ffff) == val);
   }
 
@@ -154,10 +161,10 @@ def hi16 : PatLeaf<(imm), [{
   // hi16 predicate - returns true if the immediate has all zeros in the
   // low order bits and is a 32-bit constant:
   if (N->getValueType(0) == MVT::i32) {
-    uint32_t val = uint32_t(N->getValue());
+    uint32_t val = uint32_t(N->getZExtValue());
     return ((val & 0xffff0000) == val);
   } else if (N->getValueType(0) == MVT::i64) {
-    uint64_t val = N->getValue();
+    uint64_t val = N->getZExtValue();
     return ((val & 0xffff0000ULL) == val);
   }
 
@@ -167,7 +174,7 @@ def hi16 : PatLeaf<(imm), [{
 def bitshift : PatLeaf<(imm), [{
   // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
   // (shift left quadword by bits immediate)
-  int64_t Val = N->getValue();
+  int64_t Val = N->getZExtValue();
   return (Val > 0 && Val <= 7);
 }]>;
 
@@ -196,7 +203,7 @@ def FPimm_sext16 : SDNodeXForm<fpimm, [{
 
 def FPimm_u18 : SDNodeXForm<fpimm, [{
   float fval = N->getValueAPF().convertToFloat();
-  return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
+  return getI32Imm(FloatToBits(fval) & ((1 << 18) - 1));
 }]>;
 
 def fpimmSExt16 : PatLeaf<(fpimm), [{
@@ -218,7 +225,7 @@ def hi16_f32 : PatLeaf<(fpimm), [{
 def fpimm18  : PatLeaf<(fpimm), [{
   if (N->getValueType(0) == MVT::f32) {
     uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
-    return ((Value & ((1 << 19) - 1)) == Value);
+    return isUInt<18>(Value);
   }
 
   return false;
@@ -573,7 +580,7 @@ def calltarget : Operand<iPTR> {
   let MIOperandInfo = (ops u18imm:$calldest);
 }
 
-// Relative call target
+// PC relative call target
 def relcalltarget : Operand<iPTR> {
   let PrintMethod = "printPCRelativeOperand";
   let MIOperandInfo = (ops s16imm:$calldest);
@@ -584,6 +591,11 @@ def brtarget : Operand<OtherVT> {
   let PrintMethod = "printPCRelativeOperand";
 }
 
+// Hint for branch target
+def hbrtarget : Operand<OtherVT> {
+  let PrintMethod = "printHBROperand";
+}
+
 // Indirect call target
 def indcalltarget : Operand<iPTR> {
   let PrintMethod = "printCallOperand";
@@ -602,15 +614,15 @@ def symbolLSA: Operand<i32> {
   let PrintMethod = "printSymbolLSA";
 }
 
-// memory s7imm(reg) operaand
-def memri7 : Operand<iPTR> {
-  let PrintMethod = "printMemRegImmS7";
+// Shuffle address memory operaand [s7imm(reg) d-format]
+def shufaddr : Operand<iPTR> {
+  let PrintMethod = "printShufAddr";
   let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
 }
 
 // memory s10imm(reg) operand
-def memri10 : Operand<iPTR> {
-  let PrintMethod = "printMemRegImmS10";
+def dformaddr : Operand<iPTR> {
+  let PrintMethod = "printDFormAddr";
   let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
 }
 
@@ -642,7 +654,11 @@ def memrr : Operand<iPTR> {
 // A-form   : abs     (256K LSA offset)
 // D-form(2): [r+I7]  (7-bit signed offset + reg)
 
-def dform_addr   : ComplexPattern<iPTR, 2, "SelectDFormAddr",     [], []>;
-def xform_addr   : ComplexPattern<iPTR, 2, "SelectXFormAddr",     [], []>;
-def aform_addr   : ComplexPattern<iPTR, 2, "SelectAFormAddr",     [], []>;
-def dform2_addr  : ComplexPattern<iPTR, 2, "SelectDForm2Addr",    [], []>;
+def dform_addr   : ComplexPattern<iPTR, 2, "SelectDFormAddr",
+                                  [], [SDNPWantRoot]>;
+def xform_addr   : ComplexPattern<iPTR, 2, "SelectXFormAddr",
+                                  [], [SDNPWantRoot]>;
+def aform_addr   : ComplexPattern<iPTR, 2, "SelectAFormAddr",
+                                  [], [SDNPWantRoot]>;
+def dform2_addr  : ComplexPattern<iPTR, 2, "SelectDForm2Addr",
+                                  [], [SDNPWantRoot]>;