X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPURegisterInfo.cpp;h=af94e67bbdce313bd4b57ce214ed820ba8c718d8;hb=0c439eb2c8397996cbccaf2798e598052d9982c8;hp=843760ee5eb69d8442e8beee4b6bb63f446eae84;hpb=4aefd6b7d4dadf8109221a89742725c116d8f8e0;p=oota-llvm.git diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 843760ee5eb..af94e67bbdc 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -28,7 +28,6 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -36,11 +35,12 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include using namespace llvm; @@ -178,8 +178,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) { case SPU::R126: return 126; case SPU::R127: return 127; default: - std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n"; - abort(); + llvm_report_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering"); } } @@ -191,15 +190,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, { } -void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, - const MachineInstr *Orig) const { - MachineInstr *MI = Orig->clone(); - MI->getOperand(0).setReg(DestReg); - MBB.insert(I, MI); -} - // SPU's 128-bit registers used for argument passing: static const unsigned SPU_ArgRegs[] = { SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9, @@ -227,6 +217,13 @@ SPURegisterInfo::getNumArgRegs() return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]); } +/// getPointerRegClass - Return the register class to use to hold pointers. +/// This is used for addressing modes. +const TargetRegisterClass * +SPURegisterInfo::getPointerRegClass(unsigned Kind) const { + return &SPU::R32CRegClass; +} + const unsigned * SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { @@ -249,7 +246,7 @@ SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const SPU::R0, /* link register */ 0 /* end */ }; - + return SPU_CalleeSaveRegs; } @@ -279,7 +276,7 @@ SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const &SPU::GPRCRegClass, /* link register */ 0 /* end */ }; - + return SPU_CalleeSaveRegClasses; } @@ -329,9 +326,9 @@ SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, MBB.erase(I); } -void +unsigned SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, - RegScavenger *RS) const + int *Value, RegScavenger *RS) const { unsigned i = 0; MachineInstr &MI = *II; @@ -339,7 +336,7 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, MachineFunction &MF = *MBB.getParent(); MachineFrameInfo *MFI = MF.getFrameInfo(); - while (!MI.getOperand(i).isFrameIndex()) { + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } @@ -350,10 +347,13 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, // Now add the frame object offset to the offset from r1. int Offset = MFI->getObjectOffset(FrameIndex); - // Most instructions, except for generated FrameIndex additions using AIr32, - // have the immediate in operand 1. AIr32, in this case, has the immediate - // in operand 2. - unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2); + // Most instructions, except for generated FrameIndex additions using AIr32 + // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the + // immediate in operand 2. + unsigned OpNo = 1; + if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32) + OpNo = 2; + MachineOperand &MO = MI.getOperand(OpNo); // Offset is biased by $lr's slot at the bottom. @@ -365,12 +365,13 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, SPOp.ChangeToRegister(SPU::R1, false); if (Offset > SPUFrameInfo::maxFrameOffset() || Offset < SPUFrameInfo::minFrameOffset()) { - cerr << "Large stack adjustment (" - << Offset + errs() << "Large stack adjustment (" + << Offset << ") in SPURegisterInfo::eliminateFrameIndex."; } else { MO.ChangeToImmediate(Offset); } + return 0; } /// determineFrameLayout - Determine the size of the frame and maximum call @@ -382,7 +383,7 @@ SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const // Get the number of bytes to allocate from the FrameInfo unsigned FrameSize = MFI->getStackSize(); - + // Get the alignments provided by the target, and the maximum alignment // (if any) of the fixed frame objects. unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); @@ -392,7 +393,7 @@ SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const // Get the maximum call frame size of all the calls. unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); - + // If we have dynamic alloca then maxCallFrameSize needs to be aligned so // that allocations will be aligned. if (MFI->hasVarSizedObjects()) @@ -400,7 +401,7 @@ SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const // Update maximum call frame size. MFI->setMaxCallFrameSize(maxCallFrameSize); - + // Include call frame size in total. FrameSize += maxCallFrameSize; @@ -414,11 +415,6 @@ SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { -#if 0 - // Save and clear the LR state. - SPUFunctionInfo *FI = MF.getInfo(); - FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); -#endif // Mark LR and SP unused, since the prolog spills them to stack and // we don't want anyone else to spill them for us. // @@ -434,73 +430,77 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - + DebugLoc dl = (MBBI != MBB.end() ? + MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); + // Prepare for debug frame info. bool hasDebugInfo = MMI && MMI->hasDebugInfo(); unsigned FrameLabelId = 0; - + // Move MBBI back to the beginning of the function. MBBI = MBB.begin(); - + // Work out frame sizes. determineFrameLayout(MF); int FrameSize = MFI->getStackSize(); - + assert((FrameSize & 0xf) == 0 && "SPURegisterInfo::emitPrologue: FrameSize not aligned"); - if (FrameSize > 0) { + if (FrameSize > 0 || MFI->hasCalls()) { FrameSize = -(FrameSize + SPUFrameInfo::minStackSize()); if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); } - + // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) // for the ABI - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) .addReg(SPU::R1); if (isS10Constant(FrameSize)) { // Spill $sp to adjusted $sp - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) .addReg(SPU::R1); // Adjust $sp by required amout - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(-16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1) .addReg(SPU::R2) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) .addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { - cerr << "Unhandled frame size: " << FrameSize << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Unhandled frame size: " << FrameSize; + llvm_report_error(Msg.str()); } - + if (hasDebugInfo) { std::vector &Moves = MMI->getFrameMoves(); - + // Show update of SP. MachineLocation SPDst(MachineLocation::VirtualFP); MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize); Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); - + // Add callee saved registers to move list. const std::vector &CSI = MFI->getCalleeSavedInfo(); for (unsigned I = 0, E = CSI.size(); I != E; ++I) { @@ -511,11 +511,11 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const MachineLocation CSSrc(Reg); Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); } - + // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0); - + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); + MachineLocation FPDst(SPU::R1); MachineLocation FPSrc(MachineLocation::VirtualFP); Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); @@ -526,9 +526,11 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const // this is just a best guess based on the basic block's size. if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) { MachineBasicBlock::iterator MBBI = prior(MBB.end()); + dl = MBBI->getDebugLoc(); + // Insert terminator label unsigned BranchLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0); + BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); } } } @@ -540,46 +542,49 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const const MachineFrameInfo *MFI = MF.getFrameInfo(); int FrameSize = MFI->getStackSize(); int LinkSlotOffset = SPUFrameInfo::stackSlotSize(); + DebugLoc dl = MBBI->getDebugLoc(); assert(MBBI->getOpcode() == SPU::RET && "Can only insert epilog into returning blocks"); assert((FrameSize & 0xf) == 0 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned"); - if (FrameSize > 0) { + if (FrameSize > 0 || MFI->hasCalls()) { FrameSize = FrameSize + SPUFrameInfo::minStackSize(); if (isS10Constant(FrameSize + LinkSlotOffset)) { // Reload $lr, adjust $sp by required amount // Note: We do this to slightly improve dual issue -- not by much, but it // is an opportunity for dual issue. - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(FrameSize + LinkSlotOffset) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1) .addReg(SPU::R1) .addImm(FrameSize); } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use // $r2 to adjust $sp: - BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) .addImm(16) .addReg(SPU::R1); - BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) .addImm(FrameSize); - BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1) + BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) .addReg(SPU::R1) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) .addImm(16) .addReg(SPU::R2); - BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2). + BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2). addReg(SPU::R2) .addImm(16); - BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2) + BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) .addReg(SPU::R2) .addReg(SPU::R1); } else { - cerr << "Unhandled frame size: " << FrameSize << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Unhandled frame size: " << FrameSize; + llvm_report_error(Msg.str()); } } } @@ -591,7 +596,7 @@ SPURegisterInfo::getRARegister() const } unsigned -SPURegisterInfo::getFrameRegister(MachineFunction &MF) const +SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { return SPU::R1; }