X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FCellSPU%2FSPUTargetMachine.cpp;h=21f6b25bf256867423781e0dcb365b1bd38a0069;hb=4e02f23de24375294005f88b5254a3775d39fcb2;hp=480ec3f7f885641a2b3fbe54adc0d689a2fb2a7c;hpb=ff7a562751604a9fe13efc75bd59622244b54d35;p=oota-llvm.git diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 480ec3f7f88..21f6b25bf25 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -11,51 +11,83 @@ // //===----------------------------------------------------------------------===// -#include "SPU.h" -#include "SPURegisterNames.h" -#include "SPUMCAsmInfo.h" #include "SPUTargetMachine.h" +#include "SPU.h" #include "llvm/PassManager.h" -#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/DynamicLibrary.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; -extern "C" void LLVMInitializeCellSPUTarget() { +extern "C" void LLVMInitializeCellSPUTarget() { // Register the target. RegisterTargetMachine X(TheCellSPUTarget); - RegisterAsmInfo Y(TheCellSPUTarget); } const std::pair * -SPUFrameInfo::getCalleeSaveSpillSlots(unsigned &NumEntries) const { +SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { NumEntries = 1; return &LR[0]; } -SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) - : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), +SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), - FrameInfo(*this), + FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - // For the time being, use static relocations, since there's really no - // support for PIC yet. - setRelocationModel(Reloc::Static); } //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool SPUTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { +namespace { +/// SPU Code Generator Pass Configuration Options. +class SPUPassConfig : public TargetPassConfig { +public: + SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + SPUTargetMachine &getSPUTargetMachine() const { + return getTM(); + } + + virtual bool addInstSelector(); + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SPUPassConfig(this, PM); +} + +bool SPUPassConfig::addInstSelector() { // Install an instruction selector. - PM.add(createSPUISelDag(*this)); + PM.add(createSPUISelDag(getSPUTargetMachine())); return false; } + +// passes to run just before printing the assembly +bool SPUPassConfig::addPreEmitPass() { + // load the TCE instruction scheduler, if available via + // loaded plugins + typedef llvm::FunctionPass* (*BuilderFunc)(const char*); + BuilderFunc schedulerCreator = + (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol( + "createTCESchedulerPass"); + if (schedulerCreator != NULL) + PM.add(schedulerCreator("cellspu")); + + //align instructions with nops/lnops for dual issue + PM.add(createSPUNopFillerPass(getSPUTargetMachine())); + return true; +}