X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonInstrFormats.td;h=3c5ec1701dc229723958fc866c0154429f128bb3;hb=16d4cc83c30485f28bb37715930c4302749d23b1;hp=105734349321986e2370dd5ed7939363f82453ea;hpb=798f57f9c9f3ab609f2ddabdc6f716035b0be8ba;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 10573434932..3c5ec1701dc 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -28,20 +28,14 @@ def TypeXTYPE : IType<8>; def TypeENDLOOP: IType<31>; // Maintain list of valid subtargets for each instruction. -class SubTarget value> { - bits<4> Value = value; +class SubTarget value> { + bits<6> Value = value; } -def HasV2SubT : SubTarget<0xf>; -def HasV2SubTOnly : SubTarget<0x1>; -def NoV2SubT : SubTarget<0x0>; -def HasV3SubT : SubTarget<0xe>; -def HasV3SubTOnly : SubTarget<0x2>; -def NoV3SubT : SubTarget<0x1>; -def HasV4SubT : SubTarget<0xc>; -def NoV4SubT : SubTarget<0x3>; -def HasV5SubT : SubTarget<0x8>; -def NoV5SubT : SubTarget<0x7>; +def HasAnySubT : SubTarget<0x3f>; // 111111 +def HasV5SubT : SubTarget<0x3e>; // 111110 +def HasV55SubT : SubTarget<0x3c>; // 111100 +def HasV60SubT : SubTarget<0x38>; // 111000 // Addressing modes for load/store instructions class AddrModeType value> { @@ -56,8 +50,8 @@ def BaseLongOffset : AddrModeType<4>; // Indirect with long offset def BaseRegOffset : AddrModeType<5>; // Indirect with register offset def PostInc : AddrModeType<6>; // Post increment addressing mode -class MemAccessSize value> { - bits<3> Value = value; +class MemAccessSize value> { + bits<4> Value = value; } def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. @@ -65,6 +59,8 @@ def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). def WordAccess : MemAccessSize<3>;// Word access instruction (memw). def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) +def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv) +def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv) //===----------------------------------------------------------------------===// @@ -74,17 +70,15 @@ def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) class OpcodeHexagon { field bits<32> Inst = ?; // Default to an invalid insn. bits<4> IClass = 0; // ICLASS - bits<2> IParse = 0; // Parse bits. let Inst{31-28} = IClass; - let Inst{15-14} = IParse; bits<1> zero = 0; } class InstHexagon pattern, string cstr, InstrItinClass itin, IType type> - : Instruction, OpcodeHexagon { + : Instruction { let Namespace = "Hexagon"; dag OutOperandList = outs; @@ -95,6 +89,12 @@ class InstHexagon pattern, let Itinerary = itin; let Size = 4; + // SoftFail is a field the disassembler can use to provide a way for + // instructions to not match without killing the whole decode process. It is + // mainly used for ARM, but Tablegen expects this field to exist or it fails + // to build the decode table. + field bits<32> SoftFail = 0; + // *** Must match MCTargetDesc/HexagonBaseInfo.h *** // Instruction type according to the ISA. @@ -151,11 +151,11 @@ class InstHexagon pattern, bits<2> opExtentAlign = 0; let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. - // If an instruction is valid on a subtarget (v2-v5), set the corresponding - // bit from validSubTargets. v2 is the least significant bit. + // If an instruction is valid on a subtarget, set the corresponding + // bit from validSubTargets. // By default, instruction is valid on all subtargets. - SubTarget validSubTargets = HasV2SubT; - let TSFlags{37-34} = validSubTargets.Value; + SubTarget validSubTargets = HasAnySubT; + let TSFlags{39-34} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; @@ -163,7 +163,7 @@ class InstHexagon pattern, // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{45-43} = accessSize.Value; + let TSFlags{46-43} = accessSize.Value; bits<1> isTaken = 0; let TSFlags {47} = isTaken; // Branch prediction. @@ -171,21 +171,31 @@ class InstHexagon pattern, bits<1> isFP = 0; let TSFlags {48} = isFP; // Floating-point. + bits<1> hasNewValue2 = 0; + let TSFlags{50} = hasNewValue2; // Second New-value producer insn. + bits<3> opNewValue2 = 0; + let TSFlags{53-51} = opNewValue2; // Second New-value produced operand. + + bits<1> isAccumulator = 0; + let TSFlags{54} = isAccumulator; + // Fields used for relation models. + bit isNonTemporal = 0; + string isNT = ""; // set to "true" for non-temporal vector stores. string BaseOpcode = ""; string CextOpcode = ""; string PredSense = ""; string PNewValue = ""; string NValueST = ""; // Set to "true" for new-value stores. string InputType = ""; // Input is "imm" or "reg" type. - string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. string isFloat = "false"; // Set to "true" for the floating-point load/store. - string isBrTaken = ""; // Set to "true"/"false" for jump instructions + string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), ""); let PNewValue = !if(isPredicatedNew, "new", ""); let NValueST = !if(isNVStore, "true", "false"); + let isNT = !if(isNonTemporal, "true", "false"); // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } @@ -196,9 +206,10 @@ class InstHexagon pattern, // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. +let mayLoad = 1 in class LDInst pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> - : InstHexagon; + : InstHexagon, OpcodeHexagon; let mayLoad = 1 in class LDInst2 pattern = [], @@ -218,6 +229,11 @@ class LDInstPost pattern = [], let mayLoad = 1 in class LD0Inst pattern = [], string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> + : InstHexagon, OpcodeHexagon; + +let mayLoad = 1 in +class LD1Inst pattern = [], + string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> : InstHexagon; // ST Instruction Class in V2/V3 can take SLOT0 only. @@ -226,7 +242,7 @@ class LD0Inst pattern = [], let mayStore = 1 in class STInst pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> - : InstHexagon; + : InstHexagon, OpcodeHexagon; class STInst2 pattern = [], string cstr = ""> @@ -235,6 +251,12 @@ class STInst2 pattern = [], let mayStore = 1 in class ST0Inst pattern = [], string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0> + : InstHexagon, OpcodeHexagon; + +// Same as ST0Inst but doesn't derive from OpcodeHexagon. +let mayStore = 1 in +class ST1Inst pattern = [], + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0> : InstHexagon; // ST Instruction Class in V2/V3 can take SLOT0 only. @@ -248,13 +270,14 @@ class STInstPost pattern = [], // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. class SYSInst pattern = [], string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> - : InstHexagon; + : InstHexagon, + OpcodeHexagon; // ALU32 Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class ALU32Inst pattern = [], string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : InstHexagon; + : InstHexagon, OpcodeHexagon; // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. @@ -262,7 +285,8 @@ class ALU32Inst pattern = [], // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. class ALU64Inst pattern = [], string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> - : InstHexagon; + : InstHexagon, + OpcodeHexagon; class ALU64_acc pattern = [], string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> @@ -275,6 +299,12 @@ class ALU64_acc pattern = [], // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst pattern = [], string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> + : InstHexagon, + OpcodeHexagon; + +// Same as above but doesn't derive from OpcodeHexagon +class MInst2 pattern = [], + string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> : InstHexagon; // M Instruction Class in V2/V3. @@ -291,6 +321,11 @@ class MInst_acc pattern = [], // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst pattern = [], string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> + : InstHexagon, + OpcodeHexagon; + +class SInst2 pattern = [], + string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> : InstHexagon; // S Instruction Class in V2/V3. @@ -305,34 +340,37 @@ class SInst_acc pattern = [], // Definition of the instruction class NOT CHANGED. class JInst pattern = [], string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23> - : InstHexagon; + : InstHexagon, OpcodeHexagon; // JR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JRInst pattern = [], string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> - : InstHexagon; + : InstHexagon, OpcodeHexagon; // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst pattern = [], string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3> - : InstHexagon; + : InstHexagon, OpcodeHexagon; let isCodeGenOnly = 1, isPseudo = 1 in class Endloop pattern = [], string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123> - : InstHexagon; + : InstHexagon, + OpcodeHexagon; let isCodeGenOnly = 1, isPseudo = 1 in class Pseudo pattern = [], string cstr = ""> - : InstHexagon; + : InstHexagon, + OpcodeHexagon; let isCodeGenOnly = 1, isPseudo = 1 in class PseudoM pattern = [], string cstr=""> - : InstHexagon; + : InstHexagon, + OpcodeHexagon; //===----------------------------------------------------------------------===// // Instruction Classes Definitions - @@ -358,7 +396,6 @@ class ALU32_ii pattern = [], string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> : ALU32Inst; - // // ALU64 patterns. // @@ -399,3 +436,13 @@ include "HexagonInstrFormatsV4.td" //===----------------------------------------------------------------------===// // V4 Instruction Format Definitions + //===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// V60 Instruction Format Definitions + +//===----------------------------------------------------------------------===// + +include "HexagonInstrFormatsV60.td" + +//===----------------------------------------------------------------------===// +// V60 Instruction Format Definitions + +//===----------------------------------------------------------------------===//