X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMBlaze%2FMBlazeInstrFormats.td;h=e40432a1b9a9a85f28e62fe7f6535fee7ebb2b5e;hb=65063feac53406ffb7179801272b8726a654b6d4;hp=71e3b12e8e3abca2190367be2c130dcfb039be94;hpb=a06038369b830bb83742b6b39775f39dd9e69ae2;p=oota-llvm.git diff --git a/lib/Target/MBlaze/MBlazeInstrFormats.td b/lib/Target/MBlaze/MBlazeInstrFormats.td index 71e3b12e8e3..e40432a1b9a 100644 --- a/lib/Target/MBlaze/MBlazeInstrFormats.td +++ b/lib/Target/MBlaze/MBlazeInstrFormats.td @@ -1,4 +1,4 @@ -//===- MBlazeInstrFormats.td - MB Instruction defs ---------*- tablegen -*-===// +//===-- MBlazeInstrFormats.td - MB Instruction defs --------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -15,8 +15,8 @@ class Format val> { } def FPseudo : Format<0>; -def FRRR : Format<1>; // ADD, RSUB, OR, etc. -def FRRI : Format<2>; // ADDI, RSUBI, ORI, etc. +def FRRR : Format<1>; // ADD, OR, etc. +def FRRI : Format<2>; // ADDI, ORI, etc. def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc. def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc. def FRCR : Format<5>; // BRLD, BRALD, GETD @@ -32,7 +32,10 @@ def FCRCX : Format<14>; // PUT def FCX : Format<15>; // TPUT def FCR : Format<16>; // TPUTD def FRIR : Format<17>; // RSUBI -def FC : Format<18>; // NOP +def FRRRR : Format<18>; // RSUB, FRSUB +def FRI : Format<19>; // RSUB, FRSUB +def FC : Format<20>; // NOP +def FRR : Format<21>; // CLZ //===----------------------------------------------------------------------===// // Describe MBlaze instructions format @@ -48,9 +51,8 @@ def FC : Format<18>; // NOP //===----------------------------------------------------------------------===// // Generic MBlaze Format -class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin> : Instruction -{ +class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : Instruction { let Namespace = "MBlaze"; field bits<32> Inst; @@ -59,8 +61,12 @@ class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, bits<6> FormBits = Form.Value; // Top 6 bits are the 'opcode' field - let Inst{0-5} = opcode; - + let Inst{0-5} = opcode; + + // If the instruction is marked as a pseudo, set isCodeGenOnly so that the + // assembler and disassmbler ignore it. + let isCodeGenOnly = !eq(!cast(form), "FPseudo"); + dag OutOperandList = outs; dag InOperandList = ins; @@ -76,22 +82,22 @@ class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, // Pseudo instruction class //===----------------------------------------------------------------------===// class MBlazePseudo pattern>: - MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIPseudo>; + MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>; //===----------------------------------------------------------------------===// // Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|> //===----------------------------------------------------------------------===// class TA op, bits<11> flags, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin> : - MBlazeInst + list pattern, InstrItinClass itin> : + MBlazeInst { bits<5> rd; bits<5> ra; bits<5> rb; let Inst{6-10} = rd; - let Inst{11-15} = ra; + let Inst{11-15} = ra; let Inst{16-20} = rb; let Inst{21-31} = flags; } @@ -101,24 +107,44 @@ class TA op, bits<11> flags, dag outs, dag ins, string asmstr, //===----------------------------------------------------------------------===// class TB op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin> : - MBlazeInst + InstrItinClass itin> : + MBlazeInst { bits<5> rd; bits<5> ra; bits<16> imm16; let Inst{6-10} = rd; - let Inst{11-15} = ra; + let Inst{11-15} = ra; let Inst{16-31} = imm16; } +//===----------------------------------------------------------------------===// +// Type A instruction class in MBlaze but with the operands reversed +// in the LLVM DAG : <|opcode|rd|ra|rb|flags|> +//===----------------------------------------------------------------------===// + +class TAR op, bits<11> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + TA +{ + bits<5> rrd; + bits<5> rrb; + bits<5> rra; + + let Form = FRRRR; + + let rd = rrd; + let ra = rra; + let rb = rrb; +} + //===----------------------------------------------------------------------===// // Type B instruction class in MBlaze but with the operands reversed in // the LLVM DAG : <|opcode|rd|ra|immediate|> //===----------------------------------------------------------------------===// class TBR op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin> : + InstrItinClass itin> : TB { bits<5> rrd; bits<16> rimm16; @@ -130,3 +156,73 @@ class TBR op, dag outs, dag ins, string asmstr, list pattern, let ra = rra; let imm16 = rimm16; } + +//===----------------------------------------------------------------------===// +// Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|> +//===----------------------------------------------------------------------===// +class SHT op, bits<2> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<5> ra; + bits<5> imm5; + + let Inst{6-10} = rd; + let Inst{11-15} = ra; + let Inst{16-20} = 0x0; + let Inst{21-22} = flags; + let Inst{23-26} = 0x0; + let Inst{27-31} = imm5; +} + +//===----------------------------------------------------------------------===// +// Special instruction class in MBlaze : <|opcode|rd|imm14|> +//===----------------------------------------------------------------------===// +class SPC op, bits<2> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<14> imm14; + + let Inst{6-10} = rd; + let Inst{11-15} = 0x0; + let Inst{16-17} = flags; + let Inst{18-31} = imm14; +} + +//===----------------------------------------------------------------------===// +// MSR instruction class in MBlaze : <|opcode|rd|imm15|> +//===----------------------------------------------------------------------===// +class MSR op, bits<6> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<15> imm15; + + let Inst{6-10} = rd; + let Inst{11-16} = flags; + let Inst{17-31} = imm15; +} + +//===----------------------------------------------------------------------===// +// TCLZ instruction class in MBlaze : <|opcode|rd|imm15|> +//===----------------------------------------------------------------------===// +class TCLZ op, bits<16> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<5> ra; + + let Inst{6-10} = rd; + let Inst{11-15} = ra; + let Inst{16-31} = flags; +} + +//===----------------------------------------------------------------------===// +// MBAR instruction class in MBlaze : <|opcode|rd|imm15|> +//===----------------------------------------------------------------------===// +class MBAR op, bits<26> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + let Inst{6-31} = flags; +}