X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMBlaze%2FMBlazeInstrInfo.td;h=f86bc0b0b5a4f32e7a981ca2e7389cc6d44a1ab2;hb=b52980be0788a907c98fc08de090ad61aef86716;hp=990b95da31bc27a34d76a7970fe99fe94e80a550;hpb=6b3bbb149f6a49c9ad9f763c353bc6e7b5c864a1;p=oota-llvm.git diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.td b/lib/Target/MBlaze/MBlazeInstrInfo.td index 990b95da31b..f86bc0b0b5a 100644 --- a/lib/Target/MBlaze/MBlazeInstrInfo.td +++ b/lib/Target/MBlaze/MBlazeInstrInfo.td @@ -1,4 +1,4 @@ -//===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===// +//===-- MBlazeInstrInfo.td - MBlaze Instruction defs -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -28,41 +28,41 @@ def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet, - [SDNPHasChain, SDNPOptInFlag]>; + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def MBlazeIRet : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet, - [SDNPHasChain, SDNPOptInFlag]>; + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink, - [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag, + [SDNPHasChain,SDNPOptInGlue,SDNPOutGlue, SDNPVariadic]>; def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>; def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart, - [SDNPHasChain, SDNPOutFlag]>; + [SDNPHasChain, SDNPOutGlue]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd, - [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; //===----------------------------------------------------------------------===// // MBlaze Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def HasPipe3 : Predicate<"Subtarget.hasPipe3()">; +// def HasPipe3 : Predicate<"Subtarget.hasPipe3()">; def HasBarrel : Predicate<"Subtarget.hasBarrel()">; -def NoBarrel : Predicate<"!Subtarget.hasBarrel()">; +// def NoBarrel : Predicate<"!Subtarget.hasBarrel()">; def HasDiv : Predicate<"Subtarget.hasDiv()">; def HasMul : Predicate<"Subtarget.hasMul()">; -def HasFSL : Predicate<"Subtarget.hasFSL()">; -def HasEFSL : Predicate<"Subtarget.hasEFSL()">; -def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">; -def HasException : Predicate<"Subtarget.hasException()">; +// def HasFSL : Predicate<"Subtarget.hasFSL()">; +// def HasEFSL : Predicate<"Subtarget.hasEFSL()">; +// def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">; +// def HasException : Predicate<"Subtarget.hasException()">; def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">; def HasFPU : Predicate<"Subtarget.hasFPU()">; -def HasESR : Predicate<"Subtarget.hasESR()">; -def HasPVR : Predicate<"Subtarget.hasPVR()">; +// def HasESR : Predicate<"Subtarget.hasESR()">; +// def HasPVR : Predicate<"Subtarget.hasPVR()">; def HasMul64 : Predicate<"Subtarget.hasMul64()">; def HasSqrt : Predicate<"Subtarget.hasSqrt()">; -def HasMMU : Predicate<"Subtarget.hasMMU()">; +// def HasMMU : Predicate<"Subtarget.hasMMU()">; //===----------------------------------------------------------------------===// // MBlaze Operand, Complex Patterns and Transformations Definitions. @@ -170,18 +170,18 @@ class ArithI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : TB; + [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>; class ArithI32 op, string instr_asm,Operand Od, PatLeaf imm_type> : TB; + [], IIC_ALU>; class ShiftI op, bits<2> flags, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : SHT; + [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>; class ArithR op, bits<11> flags, string instr_asm, SDNode OpNode, InstrItinClass itin> : @@ -193,7 +193,7 @@ class ArithRI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : TBR; + [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIC_ALU>; class ArithN op, bits<11> flags, string instr_asm, InstrItinClass itin> : @@ -204,7 +204,7 @@ class ArithN op, bits<11> flags, string instr_asm, class ArithNI op, string instr_asm,Operand Od, PatLeaf imm_type> : TB; + [], IIC_ALU>; class ArithRN op, bits<11> flags, string instr_asm, InstrItinClass itin> : @@ -215,7 +215,7 @@ class ArithRN op, bits<11> flags, string instr_asm, class ArithRNI op, string instr_asm,Operand Od, PatLeaf imm_type> : TBR; + [], IIC_ALU>; //===----------------------------------------------------------------------===// // Misc Arithmetic Instructions @@ -224,46 +224,51 @@ class ArithRNI op, string instr_asm,Operand Od, PatLeaf imm_type> : class Logic op, bits<11> flags, string instr_asm, SDNode OpNode> : TA; + [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIC_ALU>; class LogicI op, string instr_asm, SDNode OpNode> : TB; + IIC_ALU>; class LogicI32 op, string instr_asm> : TB; + [], IIC_ALU>; class PatCmp op, bits<11> flags, string instr_asm> : TA; + [], IIC_ALU>; //===----------------------------------------------------------------------===// // Memory Access Instructions //===----------------------------------------------------------------------===// + +let mayLoad = 1 in { class LoadM op, bits<11> flags, string instr_asm> : TA; + [], IIC_MEMl>; +} class LoadMI op, string instr_asm, PatFrag OpNode> : TB; + [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>; +let mayStore = 1 in { class StoreM op, bits<11> flags, string instr_asm> : TA; + [], IIC_MEMs>; +} class StoreMI op, string instr_asm, PatFrag OpNode> : TB; + [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIC_MEMs>; //===----------------------------------------------------------------------===// // Branch Instructions @@ -271,7 +276,7 @@ class StoreMI op, string instr_asm, PatFrag OpNode> : class Branch op, bits<5> br, bits<11> flags, string instr_asm> : TA { + [], IIC_BR> { let rd = 0x0; let ra = br; let Form = FCCR; @@ -280,7 +285,7 @@ class Branch op, bits<5> br, bits<11> flags, string instr_asm> : class BranchI op, bits<5> br, string instr_asm> : TB { + [], IIC_BR> { let rd = 0; let ra = br; let Form = FCCI; @@ -290,17 +295,17 @@ class BranchI op, bits<5> br, string instr_asm> : // Branch and Link Instructions //===----------------------------------------------------------------------===// class BranchL op, bits<5> br, bits<11> flags, string instr_asm> : - TA { + [], IIC_BRl> { let ra = br; let Form = FRCR; } class BranchLI op, bits<5> br, string instr_asm> : - TB { + [], IIC_BRl> { let ra = br; let Form = FRCI; } @@ -312,7 +317,7 @@ class BranchC op, bits<5> br, bits<11> flags, string instr_asm> : TA { + [], IIC_BRc> { let rd = br; let Form = FCRR; } @@ -320,7 +325,7 @@ class BranchC op, bits<5> br, bits<11> flags, string instr_asm> : class BranchCI op, bits<5> br, string instr_asm> : TB { + [], IIC_BRc> { let rd = br; let Form = FCRI; } @@ -330,71 +335,74 @@ class BranchCI op, bits<5> br, string instr_asm> : //===----------------------------------------------------------------------===// let isCommutable = 1, isAsCheapAsAMove = 1 in { - def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>; + def ADDK : Arith<0x04, 0x000, "addk ", add, IIC_ALU>; def AND : Logic<0x21, 0x000, "and ", and>; def OR : Logic<0x20, 0x000, "or ", or>; def XOR : Logic<0x22, 0x000, "xor ", xor>; - def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">; - def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">; - def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">; + + let Predicates=[HasPatCmp] in { + def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">; + def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">; + def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">; + } let Defs = [CARRY] in { - def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>; + def ADD : Arith<0x00, 0x000, "add ", addc, IIC_ALU>; let Uses = [CARRY] in { - def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>; + def ADDC : Arith<0x02, 0x000, "addc ", adde, IIC_ALU>; } } let Uses = [CARRY] in { - def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>; + def ADDKC : ArithN<0x06, 0x000, "addkc ", IIC_ALU>; } } let isAsCheapAsAMove = 1 in { - def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>; - def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>; - def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>; - def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>; + def ANDN : ArithN<0x23, 0x000, "andn ", IIC_ALU>; + def CMP : ArithN<0x05, 0x001, "cmp ", IIC_ALU>; + def CMPU : ArithN<0x05, 0x003, "cmpu ", IIC_ALU>; + def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIC_ALU>; let Defs = [CARRY] in { - def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>; + def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIC_ALU>; let Uses = [CARRY] in { - def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>; + def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIC_ALU>; } } let Uses = [CARRY] in { - def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>; + def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIC_ALU>; } } let isCommutable = 1, Predicates=[HasMul] in { - def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>; + def MUL : Arith<0x10, 0x000, "mul ", mul, IIC_ALUm>; } let isCommutable = 1, Predicates=[HasMul,HasMul64] in { - def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>; - def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>; + def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIC_ALUm>; + def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIC_ALUm>; } let Predicates=[HasMul,HasMul64] in { - def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>; + def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIC_ALUm>; } let Predicates=[HasBarrel] in { - def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>; - def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>; - def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>; + def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIC_SHT>; + def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIC_SHT>; + def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIC_SHT>; def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>; def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>; def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>; } let Predicates=[HasDiv] in { - def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIAlu>; - def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIAlu>; + def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIC_ALUd>; + def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIC_ALUd>; } //===----------------------------------------------------------------------===// @@ -434,17 +442,19 @@ let Predicates=[HasMul] in { //===----------------------------------------------------------------------===// let canFoldAsLoad = 1, isReMaterializable = 1 in { - def LBU : LoadM<0x30, 0x000, "lbu ">; - def LBUR : LoadM<0x30, 0x200, "lbur ">; + let neverHasSideEffects = 1 in { + def LBU : LoadM<0x30, 0x000, "lbu ">; + def LBUR : LoadM<0x30, 0x200, "lbur ">; - def LHU : LoadM<0x31, 0x000, "lhu ">; - def LHUR : LoadM<0x31, 0x200, "lhur ">; + def LHU : LoadM<0x31, 0x000, "lhu ">; + def LHUR : LoadM<0x31, 0x200, "lhur ">; - def LW : LoadM<0x32, 0x000, "lw ">; - def LWR : LoadM<0x32, 0x200, "lwr ">; + def LW : LoadM<0x32, 0x000, "lw ">; + def LWR : LoadM<0x32, 0x200, "lwr ">; - let Defs = [CARRY] in { - def LWX : LoadM<0x32, 0x400, "lwx ">; + let Defs = [CARRY] in { + def LWX : LoadM<0x32, 0x400, "lwx ">; + } } def LBUI : LoadMI<0x38, "lbui ", zextloadi8>; @@ -552,7 +562,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), "rtsd $target, $imm", [], - IIBranch>; + IIC_BR>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, @@ -560,7 +570,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), "rtid $target, $imm", [], - IIBranch>; + IIC_BR>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, @@ -568,7 +578,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), "rtbd $target, $imm", [], - IIBranch>; + IIC_BR>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, @@ -576,7 +586,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), "rted $target, $imm", [], - IIBranch>; + IIC_BR>; } //===----------------------------------------------------------------------===// @@ -584,9 +594,18 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, //===----------------------------------------------------------------------===// let neverHasSideEffects = 1 in { - def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>; + def NOP : MBlazeInst<0x20, FC, (outs), (ins), "nop ", [], IIC_ALU>; +} + +let Predicates=[HasPatCmp] in { + def CLZ : TCLZ<0x24, 0x00E0, (outs GPR:$dst), (ins GPR:$src), + "clz $dst, $src", [], IIC_ALU>; } +def IMEMBAR : MBAR<0x2E, 0x0420004, (outs), (ins), "mbar 2", [], IIC_ALU>; +def DMEMBAR : MBAR<0x2E, 0x0220004, (outs), (ins), "mbar 1", [], IIC_ALU>; +def IDMEMBAR : MBAR<0x2E, 0x0020004, (outs), (ins), "mbar 0", [], IIC_ALU>; + let usesCustomInserter = 1 in { def Select_CC : MBlazePseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), // F T reversed @@ -611,17 +630,17 @@ let usesCustomInserter = 1 in { let rb = 0 in { def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src), - "sext16 $dst, $src", [], IIAlu>; + "sext16 $dst, $src", [], IIC_ALU>; def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src), - "sext8 $dst, $src", [], IIAlu>; + "sext8 $dst, $src", [], IIC_ALU>; let Defs = [CARRY] in { def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src), - "srl $dst, $src", [], IIAlu>; + "srl $dst, $src", [], IIC_ALU>; def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src), - "sra $dst, $src", [], IIAlu>; + "sra $dst, $src", [], IIC_ALU>; let Uses = [CARRY] in { def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src), - "src $dst, $src", [], IIAlu>; + "src $dst, $src", [], IIC_ALU>; } } } @@ -637,36 +656,36 @@ let isCodeGenOnly=1 in { //===----------------------------------------------------------------------===// let Form=FRCS in { def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src), - "mfs $dst, $src", [], IIAlu>; + "mfs $dst, $src", [], IIC_ALU>; } let Form=FCRCS in { def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src), - "mts $dst, $src", [], IIAlu>; + "mts $dst, $src", [], IIC_ALU>; } def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), - "msrset $dst, $set", [], IIAlu>; + "msrset $dst, $set", [], IIC_ALU>; def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr), - "msrclr $dst, $clr", [], IIAlu>; + "msrclr $dst, $clr", [], IIC_ALU>; let rd=0x0, Form=FCRR in { def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), - "wdc $a, $b", [], IIAlu>; + "wdc $a, $b", [], IIC_WDC>; def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b), - "wdc.flush $a, $b", [], IIAlu>; + "wdc.flush $a, $b", [], IIC_WDC>; def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b), - "wdc.clear $a, $b", [], IIAlu>; + "wdc.clear $a, $b", [], IIC_WDC>; def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b), - "wic $a, $b", [], IIAlu>; + "wic $a, $b", [], IIC_WDC>; } def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">; def BRKI : BranchLI<0x2E, 0x0C, "brki ">; def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), - "imm $imm", [], IIAlu>; + "imm $imm", [], IIC_ALU>; //===----------------------------------------------------------------------===// // Pseudo instructions for atomic operations @@ -714,7 +733,7 @@ let usesCustomInserter=1 in { //===----------------------------------------------------------------------===// // Small immediates -def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>; +def : Pat<(i32 0), (ADDK (i32 R0), (i32 R0))>; def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>; def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>; @@ -741,6 +760,56 @@ def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>; def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>; // SET_CC operations +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETEQ), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 1)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETNE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 2)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 3)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 4)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 5)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 6)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU (i32 R0), GPR:$L), 3)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU (i32 R0), GPR:$L), 4)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU (i32 R0), GPR:$L), 5)>; +def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU (i32 R0), GPR:$L), 6)>; + +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETEQ), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 1)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETNE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 2)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETGT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 3)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 4)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETGE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 5)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 6)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETUGT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU GPR:$R, (i32 R0)), 3)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETULT), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU GPR:$R, (i32 R0)), 4)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETUGE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU GPR:$R, (i32 R0)), 5)>; +def : Pat<(setcc (i32 0), (i32 GPR:$R), SETULE), + (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), + (CMPU GPR:$R, (i32 R0)), 6)>; + def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), (CMP GPR:$R, GPR:$L), 1)>; @@ -777,6 +846,68 @@ def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)), (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>; // SELECT_CC +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETEQ), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 1)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETNE), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 2)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETGT), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 3)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETLT), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 4)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETGE), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 5)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETLE), + (Select_CC GPR:$T, GPR:$F, GPR:$L, 6)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETUGT), + (Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 3)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETULT), + (Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 4)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETUGE), + (Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 5)>; +def : Pat<(selectcc (i32 GPR:$L), (i32 0), + (i32 GPR:$T), (i32 GPR:$F), SETULE), + (Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 6)>; + +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETEQ), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 1)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETNE), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 2)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETGT), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 3)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETLT), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 4)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETGE), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 5)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETLE), + (Select_CC GPR:$T, GPR:$F, GPR:$R, 6)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETUGT), + (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 3)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETULT), + (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 4)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETUGE), + (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 5)>; +def : Pat<(selectcc (i32 0), (i32 GPR:$R), + (i32 GPR:$T), (i32 GPR:$F), SETULE), + (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 6)>; + def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), (i32 GPR:$T), (i32 GPR:$F), SETEQ), (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 1)>; @@ -817,6 +948,48 @@ def : Pat<(br bb:$T), (BRID bb:$T)>; def : Pat<(brind GPR:$T), (BRAD GPR:$T)>; // BRCOND instructions +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETEQ), bb:$T), + (BEQID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETNE), bb:$T), + (BNEID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETGT), bb:$T), + (BGTID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLT), bb:$T), + (BLTID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETGE), bb:$T), + (BGEID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLE), bb:$T), + (BLEID GPR:$L, bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETUGT), bb:$T), + (BGTID (CMPU (i32 R0), GPR:$L), bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETULT), bb:$T), + (BLTID (CMPU (i32 R0), GPR:$L), bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETUGE), bb:$T), + (BGEID (CMPU (i32 R0), GPR:$L), bb:$T)>; +def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETULE), bb:$T), + (BLEID (CMPU (i32 R0), GPR:$L), bb:$T)>; + +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETEQ), bb:$T), + (BEQID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETNE), bb:$T), + (BNEID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETGT), bb:$T), + (BGTID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLT), bb:$T), + (BLTID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETGE), bb:$T), + (BGEID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLE), bb:$T), + (BLEID GPR:$R, bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETUGT), bb:$T), + (BGTID (CMPU GPR:$R, (i32 R0)), bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETULT), bb:$T), + (BLTID (CMPU GPR:$R, (i32 R0)), bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETUGE), bb:$T), + (BGEID (CMPU GPR:$R, (i32 R0)), bb:$T)>; +def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETULE), bb:$T), + (BLEID (CMPU GPR:$R, (i32 R0)), bb:$T)>; + def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T), (BEQID (CMP GPR:$R, GPR:$L), bb:$T)>; def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T), @@ -848,11 +1021,6 @@ def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>; // Misc instructions def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>; -// Arithmetic with immediates -def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDIK GPR:$in, imm:$imm)>; -def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>; -def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>; - // Convert any extend loads into zero extend loads def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>; def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>; @@ -864,16 +1032,19 @@ def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>; def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>; // 16-bit load and store -def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>; +def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$ad), (SH GPR:$dst, xaddr:$ad)>; def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>; // 8-bit load and store -def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>; +def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$ad), (SB GPR:$dst, xaddr:$ad)>; def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>; // Peepholes def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>; +// Atomic fence +def : Pat<(atomic_fence (imm), (imm)), (MEMBARRIER)>; + //===----------------------------------------------------------------------===// // Floating Point Support //===----------------------------------------------------------------------===//