X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMSP430%2FMSP430RegisterInfo.cpp;h=aed46a2ec595e53b49c964de7a7b6c6845362865;hb=fef904d0e824a2c587f8c1063b6c4fbf47fec898;hp=b40cca988d9a07abff9082f2bfd11823522a5281;hpb=3a4fbcfd330de43011550079f811d92f741a08a1;p=oota-llvm.git diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp index b40cca988d9..aed46a2ec59 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===// +//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===// // // The LLVM Compiler Infrastructure // @@ -13,77 +13,229 @@ #define DEBUG_TYPE "msp430-reg-info" -#include "MSP430.h" #include "MSP430RegisterInfo.h" +#include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" +#include "MSP430TargetMachine.h" +#include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" +#include "llvm/Support/ErrorHandling.h" + +#define GET_REGINFO_TARGET_DESC +#include "MSP430GenRegisterInfo.inc" using namespace llvm; // FIXME: Provide proper call frame setup / destroy opcodes. -MSP430RegisterInfo::MSP430RegisterInfo(const TargetInstrInfo &tii) - : MSP430GenRegisterInfo(MSP430::NOP, MSP430::NOP), - TII(tii) {} +MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, + const TargetInstrInfo &tii) + : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) { + StackAlign = TM.getFrameLowering()->getStackAlignment(); +} -const unsigned* +const uint16_t* MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - assert(0 && "Not implemented yet!"); -} + const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering(); + const Function* F = MF->getFunction(); + static const uint16_t CalleeSavedRegs[] = { + MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, + MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + 0 + }; + static const uint16_t CalleeSavedRegsFP[] = { + MSP430::R5W, MSP430::R6W, MSP430::R7W, + MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + 0 + }; + static const uint16_t CalleeSavedRegsIntr[] = { + MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, + MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, + 0 + }; + static const uint16_t CalleeSavedRegsIntrFP[] = { + MSP430::R5W, MSP430::R6W, MSP430::R7W, + MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, + 0 + }; + + if (TFI->hasFP(*MF)) + return (F->getCallingConv() == CallingConv::MSP430_INTR ? + CalleeSavedRegsIntrFP : CalleeSavedRegsFP); + else + return (F->getCallingConv() == CallingConv::MSP430_INTR ? + CalleeSavedRegsIntr : CalleeSavedRegs); -const TargetRegisterClass* const* -MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { - assert(0 && "Not implemented yet!"); } -BitVector -MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { +BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - - // Mark 4 special registers as reserved. - Reserved.set(MSP430::PC); - Reserved.set(MSP430::SP); - Reserved.set(MSP430::SR); - Reserved.set(MSP430::CG); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + + // Mark 4 special registers with subregisters as reserved. + Reserved.set(MSP430::PCB); + Reserved.set(MSP430::SPB); + Reserved.set(MSP430::SRB); + Reserved.set(MSP430::CGB); + Reserved.set(MSP430::PCW); + Reserved.set(MSP430::SPW); + Reserved.set(MSP430::SRW); + Reserved.set(MSP430::CGW); // Mark frame pointer as reserved if needed. - if (hasFP(MF)) - Reserved.set(MSP430::FP); + if (TFI->hasFP(MF)) + Reserved.set(MSP430::FPW); return Reserved; } -bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const { - return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); +const TargetRegisterClass * +MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) + const { + return &MSP430::GR16RegClass; +} + +void MSP430RegisterInfo:: +eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + + if (!TFI->hasReservedCallFrame(MF)) { + // If the stack pointer can be changed after prologue, turn the + // adjcallstackup instruction into a 'sub SPW, ' and the + // adjcallstackdown instruction into 'add SPW, ' + // TODO: consider using push / pop instead of sub + store / add + MachineInstr *Old = I; + uint64_t Amount = Old->getOperand(0).getImm(); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; + + MachineInstr *New = 0; + if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) { + New = BuildMI(MF, Old->getDebugLoc(), + TII.get(MSP430::SUB16ri), MSP430::SPW) + .addReg(MSP430::SPW).addImm(Amount); + } else { + assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode()); + // factor out the amount the callee already popped. + uint64_t CalleeAmt = Old->getOperand(1).getImm(); + Amount -= CalleeAmt; + if (Amount) + New = BuildMI(MF, Old->getDebugLoc(), + TII.get(MSP430::ADD16ri), MSP430::SPW) + .addReg(MSP430::SPW).addImm(Amount); + } + + if (New) { + // The SRW implicit def is dead. + New->getOperand(3).setIsDead(); + + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } + } + } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) { + // If we are performing frame pointer elimination and if the callee pops + // something off the stack pointer, add it back. + if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { + MachineInstr *Old = I; + MachineInstr *New = + BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri), + MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt); + // The SRW implicit def is dead. + New->getOperand(3).setIsDead(); + + MBB.insert(I, New); + } + } + + MBB.erase(I); } void MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { - assert(0 && "Not implemented yet!"); + assert(SPAdj == 0 && "Unexpected"); + + unsigned i = 0; + MachineInstr &MI = *II; + MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + DebugLoc dl = MI.getDebugLoc(); + while (!MI.getOperand(i).isFI()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + + int FrameIndex = MI.getOperand(i).getIndex(); + + unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW); + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); + + // Skip the saved PC + Offset += 2; + + if (!TFI->hasFP(MF)) + Offset += MF.getFrameInfo()->getStackSize(); + else + Offset += 2; // Skip the saved FPW + + // Fold imm into offset + Offset += MI.getOperand(i+1).getImm(); + + if (MI.getOpcode() == MSP430::ADD16ri) { + // This is actually "load effective address" of the stack slot + // instruction. We have only two-address instructions, thus we need to + // expand it into mov + add + + MI.setDesc(TII.get(MSP430::MOV16rr)); + MI.getOperand(i).ChangeToRegister(BasePtr, false); + + if (Offset == 0) + return; + + // We need to materialize the offset via add instruction. + unsigned DstReg = MI.getOperand(0).getReg(); + if (Offset < 0) + BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) + .addReg(DstReg).addImm(-Offset); + else + BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) + .addReg(DstReg).addImm(Offset); + + return; + } + + MI.getOperand(i).ChangeToRegister(BasePtr, false); + MI.getOperand(i+1).ChangeToImmediate(Offset); } -void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const { - assert(0 && "Not implemented yet!"); -} - -void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - assert(0 && "Not implemented yet!"); -} - -unsigned MSP430RegisterInfo::getRARegister() const { - assert(0 && "Not implemented yet!"); +void +MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) + const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + + // Create a frame entry for the FPW register that must be saved. + if (TFI->hasFP(MF)) { + int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true); + (void)FrameIdx; + assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && + "Slot for FPW register must be last in order to be found!"); + } } -unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const { - assert(0 && "Not implemented yet!"); -} +unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); -int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - assert(0 && "Not implemented yet!"); + return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; } - -#include "MSP430GenRegisterInfo.inc"