X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMips16InstrFormats.td;h=da3a1f114af39f9b5e454ee3f715a6c9069dc151;hb=bec8cee98120d48bc94f08d8921d8f5d6ad0ac9a;hp=3672ea8b9492b2ed7ec77f768e7ad153cfeb370e;hpb=4a5a8949cd15bab98c6d73754b4d6376b34ee8af;p=oota-llvm.git diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index 3672ea8b949..da3a1f114af 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -14,10 +14,10 @@ // // funct or f Function field // -// immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or +// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or // or imm address displacement // -// op 5-bit major operation code +// op 5-bit major operation code // // rx 3-bit source or destination register // @@ -29,52 +29,16 @@ // //===----------------------------------------------------------------------===// -// Format specifies the encoding used by the instruction. This is part of the -// ad-hoc solution used to emit machine instruction encodings by our machine -// code emitter. -// -class Format16 val> { - bits<5> Value = val; -} - -def Pseudo16 : Format16<0>; -def FrmI16 : Format16<1>; -def FrmRI16 : Format16<2>; -def FrmRR16 : Format16<3>; -def FrmRRI16 : Format16<4>; -def FrmRRR16 : Format16<5>; -def FrmRRI_A16 : Format16<6>; -def FrmSHIFT16 : Format16<7>; -def FrmI8_TYPE16 : Format16<8>; -def FrmI8_MOVR3216 : Format16<9>; -def FrmI8_MOV32R16 : Format16<10>; -def FrmI8_SVRS16 : Format16<11>; -def FrmJAL16 : Format16<12>; -def FrmJALX16 : Format16<13>; -def FrmEXT_I16 : Format16<14>; -def FrmASMACRO16 : Format16<15>; -def FrmEXT_RI16 : Format16<16>; -def FrmEXT_RRI16 : Format16<17>; -def FrmEXT_RRI_A16 : Format16<18>; -def FrmEXT_SHIFT16 : Format16<19>; -def FrmEXT_I816 : Format16<20>; -def FrmEXT_I8_SVRS16 : Format16<21>; -def FrmOther16 : Format16<22>; // Instruction w/ a custom format -// Generic Mips 16 Format -class MipsInst16 pattern, - InstrItinClass itin, Format16 f>: Instruction +// Base class for Mips 16 Format +// This class does not depend on the instruction size +// +class MipsInst16_Base pattern, + InstrItinClass itin>: Instruction { - field bits<16> Inst; - Format16 Form = f; let Namespace = "Mips"; - bits<5> Opcode = 0; - - // Top 6 bits are the 'opcode' field - let Inst{15-11} = Opcode; - let OutOperandList = outs; let InOperandList = ins; @@ -82,68 +46,63 @@ class MipsInst16 pattern, let Pattern = pattern; let Itinerary = itin; - // - // Attributes specific to Mips instructions... - // - bits<5> FormBits = Form.Value; - - // TSFlags layout should be kept in sync with MipsInstrInfo.h. - let TSFlags{4-0} = FormBits; + let Predicates = [InMips16Mode]; } // -// TBD. Maybe MipsInst16 and Mips16_EXTEND should be derived from a single -// base class +// Generic Mips 16 Format // - -class MipsInst16_EXTEND pattern, - InstrItinClass itin, Format16 f>: Instruction +class MipsInst16 pattern, + InstrItinClass itin>: + MipsInst16_Base { - field bits<32> Inst; - Format16 Form = f; - - let Namespace = "Mips"; - + field bits<16> Inst; bits<5> Opcode = 0; - bits<5> extend; - // Top 6 bits are the 'opcode' field - let Inst{31-27} = extend; + // Top 5 bits are the 'opcode' field let Inst{15-11} = Opcode; - let OutOperandList = outs; - let InOperandList = ins; + let Size=2; + field bits<16> SoftFail = 0; +} - let AsmString = asmstr; - let Pattern = pattern; - let Itinerary = itin; +// +// For 32 bit extended instruction forms. +// +class MipsInst16_32 pattern, + InstrItinClass itin>: + MipsInst16_Base +{ + field bits<32> Inst; - // - // Attributes specific to Mips instructions... - // - bits<5> FormBits = Form.Value; + let Size=4; + field bits<32> SoftFail = 0; +} - // TSFlags layout should be kept in sync with MipsInstrInfo.h. - let TSFlags{4-0} = FormBits; +class MipsInst16_EXTEND pattern, + InstrItinClass itin>: + MipsInst16_32 +{ + let Inst{31-27} = 0b11110; } // Mips Pseudo Instructions Format class MipsPseudo16 pattern>: - MipsInst16 { + MipsInst16 { let isCodeGenOnly = 1; let isPseudo = 1; } //===----------------------------------------------------------------------===// -// Format I instruction class in Mips : <|opcode|immediate|> +// Format I instruction class in Mips : <|opcode|imm11|> //===----------------------------------------------------------------------===// class FI16 op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin>: MipsInst16 + InstrItinClass itin>: + MipsInst16 { bits<11> imm11; @@ -153,12 +112,12 @@ class FI16 op, dag outs, dag ins, string asmstr, list pattern, } //===----------------------------------------------------------------------===// -// Format RI instruction class in Mips : <|opcode|rx|immed|> +// Format RI instruction class in Mips : <|opcode|rx|imm8|> //===----------------------------------------------------------------------===// class FRI16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<8> imm8; @@ -175,7 +134,7 @@ class FRI16 op, dag outs, dag ins, string asmstr, class FRR16 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -189,13 +148,90 @@ class FRR16 _funct, dag outs, dag ins, string asmstr, let Inst{4-0} = funct; } +class FRRBreak16 pattern, InstrItinClass itin>: + MipsInst16 +{ + bits<6> Code; + bits<5> funct; + + let Opcode = 0b11101; + let funct = 0b00101; + + let Inst{10-5} = Code; + let Inst{4-0} = funct; +} + +// +// For conversion functions. +// +class FRR_SF16 _funct, bits<3> _subfunct, dag outs, dag ins, + string asmstr, list pattern, InstrItinClass itin>: + MipsInst16 +{ + bits<3> rx; + bits<3> subfunct; + bits<5> funct; + + let Opcode = 0b11101; // RR + let funct = _funct; + let subfunct = _subfunct; + + let Inst{10-8} = rx; + let Inst{7-5} = subfunct; + let Inst{4-0} = funct; +} + +// +// just used for breakpoint (hardware and software) instructions. +// +class FC16 _funct, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin>: + MipsInst16 +{ + bits<6> _code; // code is a keyword in tablegen + bits<5> funct; + + let Opcode = 0b11101; // RR + let funct = _funct; + + let Inst{10-5} = _code; + let Inst{4-0} = funct; +} + +// +// J(AL)R(C) subformat +// +class FRR16_JALRC _nd, bits<1> _l, bits<1> r_a, + dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin>: + MipsInst16 +{ + bits<3> rx; + bits<1> nd; + bits<1> l; + bits<1> ra; + + let nd = _nd; + let l = _l; + let ra = r_a; + + let Opcode = 0b11101; + + let Inst{10-8} = rx; + let Inst{7} = nd; + let Inst{6} = l; + let Inst{5} = ra; + let Inst{4-0} = 0; +} + //===----------------------------------------------------------------------===// -// Format RRI instruction class in Mips : <|opcode|rx|ry|immed|> +// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> //===----------------------------------------------------------------------===// class FRRI16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -213,16 +249,16 @@ class FRRI16 op, dag outs, dag ins, string asmstr, // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|> //===----------------------------------------------------------------------===// -class FRRR16 op, bits<2> _f, dag outs, dag ins, string asmstr, +class FRRR16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; bits<3> rz; bits<2> f; - let Opcode = op; + let Opcode = 0b11100; let f = _f; let Inst{10-8} = rx; @@ -232,19 +268,19 @@ class FRRR16 op, bits<2> _f, dag outs, dag ins, string asmstr, } //===----------------------------------------------------------------------===// -// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|immed|> +// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|> //===----------------------------------------------------------------------===// -class FRRI_A16 op, bits<1> _f, dag outs, dag ins, string asmstr, +class FRRI_A16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; bits<1> f; bits<4> imm4; - let Opcode = op; + let Opcode = 0b01000; let f = _f; let Inst{10-8} = rx; @@ -257,16 +293,16 @@ class FRRI_A16 op, bits<1> _f, dag outs, dag ins, string asmstr, // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|> //===----------------------------------------------------------------------===// -class FSHIFT16 op, bits<2> _f, dag outs, dag ins, string asmstr, +class FSHIFT16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; bits<3> sa; bits<2> f; - let Opcode = op; + let Opcode = 0b00110; let f = _f; let Inst{10-8} = rx; @@ -276,170 +312,157 @@ class FSHIFT16 op, bits<2> _f, dag outs, dag ins, string asmstr, } //===----------------------------------------------------------------------===// -// Format i8 instruction class in Mips : <|opcode|funct|immed> +// Format i8 instruction class in Mips : <|opcode|funct|imm8> //===----------------------------------------------------------------------===// -class FI816 op, bits<3> _func, dag outs, dag ins, string asmstr, +class FI816 _func, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> func; - bits<8> immed8; - - let Opcode = op; + bits<8> imm8; + + let Opcode = 0b01100; let func = _func; let Inst{10-8} = func; - let Inst{7-0} = immed8; + let Inst{7-0} = imm8; } //===----------------------------------------------------------------------===// // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32> //===----------------------------------------------------------------------===// -class FI8_MOVR3216 op, bits<3> _func, dag outs, dag ins, string asmstr, +class FI8_MOVR3216 pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { - bits<3> func; bits<4> ry; bits<4> r32; - - let Opcode = op; - let func = _func; - let Inst{10-8} = func; + let Opcode = 0b01100; + + let Inst{10-8} = 0b111; let Inst{7-4} = ry; let Inst{3-0} = r32; - + } //===----------------------------------------------------------------------===// -// Format i8_MOV32R instruction class in Mips : <|opcode|func|ry|r32> +// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz> //===----------------------------------------------------------------------===// -class FI8_MOV32R16 op, bits<3> _func, dag outs, dag ins, string asmstr, +class FI8_MOV32R16 pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> func; bits<5> r32; bits<3> rz; - - let Opcode = op; - let func = _func; - let Inst{10-8} = func; - let Inst{7-5} = r32{2-0}; + let Opcode = 0b01100; + + let Inst{10-8} = 0b101; + let Inst{7-5} = r32{2-0}; let Inst{4-3} = r32{4-3}; let Inst{2-0} = rz; - + } //===----------------------------------------------------------------------===// -// Format i8_SVRS instruction class in Mips : +// Format i8_SVRS instruction class in Mips : // <|opcode|svrs|s|ra|s0|s1|framesize> //===----------------------------------------------------------------------===// -class FI8_SVRS16 op, bits<3> _SVRS, dag outs, dag ins, string asmstr, +class FI8_SVRS16 _s, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { - bits<3> SVRS; bits<1> s; - bits<1> ra; - bits<1> s0; - bits<1> s1; - bits<4> framesize; - - let Opcode = op; - let SVRS = _SVRS; + bits<1> ra = 0; + bits<1> s0 = 0; + bits<1> s1 = 0; + bits<4> framesize = 0; - let Inst{10-8} = SVRS; + let s =_s; + let Opcode = 0b01100; + + let Inst{10-8} = 0b100; let Inst{7} = s; let Inst{6} = ra; let Inst{5} = s0; let Inst{4} = s1; let Inst{3-0} = framesize; - + } //===----------------------------------------------------------------------===// -// Format JAL instruction class in Mips16 : +// Format JAL instruction class in Mips16 : // <|opcode|svrs|s|ra|s0|s1|framesize> //===----------------------------------------------------------------------===// -class FJAL16 op, bits<1> _X, dag outs, dag ins, string asmstr, +class FJAL16 _X, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_32 { bits<1> X; - bits<26> immed26; + bits<26> imm26; + - - let Opcode = op; let X = _X; + let Inst{31-27} = 0b00011; let Inst{26} = X; - let Inst{25-21} = immed26{20-16}; - let Inst{20-16} = immed26{25-21}; - let Inst{15-0} = immed26{15-0}; - -} + let Inst{25-21} = imm26{20-16}; + let Inst{20-16} = imm26{25-21}; + let Inst{15-0} = imm26{15-0}; +} //===----------------------------------------------------------------------===// -// Format EXT-I instruction class in Mips16 : -// <|opcode|immed10:5|immed15:1|op|0|0|0|0|0|0|immed4:0> +// Format EXT-I instruction class in Mips16 : +// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0> //===----------------------------------------------------------------------===// -class FEXT_I16 op, bits<5> _eop, dag outs, dag ins, string asmstr, +class FEXT_I16 _eop, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<16> immed16; + bits<16> imm16; bits<5> eop; - - let Opcode = op; + let eop = _eop; - let Inst{26-21} = immed16{10-5}; - let Inst{20-16} = immed16{15-11}; + let Inst{26-21} = imm16{10-5}; + let Inst{20-16} = imm16{15-11}; let Inst{15-11} = eop; let Inst{10-5} = 0; - let Inst{4-0} = immed16{4-0}; - -} - - - - + let Inst{4-0} = imm16{4-0}; +} //===----------------------------------------------------------------------===// -// Format ASMACRO instruction class in Mips16 : +// Format ASMACRO instruction class in Mips16 : // //===----------------------------------------------------------------------===// -class FASMACRO16 op, dag outs, dag ins, string asmstr, +class FASMACRO16 pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<3> select; bits<3> p4; bits<5> p3; - bits<5> RRR; + bits<5> RRR = 0b11100; bits<3> p2; bits<3> p1; bits<5> p0; - - let Opcode = op; + let Inst{26-24} = select; let Inst{23-21} = p4; @@ -447,170 +470,158 @@ class FASMACRO16 op, dag outs, dag ins, string asmstr, let Inst{15-11} = RRR; let Inst{10-8} = p2; let Inst{7-5} = p1; - let Inst{4-0} = p0; - + let Inst{4-0} = p0; + } //===----------------------------------------------------------------------===// -// Format EXT-RI instruction class in Mips16 : -// <|opcode|immed10:5|immed15:11|op|rx|0|0|0|immed4:0> +// Format EXT-RI instruction class in Mips16 : +// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> //===----------------------------------------------------------------------===// -class FEXT_RI16 op, bits<5> _eop, dag outs, dag ins, string asmstr, +class FEXT_RI16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<16> immed16; - bits<5> eop; + bits<16> imm16; + bits<5> op; bits<3> rx; - - let Opcode = op; - let eop = _eop; - let Inst{26-21} = immed16{10-5}; - let Inst{20-16} = immed16{15-11}; - let Inst{15-11} = eop; + let op = _op; + + let Inst{26-21} = imm16{10-5}; + let Inst{20-16} = imm16{15-11}; + let Inst{15-11} = op; let Inst{10-8} = rx; let Inst{7-5} = 0; - let Inst{4-0} = immed16{4-0}; - + let Inst{4-0} = imm16{4-0}; + } //===----------------------------------------------------------------------===// // Format EXT-RRI instruction class in Mips16 : -// <|opcode|immed10:5|immed15:11|op|rx|ry|immed4:0> +// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0> //===----------------------------------------------------------------------===// -class FEXT_RRI16 op, bits<5> _eop, dag outs, dag ins, string asmstr, +class FEXT_RRI16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<16> immed16; - bits<5> eop; + bits<5> op; + bits<16> imm16; bits<3> rx; bits<3> ry; - - let Opcode = op; - let eop = _eop; - let Inst{26-21} = immed16{10-5}; - let Inst{20-16} = immed16{15-11}; - let Inst{15-11} = eop; + let op=_op; + + let Inst{26-21} = imm16{10-5}; + let Inst{20-16} = imm16{15-11}; + let Inst{15-11} = op; let Inst{10-8} = rx; let Inst{7-5} = ry; - let Inst{4-0} = immed16{4-0}; - + let Inst{4-0} = imm16{4-0}; + } //===----------------------------------------------------------------------===// -// Format EXT-RRI-A instruction class in Mips16 : -// <|opcode|immed10:4|immed14:11|RRI-A|rx|ry|f|immed3:0> +// Format EXT-RRI-A instruction class in Mips16 : +// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0> //===----------------------------------------------------------------------===// -class FEXT_RRI_A16 op, bits<1> _f, dag outs, dag ins, string asmstr, +class FEXT_RRI_A16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<15> immed15; - bits<5> RRI_A; + bits<15> imm15; bits<3> rx; bits<3> ry; bits<1> f; - - let Opcode = op; + let f = _f; - let Inst{26-20} = immed15{10-4}; - let Inst{19-16} = immed15{14-11}; - let Inst{15-11} = RRI_A; + let Inst{26-20} = imm15{10-4}; + let Inst{19-16} = imm15{14-11}; + let Inst{15-11} = 0b01000; let Inst{10-8} = rx; let Inst{7-5} = ry; let Inst{4} = f; - let Inst{3-0} = immed15{3-0}; - + let Inst{3-0} = imm15{3-0}; + } //===----------------------------------------------------------------------===// -// Format EXT-SHIFT instruction class in Mips16 : -// <|opcode|sa 4:0|s5|0|SHIFT|rx|ry|0|f> +// Format EXT-SHIFT instruction class in Mips16 : +// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f> //===----------------------------------------------------------------------===// -class FEXT_SHIFT16 op, bits<2> _f, dag outs, dag ins, string asmstr, +class FEXT_SHIFT16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<6> sa6; - bits<5> shift; bits<3> rx; bits<3> ry; bits<2> f; - - let Opcode = op; + let f = _f; let Inst{26-22} = sa6{4-0}; let Inst{21} = sa6{5}; let Inst{20-16} = 0; - let Inst{15-11} = shift; + let Inst{15-11} = 0b00110; let Inst{10-8} = rx; let Inst{7-5} = ry; let Inst{4-2} = 0; - let Inst{1-0} = f; - + let Inst{1-0} = f; + } //===----------------------------------------------------------------------===// -// Format EXT-I8 instruction class in Mips16 : -// <|opcode|immed10:5|immed15:11|I8|funct|0|immed4:0> +// Format EXT-I8 instruction class in Mips16 : +// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0> //===----------------------------------------------------------------------===// -class FEXT_I816 op, bits<3> _funct, dag outs, dag ins, string asmstr, +class FEXT_I816 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<16> immed16; + bits<16> imm16; bits<5> I8; bits<3> funct; - - let Opcode = op; + let funct = _funct; + let I8 = 0b0110; - let Inst{26-21} = immed16{10-5}; - let Inst{20-16} = immed16{15-11}; + let Inst{26-21} = imm16{10-5}; + let Inst{20-16} = imm16{15-11}; let Inst{15-11} = I8; let Inst{10-8} = funct; let Inst{7-5} = 0; - let Inst{4-0} = immed16{4-0}; - + let Inst{4-0} = imm16{4-0}; + } //===----------------------------------------------------------------------===// -// Format EXT-I8_SVRS instruction class in Mips16 : -// <|opcode|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> +// Format EXT-I8_SVRS instruction class in Mips16 : +// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> //===----------------------------------------------------------------------===// -class FEXT_I8_SVRS16 op, dag outs, dag ins, string asmstr, +class FEXT_I8_SVRS16 s_, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { - bits<3> xsregs; - bits<8> framesize; - bits<3> aregs; - bits<5> I8; - bits<3> SVRS; + bits<3> xsregs =0; + bits<8> framesize =0; + bits<3> aregs =0; + bits<5> I8 = 0b01100; + bits<3> SVRS = 0b100; bits<1> s; - bits<1> ra; - bits<1> s0; - bits<1> s1; - - let Opcode = op; + bits<1> ra = 0; + bits<1> s0 = 0; + bits<1> s1 = 0; + + let s= s_; let Inst{26-24} = xsregs; let Inst{23-20} = framesize{7-4}; @@ -623,9 +634,7 @@ class FEXT_I8_SVRS16 op, dag outs, dag ins, string asmstr, let Inst{5} = s0; let Inst{4} = s1; let Inst{3-0} = framesize{3-0}; - - -} +}