X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsCondMov.td;h=559370bc2a107fed69563bb62796e72ca596c946;hb=398db9368d72d1d60d40b2e18c16ca2c14aa7f39;hp=5e21d4dc2bea31ce53b0497a845a001c51debc6b;hpb=c567b1cd0d6bf973a21df4b5c8cae37e5e7518f8;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index 5e21d4dc2be..559370bc2a1 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -16,11 +16,10 @@ // MipsISelLowering::EmitInstrWithCustomInserter if target does not have // conditional move instructions. // cond:int, data:int -class CondMovIntInt funct, - string instr_asm> : - FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), - !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> { - let shamt = 0; +class CMov_I_I_FT : + InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), + !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> { let Constraints = "$F = $rd"; } @@ -102,26 +101,34 @@ multiclass MovnPats; +def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegs, CPURegs, NoItinerary>, + ADD_FM<0, 0xa>; let Predicates = [HasStdEnc], DecoderNamespace = "Mips64" in { - def MOVZ_I_I64 : CondMovIntInt; - def MOVZ_I64_I : CondMovIntInt { + def MOVZ_I_I64 : CMov_I_I_FT<"movz", CPURegs, CPU64Regs, NoItinerary>, + ADD_FM<0, 0xa>; + def MOVZ_I64_I : CMov_I_I_FT<"movz", CPU64Regs, CPURegs, NoItinerary>, + ADD_FM<0, 0xa> { let isCodeGenOnly = 1; } - def MOVZ_I64_I64 : CondMovIntInt { + def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64Regs, CPU64Regs, NoItinerary>, + ADD_FM<0, 0xa> { let isCodeGenOnly = 1; } } -def MOVN_I_I : CondMovIntInt; +def MOVN_I_I : CMov_I_I_FT<"movn", CPURegs, CPURegs, NoItinerary>, + ADD_FM<0, 0xb>; let Predicates = [HasStdEnc], DecoderNamespace = "Mips64" in { - def MOVN_I_I64 : CondMovIntInt; - def MOVN_I64_I : CondMovIntInt { + def MOVN_I_I64 : CMov_I_I_FT<"movn", CPURegs, CPU64Regs, NoItinerary>, + ADD_FM<0, 0xb>; + def MOVN_I64_I : CMov_I_I_FT<"movn", CPU64Regs, CPURegs, NoItinerary>, + ADD_FM<0, 0xb> { let isCodeGenOnly = 1; } - def MOVN_I64_I64 : CondMovIntInt { + def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64Regs, CPU64Regs, NoItinerary>, + ADD_FM<0, 0xb> { let isCodeGenOnly = 1; } }