X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsInstrFormats.td;h=9f55fb38b959c23f908593e52deae3ae862135a2;hb=bdd83fe382d6c3d6fc73aa7142e73f30cbd4dfad;hp=bda63629f31ac95ede1947f4c61a9d5b7203747b;hpb=64d80e3387f328d21cd9cc06464b5de7861e3f27;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index bda63629f31..9f55fb38b95 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -1,16 +1,16 @@ -//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===// +//===- MipsInstrFormats.td - Mips Instruction Formats ------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // -// This file was developed by Bruno Cardoso Lopes and is distributed under the -// University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Describe MIPS instructions format // -// All the possible Mips fields are: +// CPU INSTRUCTION FORMATS // // opcode - operation code. // rs - src reg. @@ -22,8 +22,8 @@ //===----------------------------------------------------------------------===// // Generic Mips Format -class MipsInst pattern>: - Instruction +class MipsInst pattern, + InstrItinClass itin>: Instruction { field bits<32> Inst; @@ -32,22 +32,27 @@ class MipsInst pattern>: bits<6> opcode; // Top 5 bits are the 'opcode' field - let Inst{31-26} = opcode; - + let Inst{31-26} = opcode; + dag OutOperandList = outs; - dag InOperandList = ins; + dag InOperandList = ins; + let AsmString = asmstr; let Pattern = pattern; + let Itinerary = itin; } +// Mips Pseudo Instructions Format +class MipsPseudo pattern>: + MipsInst; //===----------------------------------------------------------------------===// // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> //===----------------------------------------------------------------------===// class FR op, bits<6> _funct, dag outs, dag ins, string asmstr, - list pattern>: - MipsInst + list pattern, InstrItinClass itin>: + MipsInst { bits<5> rd; bits<5> rs; @@ -59,7 +64,7 @@ class FR op, bits<6> _funct, dag outs, dag ins, string asmstr, let funct = _funct; let Inst{25-21} = rs; - let Inst{20-16} = rt; + let Inst{20-16} = rt; let Inst{15-11} = rd; let Inst{10-6} = shamt; let Inst{5-0} = funct; @@ -69,8 +74,8 @@ class FR op, bits<6> _funct, dag outs, dag ins, string asmstr, // Format I instruction class in Mips : <|opcode|rs|rt|immediate|> //===----------------------------------------------------------------------===// -class FI op, dag outs, dag ins, string asmstr, list pattern>: - MipsInst +class FI op, dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin>: MipsInst { bits<5> rt; bits<5> rs; @@ -79,7 +84,7 @@ class FI op, dag outs, dag ins, string asmstr, list pattern>: let opcode = op; let Inst{25-21} = rs; - let Inst{20-16} = rt; + let Inst{20-16} = rt; let Inst{15-0} = imm16; } @@ -87,12 +92,136 @@ class FI op, dag outs, dag ins, string asmstr, list pattern>: // Format J instruction class in Mips : <|opcode|address|> //===----------------------------------------------------------------------===// -class FJ op, dag outs, dag ins, string asmstr, list pattern>: - MipsInst +class FJ op, dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin>: MipsInst { bits<26> addr; let opcode = op; - + let Inst{25-0} = addr; } + +//===----------------------------------------------------------------------===// +// +// FLOATING POINT INSTRUCTION FORMATS +// +// opcode - operation code. +// fs - src reg. +// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). +// fd - dst reg, only used on 3 regs instr. +// fmt - double or single precision. +// funct - combined with opcode field give us an operation code. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> +//===----------------------------------------------------------------------===// + +class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, + string asmstr, list pattern> : + MipsInst +{ + bits<5> fd; + bits<5> fs; + bits<5> ft; + bits<5> fmt; + bits<6> funct; + + let opcode = op; + let funct = _funct; + let fmt = _fmt; + + let Inst{25-21} = fmt; + let Inst{20-16} = ft; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = funct; +} + +//===----------------------------------------------------------------------===// +// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> +//===----------------------------------------------------------------------===// + +class FFI op, dag outs, dag ins, string asmstr, list pattern>: + MipsInst +{ + bits<5> ft; + bits<5> base; + bits<16> imm16; + + let opcode = op; + + let Inst{25-21} = base; + let Inst{20-16} = ft; + let Inst{15-0} = imm16; +} + +//===----------------------------------------------------------------------===// +// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> +//===----------------------------------------------------------------------===// + +class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> : + MipsInst +{ + bits<5> fs; + bits<5> ft; + bits<4> cc; + bits<5> fmt; + + let opcode = 0x11; + let fmt = _fmt; + + let Inst{25-21} = fmt; + let Inst{20-16} = ft; + let Inst{15-11} = fs; + let Inst{10-6} = 0; + let Inst{5-4} = 0b11; + let Inst{3-0} = cc; +} + + +class FCMOV _tf, dag outs, dag ins, string asmstr, + list pattern> : + MipsInst +{ + bits<5> rd; + bits<5> rs; + bits<3> N; + bits<1> tf; + + let opcode = 0; + let tf = _tf; + + let Inst{25-21} = rs; + let Inst{20-18} = N; + let Inst{17} = 0; + let Inst{16} = tf; + let Inst{15-11} = rd; + let Inst{10-6} = 0; + let Inst{5-0} = 1; +} + +class FFCMOV _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, + list pattern> : + MipsInst +{ + bits<5> fd; + bits<5> fs; + bits<3> N; + bits<5> fmt; + bits<1> tf; + + let opcode = 17; + let fmt = _fmt; + let tf = _tf; + + let Inst{25-21} = fmt; + let Inst{20-18} = N; + let Inst{17} = 0; + let Inst{16} = tf; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = 17; +} \ No newline at end of file