X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsInstrInfo.td;h=5337c9fb816a2d7b08e507309d496a2318f900f1;hb=00667a54f21f2d58382ac2eed973706332ed5817;hp=0e0af5d45a1ef5732a68003cbde38ba21567e0cd;hpb=7728f7e890fd326af6948c52092fc9ea4f38c986;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 0e0af5d45a1..5337c9fb816 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -19,20 +19,25 @@ include "MipsInstrFormats.td" def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; -def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, - SDTCisSameAs<1, 2>, SDTCisInt<3>]>; +def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, + SDTCisSameAs<2, 3>, SDTCisInt<1>]>; +def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, + SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, + SDTCisInt<4>]>; def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; // Call -def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, - SDNPOutFlag]>; +def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, + [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag, + SDNPVariadic]>; // Hi and Lo nodes are used to handle global addresses. Used on // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol // static model. (nothing to do with Mips Registers Hi and Lo) -def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>; -def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; +def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; +def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; +def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; // Return def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, @@ -47,10 +52,16 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, // Select Condition Code def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>; +// Conditional Move +def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>; + //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">; +def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">; +def HasBitCount : Predicate<"Subtarget.hasBitCount()">; +def HasSwap : Predicate<"Subtarget.hasSwap()">; +def HasCondMov : Predicate<"Subtarget.hasCondMov()">; //===----------------------------------------------------------------------===// // Mips Operand, Complex Patterns and Transformations Definitions. @@ -59,10 +70,14 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">; // Instruction operand types def brtarget : Operand; def calltarget : Operand; -def uimm16 : Operand; def simm16 : Operand; def shamt : Operand; +// Unsigned Operand +def uimm16 : Operand { + let PrintMethod = "printUnsignedImm"; +} + // Address operand def mem : Operand { let PrintMethod = "printMemOperand"; @@ -71,21 +86,21 @@ def mem : Operand { // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXFormgetValue() & 0xFFFF); + return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF); }]>; // Transformation Function - get the higher 16 bits. def HI16 : SDNodeXFormgetValue() >> 16); + return getI32Imm((unsigned)N->getZExtValue() >> 16); }]>; // Node immediate fits as 16-bit sign extended on target immediate. // e.g. addi, andi def immSExt16 : PatLeaf<(imm), [{ if (N->getValueType(0) == MVT::i32) - return (int32_t)N->getValue() == (short)N->getValue(); + return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); else - return (int64_t)N->getValue() == (short)N->getValue(); + return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); }]>; // Node immediate fits as 16-bit zero extended on target immediate. @@ -94,24 +109,19 @@ def immSExt16 : PatLeaf<(imm), [{ // e.g. addiu, sltiu def immZExt16 : PatLeaf<(imm), [{ if (N->getValueType(0) == MVT::i32) - return (uint32_t)N->getValue() == (unsigned short)N->getValue(); + return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); else - return (uint64_t)N->getValue() == (unsigned short)N->getValue(); + return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); }], LO16>; -// Node immediate fits as 32-bit zero extended on target immediate. -//def immZExt32 : PatLeaf<(imm), [{ -// return (uint64_t)N->getValue() == (uint32_t)N->getValue(); -//}], LO16>; - // shamt field must fit in 5 bits. def immZExt5 : PatLeaf<(imm), [{ - return N->getValue() == ((N->getValue()) & 0x1f) ; + return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ; }]>; // Mips Address Mode! SDNode frameindex could possibily be a match // since load and store instructions from stack used it. -def addr : ComplexPattern; +def addr : ComplexPattern; //===----------------------------------------------------------------------===// // Instructions specific format @@ -125,7 +135,7 @@ class ArithR op, bits<6> func, string instr_asm, SDNode OpNode, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>; let isCommutable = 1 in @@ -134,7 +144,7 @@ class ArithOverflowR op, bits<6> func, string instr_asm>: func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>; // Arithmetic 2 register operands @@ -143,9 +153,17 @@ class ArithI op, string instr_asm, SDNode OpNode, FI< op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>; +class ArithOverflowI op, string instr_asm, SDNode OpNode, + Operand Od, PatLeaf imm_type> : + FI< op, + (outs CPURegs:$dst), + (ins CPURegs:$b, Od:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [], IIAlu>; + // Arithmetic Multiply ADD/SUB let rd=0 in class MArithR func, string instr_asm> : @@ -153,7 +171,7 @@ class MArithR func, string instr_asm> : func, (outs CPURegs:$rs), (ins CPURegs:$rt), - !strconcat(instr_asm, " $rs, $rt"), + !strconcat(instr_asm, "\t$rs, $rt"), [], IIImul>; // Logical @@ -162,14 +180,14 @@ class LogicR func, string instr_asm, SDNode OpNode>: func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; class LogicI op, string instr_asm, SDNode OpNode>: FI< op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>; class LogicNOR op, bits<6> func, string instr_asm>: @@ -177,7 +195,7 @@ class LogicNOR op, bits<6> func, string instr_asm>: func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>; // Shifts @@ -187,7 +205,7 @@ class LogicR_shift_imm func, string instr_asm, SDNode OpNode>: func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>; class LogicR_shift_reg func, string instr_asm, SDNode OpNode>: @@ -195,7 +213,7 @@ class LogicR_shift_reg func, string instr_asm, SDNode OpNode>: func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; // Load Upper Imediate @@ -203,23 +221,23 @@ class LoadUpper op, string instr_asm>: FI< op, (outs CPURegs:$dst), (ins uimm16:$imm), - !strconcat(instr_asm, " $dst, $imm"), + !strconcat(instr_asm, "\t$dst, $imm"), [], IIAlu>; // Memory Load/Store -let isSimpleLoad = 1, hasDelaySlot = 1 in +let canFoldAsLoad = 1, hasDelaySlot = 1 in class LoadM op, string instr_asm, PatFrag OpNode>: FI< op, (outs CPURegs:$dst), (ins mem:$addr), - !strconcat(instr_asm, " $dst, $addr"), + !strconcat(instr_asm, "\t$dst, $addr"), [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>; class StoreM op, string instr_asm, PatFrag OpNode>: FI< op, (outs), (ins CPURegs:$dst, mem:$addr), - !strconcat(instr_asm, " $dst, $addr"), + !strconcat(instr_asm, "\t$dst, $addr"), [(OpNode CPURegs:$dst, addr:$addr)], IIStore>; // Conditional Branch @@ -228,7 +246,7 @@ class CBranch op, string instr_asm, PatFrag cond_op>: FI< op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset), - !strconcat(instr_asm, " $a, $b, $offset"), + !strconcat(instr_asm, "\t$a, $b, $offset"), [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)], IIBranch>; @@ -237,7 +255,7 @@ class CBranchZero op, string instr_asm, PatFrag cond_op>: FI< op, (outs), (ins CPURegs:$src, brtarget:$offset), - !strconcat(instr_asm, " $src, $offset"), + !strconcat(instr_asm, "\t$src, $offset"), [(brcond (cond_op CPURegs:$src, 0), bb:$offset)], IIBranch>; } @@ -249,7 +267,7 @@ class SetCC_R op, bits<6> func, string instr_asm, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))], IIAlu>; @@ -258,7 +276,7 @@ class SetCC_I op, string instr_asm, PatFrag cond_op, FI< op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c), - !strconcat(instr_asm, " $dst, $b, $c"), + !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))], IIAlu>; @@ -268,7 +286,7 @@ class JumpFJ op, string instr_asm>: FJ< op, (outs), (ins brtarget:$target), - !strconcat(instr_asm, " $target"), + !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>; let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in @@ -277,19 +295,19 @@ class JumpFR op, bits<6> func, string instr_asm>: func, (outs), (ins CPURegs:$target), - !strconcat(instr_asm, " $target"), + !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>; // Jump and Link (Call) let isCall=1, hasDelaySlot=1, // All calls clobber the non-callee saved registers... - Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, - T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in { + Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, + K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in { class JumpLink op, string instr_asm>: FJ< op, (outs), - (ins calltarget:$target), - !strconcat(instr_asm, " $target"), + (ins calltarget:$target, variable_ops), + !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], IIBranch>; let rd=31 in @@ -297,15 +315,15 @@ let isCall=1, hasDelaySlot=1, FR< op, func, (outs), - (ins CPURegs:$rs), - !strconcat(instr_asm, " $rs"), + (ins CPURegs:$rs, variable_ops), + !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>; class BranchLink: FI< 0x1, (outs), - (ins CPURegs:$rs, brtarget:$target), - !strconcat(instr_asm, " $rs, $target"), + (ins CPURegs:$rs, brtarget:$target, variable_ops), + !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>; } @@ -315,26 +333,25 @@ class MulDiv func, string instr_asm, InstrItinClass itin>: func, (outs), (ins CPURegs:$a, CPURegs:$b), - !strconcat(instr_asm, " $a, $b"), + !strconcat(instr_asm, "\t$a, $b"), [], itin>; // Move from Hi/Lo -class MoveFromTo func, string instr_asm>: +class MoveFromLOHI func, string instr_asm>: FR< 0x00, func, (outs CPURegs:$dst), (ins), - !strconcat(instr_asm, " $dst"), + !strconcat(instr_asm, "\t$dst"), [], IIHiLo>; -// Count Leading Ones/Zeros in Word -class CountLeading func, string instr_asm>: - FR< 0x1c, +class MoveToLOHI func, string instr_asm>: + FR< 0x00, func, - (outs CPURegs:$dst), + (outs), (ins CPURegs:$src), - !strconcat(instr_asm, " $dst, $src"), - [], IIAlu>; + !strconcat(instr_asm, "\t$src"), + [], IIHiLo>; class EffectiveAddress : FI<0x09, @@ -343,11 +360,30 @@ class EffectiveAddress : instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; +// Count Leading Ones/Zeros in Word +class CountLeading func, string instr_asm, SDNode CountOp>: + FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$dst, $src"), + [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>; + +// Sign Extend in Register. class SignExtInReg func, string instr_asm, ValueType vt>: FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, " $dst, $src"), + !strconcat(instr_asm, "\t$dst, $src"), [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>; +// Byte Swap +class ByteSwap func, string instr_asm>: + FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$dst, $src"), + [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>; + +// Conditional Move +class CondMov func, string instr_asm, PatLeaf MovCode>: + FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T, + CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"), + [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T, + CPURegs:$cond, MovCode))], NoItinerary>; //===----------------------------------------------------------------------===// // Pseudo instructions @@ -357,33 +393,38 @@ class SignExtInReg func, string instr_asm, ValueType vt>: let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt), "!ADJCALLSTACKDOWN $amt", - [(callseq_start imm:$amt)]>; + [(callseq_start timm:$amt)]>; def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2), "!ADJCALLSTACKUP $amt1", - [(callseq_end imm:$amt1, imm:$amt2)]>; + [(callseq_end timm:$amt1, timm:$amt2)]>; } +// Some assembly macros need to avoid pseudoinstructions and assembler +// automatic reodering, we should reorder ourselves. +def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>; +def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>; +def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>; +def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>; + // When handling PIC code the assembler needs .cpload and .cprestore // directives. If the real instructions corresponding these directives // are used, we have the same behavior, but get also a bunch of warnings // from the assembler. -def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$reg), - ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", - []>; -def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), - ".cprestore $loc\n", []>; +def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>; +def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>; // The supported Mips ISAs dont have any instruction close to the SELECT_CC // operation. The solution is to create a Mips pseudo SELECT_CC instruction // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally // replace it for real supported nodes into EmitInstrWithCustomInserter -let usesCustomDAGSchedInserter = 1 in { - def Select_CC : MipsPseudo<(outs CPURegs:$dst), - (ins CPURegs:$CmpRes, CPURegs:$T, CPURegs:$F), "# MipsSelect_CC", - [(set CPURegs:$dst, (MipsSelectCC CPURegs:$CmpRes, - CPURegs:$T, CPURegs:$F))]>; +let usesCustomInserter = 1 in { + class PseudoSelCC: + MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr, + [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>; } +def Select_CC : PseudoSelCC; + //===----------------------------------------------------------------------===// // Instruction definition //===----------------------------------------------------------------------===// @@ -392,29 +433,29 @@ let usesCustomDAGSchedInserter = 1 in { // MipsI Instructions //===----------------------------------------------------------------------===// -// Arithmetic +/// Arithmetic Instructions (ALU Immediate) +def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>; +def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>; +def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>; +def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>; +def ANDi : LogicI<0x0c, "andi", and>; +def ORi : LogicI<0x0d, "ori", or>; +def XORi : LogicI<0x0e, "xori", xor>; +def LUi : LoadUpper<0x0f, "lui">; -// ADDiu just accept 16-bit immediates but we handle this on Pat's. -// immZExt32 is used here so it can match GlobalAddress immediates. -// MUL is a assembly macro in the current used ISAs. -def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>; -def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>; -//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; +/// Arithmetic Instructions (3-Operand, R-Type) def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>; def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>; def ADD : ArithOverflowR<0x00, 0x20, "add">; def SUB : ArithOverflowR<0x00, 0x22, "sub">; - -// Logical +def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>; +def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>; def AND : LogicR<0x24, "and", and>; def OR : LogicR<0x25, "or", or>; def XOR : LogicR<0x26, "xor", xor>; -def ANDi : LogicI<0x0c, "andi", and>; -def ORi : LogicI<0x0d, "ori", or>; -def XORi : LogicI<0x0e, "xori", xor>; def NOR : LogicNOR<0x00, 0x27, "nor">; -// Shifts +/// Shift Instructions def SLL : LogicR_shift_imm<0x00, "sll", shl>; def SRL : LogicR_shift_imm<0x02, "srl", srl>; def SRA : LogicR_shift_imm<0x03, "sra", sra>; @@ -422,10 +463,7 @@ def SLLV : LogicR_shift_reg<0x04, "sllv", shl>; def SRLV : LogicR_shift_reg<0x06, "srlv", srl>; def SRAV : LogicR_shift_reg<0x07, "srav", sra>; -// Load Upper Immediate -def LUi : LoadUpper<0x0f, "lui">; - -// Load/Store +/// Load and Store Instructions def LB : LoadM<0x20, "lb", sextloadi8>; def LBu : LoadM<0x24, "lbu", zextloadi8>; def LH : LoadM<0x21, "lh", sextloadi16>; @@ -435,74 +473,88 @@ def SB : StoreM<0x28, "sb", truncstorei8>; def SH : StoreM<0x29, "sh", truncstorei16>; def SW : StoreM<0x2b, "sw", store>; -// Conditional Branch +/// Jump and Branch Instructions +def J : JumpFJ<0x02, "j">; +def JR : JumpFR<0x00, 0x08, "jr">; +def JAL : JumpLink<0x03, "jal">; +def JALR : JumpLinkReg<0x00, 0x09, "jalr">; def BEQ : CBranch<0x04, "beq", seteq>; def BNE : CBranch<0x05, "bne", setne>; let rt=1 in -def BGEZ : CBranchZero<0x01, "bgez", setge>; + def BGEZ : CBranchZero<0x01, "bgez", setge>; let rt=0 in { -def BGTZ : CBranchZero<0x07, "bgtz", setgt>; -def BLEZ : CBranchZero<0x07, "blez", setle>; -def BLTZ : CBranchZero<0x01, "bltz", setlt>; + def BGTZ : CBranchZero<0x07, "bgtz", setgt>; + def BLEZ : CBranchZero<0x07, "blez", setle>; + def BLTZ : CBranchZero<0x01, "bltz", setlt>; } -// Set Condition Code -def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>; -def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>; -def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>; -def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>; - -// Unconditional jump -def J : JumpFJ<0x02, "j">; -def JR : JumpFR<0x00, 0x08, "jr">; - -// Jump and Link (Call) -def JAL : JumpLink<0x03, "jal">; -def JALR : JumpLinkReg<0x00, 0x09, "jalr">; def BGEZAL : BranchLink<"bgezal">; def BLTZAL : BranchLink<"bltzal">; -// MulDiv and Move From Hi/Lo operations, have -// their correpondent SDNodes created on ISelDAG. -// Special Mul, Div operations -def MULT : MulDiv<0x18, "mult", IIImul>; -def MULTu : MulDiv<0x19, "multu", IIImul>; -def DIV : MulDiv<0x1a, "div", IIIdiv>; -def DIVu : MulDiv<0x1b, "divu", IIIdiv>; - -// Move From Hi/Lo -def MFHI : MoveFromTo<0x10, "mfhi">; -def MFLO : MoveFromTo<0x12, "mflo">; -def MTHI : MoveFromTo<0x11, "mthi">; -def MTLO : MoveFromTo<0x13, "mtlo">; - -// No operation -let addr=0 in -def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; - -// Ret instruction - as mips does not have "ret" a -// jr $ra must be generated. let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in -{ def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target), - "jr $target", [(MipsRet CPURegs:$target)], IIBranch>; + "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>; + +/// Multiply and Divide Instructions. +let Defs = [HI, LO] in { + def MULT : MulDiv<0x18, "mult", IIImul>; + def MULTu : MulDiv<0x19, "multu", IIImul>; + def DIV : MulDiv<0x1a, "div", IIIdiv>; + def DIVu : MulDiv<0x1b, "divu", IIIdiv>; +} + +let Defs = [HI] in + def MTHI : MoveToLOHI<0x11, "mthi">; +let Defs = [LO] in + def MTLO : MoveToLOHI<0x13, "mtlo">; + +let Uses = [HI] in + def MFHI : MoveFromLOHI<0x10, "mfhi">; +let Uses = [LO] in + def MFLO : MoveFromLOHI<0x12, "mflo">; + +/// Sign Ext In Register Instructions. +let Predicates = [HasSEInReg] in { + let shamt = 0x10, rs = 0 in + def SEB : SignExtInReg<0x21, "seb", i8>; + + let shamt = 0x18, rs = 0 in + def SEH : SignExtInReg<0x20, "seh", i16>; +} + +/// Count Leading +let Predicates = [HasBitCount] in { + let rt = 0 in + def CLZ : CountLeading<0b010110, "clz", ctlz>; +} + +/// Byte Swap +let Predicates = [HasSwap] in { + let shamt = 0x3, rs = 0 in + def WSBW : ByteSwap<0x20, "wsbw">; +} + +/// Conditional Move +def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>; +def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>; + +let Predicates = [HasCondMov], Constraints = "$F = $dst" in { + def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>; + def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>; } +/// No operation +let addr=0 in + def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; + // FrameIndexes are legalized when they are operands from load/store // instructions. The same not happens for stack address copies, so an // add op with mem ComplexPattern is used and the stack address copy // can be matched. It's similar to Sparc LEA_ADDRi -def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">; - -// Count Leading -// CLO/CLZ are part of the newer MIPS32(tm) instruction -// set and not older Mips I keep this for future use -// though. -//def CLO : CountLeading<0x21, "clo">; -//def CLZ : CountLeading<0x20, "clz">; +def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; // MADD*/MSUB* are not part of MipsI either. //def MADD : MArithR<0x00, "madd">; @@ -510,13 +562,9 @@ def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">; //def MSUB : MArithR<0x04, "msub">; //def MSUBU : MArithR<0x05, "msubu">; -let Predicates = [HasSEInReg] in { - let shamt = 0x10, rs = 0 in - def SEB : SignExtInReg<0x21, "seb", i8>; - - let shamt = 0x18, rs = 0 in - def SEH : SignExtInReg<0x20, "seh", i16>; -} +// MUL is a assembly macro in the current used ISAs. In recent ISA's +// it is a real instruction. +//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions @@ -545,73 +593,92 @@ def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), (JAL tglobaladdr:$dst)>; def : Pat<(MipsJmpLink (i32 texternalsym:$dst)), (JAL texternalsym:$dst)>; -def : Pat<(MipsJmpLink CPURegs:$dst), - (JALR CPURegs:$dst)>; +//def : Pat<(MipsJmpLink CPURegs:$dst), +// (JALR CPURegs:$dst)>; -// GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable +// hi/lo relocs def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; -def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; + def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; -def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), (ADDiu CPURegs:$hi, tjumptable:$lo)>; +def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; +def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), + (ADDiu CPURegs:$hi, tconstpool:$lo)>; + +// gp_rel relocs +def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), + (ADDiu CPURegs:$gp, tglobaladdr:$in)>; +def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), + (ADDiu CPURegs:$gp, tconstpool:$in)>; + // Mips does not have "not", so we expand our way def : Pat<(not CPURegs:$in), (NOR CPURegs:$in, ZERO)>; // extended load and stores -def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; -def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; -def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; +def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>; +def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>; +def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>; // peepholes def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; // brcond patterns -// direct match equal/notequal zero branches def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst), (BNE CPURegs:$lhs, ZERO, bb:$dst)>; def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst), (BEQ CPURegs:$lhs, ZERO, bb:$dst)>; def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; + (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; - -def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; -def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; + (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; +def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst), + (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; +def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst), + (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; + (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>; def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; - -def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst), - (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst), - (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; - -def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; -def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst), - (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; - -// generic brcond pattern + (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>; + def : Pat<(brcond CPURegs:$cond, bb:$dst), (BNE CPURegs:$cond, ZERO, bb:$dst)>; -/// setcc patterns, only matched when there -/// is no brcond following a setcc operation +// select patterns +def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>; +def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>; +def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>; +def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>; + +def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>; +def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>; + +def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>; +def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), + (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>; + +def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F), + (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>; + +// setcc patterns +def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs), + (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>; +def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs), + (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>; + def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs), (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>; def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs), @@ -627,18 +694,10 @@ def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs), def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs), (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>; -def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs), - (OR (SLT CPURegs:$lhs, CPURegs:$rhs), - (SLT CPURegs:$rhs, CPURegs:$lhs))>; - -def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs), - (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs), - (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>; - def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs), (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>; -def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs), - (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>; +def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs), + (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>; //===----------------------------------------------------------------------===// // Floating Point Support