X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsInstrInfo.td;h=f52ca52060ef59ca7d0340d03ee3e659559290c3;hb=c12979aa1c53c240b75c46b894a828c637377a12;hp=b6cfe6d53e0263d520e64688066a322c1d62bdf1;hpb=91625aab6057c46cb167f7ac4a487fe02993acb1;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b6cfe6d53e0..f52ca52060e 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -16,7 +16,6 @@ // Mips profiles and nodes //===----------------------------------------------------------------------===// -def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, @@ -34,8 +33,6 @@ def SDT_MipsDivRem : SDTypeProfile<0, 2, def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; -def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, - SDTCisSameAs<0, 1>]>; def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, @@ -53,6 +50,10 @@ def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; +// Tail call +def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + // Hi and Lo nodes are used to handle global addresses. Used on // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol // static model. (nothing to do with Mips Registers Hi and Lo) @@ -71,14 +72,14 @@ def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; // Return -def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, - SDNPOptInGlue]>; +def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; // These are target-independent nodes, but have target-specific formats. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, - [SDNPHasChain, SDNPOutGlue]>; + [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + [SDNPHasChain, SDNPSideEffect, + SDNPOptInGlue, SDNPOutGlue]>; // MAdd*/MSub* nodes def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, @@ -108,11 +109,7 @@ def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; -// Pointer to dynamically allocated stack area. -def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, - [SDNPHasChain, SDNPInGlue]>; - -def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>; +def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; @@ -145,14 +142,14 @@ def HasSwap : Predicate<"Subtarget.hasSwap()">, AssemblerPredicate<"FeatureSwap">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">, AssemblerPredicate<"FeatureCondMov">; +def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, + AssemblerPredicate<"FeatureFPIdx">; def HasMips32 : Predicate<"Subtarget.hasMips32()">, AssemblerPredicate<"FeatureMips32">; def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, AssemblerPredicate<"FeatureMips32r2">; def HasMips64 : Predicate<"Subtarget.hasMips64()">, AssemblerPredicate<"FeatureMips64">; -def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, - AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; def NotMips64 : Predicate<"!Subtarget.hasMips64()">, AssemblerPredicate<"!FeatureMips64">; def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, @@ -169,8 +166,45 @@ def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, AssemblerPredicate<"FeatureMips32">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, AssemblerPredicate<"FeatureMips32">; -def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, - AssemblerPredicate<"!FeatureMips16">; +def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, + AssemblerPredicate<"!FeatureMips16">; + +class MipsPat : Pat { + let Predicates = [HasStdEnc]; +} + +class IsCommutable { + bit isCommutable = 1; +} + +class IsBranch { + bit isBranch = 1; +} + +class IsReturn { + bit isReturn = 1; +} + +class IsCall { + bit isCall = 1; +} + +class IsTailCall { + bit isCall = 1; + bit isTerminator = 1; + bit isReturn = 1; + bit isBarrier = 1; + bit hasExtraSrcRegAllocReq = 1; + bit isCodeGenOnly = 1; +} + +class IsAsCheapAsAMove { + bit isAsCheapAsAMove = 1; +} + +class NeverHasSideEffects { + bit neverHasSideEffects = 1; +} //===----------------------------------------------------------------------===// // Instruction format superclass @@ -206,16 +240,24 @@ def uimm16 : Operand { let PrintMethod = "printUnsignedImm"; } +def MipsMemAsmOperand : AsmOperandClass { + let Name = "Mem"; + let ParserMethod = "parseMemOperand"; +} + // Address operand def mem : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops CPURegs, simm16); let EncoderMethod = "getMemEncoding"; + let ParserMatchClass = MipsMemAsmOperand; } def mem64 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops CPU64Regs, simm16_64); + let EncoderMethod = "getMemEncoding"; + let ParserMatchClass = MipsMemAsmOperand; } def mem_ea : Operand { @@ -256,6 +298,10 @@ def HI16 : SDNodeXForm(N->getSExtValue()); }]>; +// Node immediate fits as 15-bit sign extended on target immediate. +// e.g. addi, andi +def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; + // Node immediate fits as 16-bit zero extended on target immediate. // The LO16 param means that only the lower 16 bits of the node // immediate are caught. @@ -281,140 +327,69 @@ def immZExt5 : ImmLeaf; def addr : ComplexPattern; -//===----------------------------------------------------------------------===// -// Pattern fragment for load/store -//===----------------------------------------------------------------------===// -class UnalignedLoad : - PatFrag<(ops node:$ptr), (Node node:$ptr), [{ - LoadSDNode *LD = cast(N); - return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment(); -}]>; - -class AlignedLoad : - PatFrag<(ops node:$ptr), (Node node:$ptr), [{ - LoadSDNode *LD = cast(N); - return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment(); -}]>; - -class UnalignedStore : - PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ - StoreSDNode *SD = cast(N); - return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment(); -}]>; - -class AlignedStore : - PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ - StoreSDNode *SD = cast(N); - return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment(); -}]>; - -// Load/Store PatFrags. -def sextloadi16_a : AlignedLoad; -def zextloadi16_a : AlignedLoad; -def extloadi16_a : AlignedLoad; -def load_a : AlignedLoad; -def sextloadi32_a : AlignedLoad; -def zextloadi32_a : AlignedLoad; -def extloadi32_a : AlignedLoad; -def truncstorei16_a : AlignedStore; -def store_a : AlignedStore; -def truncstorei32_a : AlignedStore; -def sextloadi16_u : UnalignedLoad; -def zextloadi16_u : UnalignedLoad; -def extloadi16_u : UnalignedLoad; -def load_u : UnalignedLoad; -def sextloadi32_u : UnalignedLoad; -def zextloadi32_u : UnalignedLoad; -def extloadi32_u : UnalignedLoad; -def truncstorei16_u : UnalignedStore; -def store_u : UnalignedStore; -def truncstorei32_u : UnalignedStore; - //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// // Arithmetic and logical instructions with 3 register operands. -class ArithLogicR op, bits<6> func, string instr_asm, SDNode OpNode, - InstrItinClass itin, RegisterClass RC, bit isComm = 0>: - FR { - let shamt = 0; +class ArithLogicR: + InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { let isCommutable = isComm; let isReMaterializable = 1; -} - -class ArithOverflowR op, bits<6> func, string instr_asm, - InstrItinClass itin, RegisterClass RC, bit isComm = 0>: - FR { - let shamt = 0; - let isCommutable = isComm; + string BaseOpcode; + string Arch; } // Arithmetic and logical instructions with 2 register operands. -class ArithLogicI op, string instr_asm, SDNode OpNode, - Operand Od, PatLeaf imm_type, RegisterClass RC> : - FI { +class ArithLogicI : + InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), + !strconcat(opstr, "\t$rt, $rs, $imm16"), + [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { let isReMaterializable = 1; } -class ArithOverflowI op, string instr_asm, SDNode OpNode, - Operand Od, PatLeaf imm_type, RegisterClass RC> : - FI; - // Arithmetic Multiply ADD/SUB -let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in -class MArithR func, string instr_asm, SDNode op, bit isComm = 0> : - FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), - !strconcat(instr_asm, "\t$rs, $rt"), - [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { - let rd = 0; - let shamt = 0; +class MArithR : + InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt), + !strconcat(opstr, "\t$rs, $rt"), + [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> { + let Defs = [HI, LO]; + let Uses = [HI, LO]; let isCommutable = isComm; } // Logical -class LogicNOR op, bits<6> func, string instr_asm, RegisterClass RC>: - FR { - let shamt = 0; +class LogicNOR: + InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { let isCommutable = 1; } // Shifts -class shift_rotate_imm func, bits<5> isRotate, string instr_asm, - SDNode OpNode, PatFrag PF, Operand ImmOpnd, - RegisterClass RC>: - FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), - !strconcat(instr_asm, "\t$rd, $rt, $shamt"), - [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { - let rs = isRotate; -} - -// 32-bit shift instructions. -class shift_rotate_imm32 func, bits<5> isRotate, string instr_asm, - SDNode OpNode>: - shift_rotate_imm; - -class shift_rotate_reg func, bits<5> isRotate, string instr_asm, - SDNode OpNode, RegisterClass RC>: - FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), - !strconcat(instr_asm, "\t$rd, $rt, $rs"), - [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { - let shamt = isRotate; -} +class shift_rotate_imm : + InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), + !strconcat(opstr, "\t$rd, $rt, $shamt"), + [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; + +class shift_rotate_reg: + InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rt, $rs"), + [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; // Load Upper Imediate -class LoadUpper op, string instr_asm, RegisterClass RC, Operand Imm>: - FI { - let rs = 0; +class LoadUpper: + InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), + [], IIAlu, FrmI>, IsAsCheapAsAMove { let neverHasSideEffects = 1; let isReMaterializable = 1; } @@ -428,66 +403,34 @@ class FMem op, dag outs, dag ins, string asmstr, list pattern, } // Memory Load/Store -let canFoldAsLoad = 1 in -class LoadM op, string instr_asm, PatFrag OpNode, RegisterClass RC, - Operand MemOpnd, bit Pseudo>: - FMem { - let isPseudo = Pseudo; -} - -class StoreM op, string instr_asm, PatFrag OpNode, RegisterClass RC, - Operand MemOpnd, bit Pseudo>: - FMem { - let isPseudo = Pseudo; -} - -// 32-bit load. -multiclass LoadM32 op, string instr_asm, PatFrag OpNode, - bit Pseudo = 0> { - def #NAME# : LoadM, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : LoadM, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } +class Load : + InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; + let canFoldAsLoad = 1; } -// 64-bit load. -multiclass LoadM64 op, string instr_asm, PatFrag OpNode, - bit Pseudo = 0> { - def #NAME# : LoadM, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : LoadM, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } +class Store : + InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; } -// 32-bit store. -multiclass StoreM32 op, string instr_asm, PatFrag OpNode, - bit Pseudo = 0> { - def #NAME# : StoreM, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : StoreM, - Requires<[IsN64, HasStandardEncoding]> { +multiclass LoadM { + def #NAME# : Load, Requires<[NotN64, HasStdEnc]>; + def _P8 : Load, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; } } -// 64-bit store. -multiclass StoreM64 op, string instr_asm, PatFrag OpNode, - bit Pseudo = 0> { - def #NAME# : StoreM, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : StoreM, - Requires<[IsN64, HasStandardEncoding]> { +multiclass StoreM { + def #NAME# : Store, Requires<[NotN64, HasStdEnc]>; + def _P8 : Store, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; } @@ -495,81 +438,58 @@ multiclass StoreM64 op, string instr_asm, PatFrag OpNode, // Load/Store Left/Right let canFoldAsLoad = 1 in -class LoadLeftRight op, string instr_asm, SDNode OpNode, - RegisterClass RC, Operand MemOpnd> : - FMem { +class LoadLeftRight : + InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), + !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; string Constraints = "$src = $rt"; } -class StoreLeftRight op, string instr_asm, SDNode OpNode, - RegisterClass RC, Operand MemOpnd>: - FMem; - -// 32-bit load left/right. -multiclass LoadLeftRightM32 op, string instr_asm, SDNode OpNode> { - def #NAME# : LoadLeftRight, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : LoadLeftRight, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } -} - -// 64-bit load left/right. -multiclass LoadLeftRightM64 op, string instr_asm, SDNode OpNode> { - def #NAME# : LoadLeftRight, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : LoadLeftRight, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } +class StoreLeftRight: + InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; } -// 32-bit store left/right. -multiclass StoreLeftRightM32 op, string instr_asm, SDNode OpNode> { - def #NAME# : StoreLeftRight, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : StoreLeftRight, - Requires<[IsN64, HasStandardEncoding]> { +multiclass LoadLeftRightM { + def #NAME# : LoadLeftRight, + Requires<[NotN64, HasStdEnc]>; + def _P8 : LoadLeftRight, + Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; } } -// 64-bit store left/right. -multiclass StoreLeftRightM64 op, string instr_asm, SDNode OpNode> { - def #NAME# : StoreLeftRight, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : StoreLeftRight, - Requires<[IsN64, HasStandardEncoding]> { +multiclass StoreLeftRightM { + def #NAME# : StoreLeftRight, + Requires<[NotN64, HasStdEnc]>; + def _P8 : StoreLeftRight, + Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; } } // Conditional Branch -class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: - BranchBase { +class CBranch : + InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), + !strconcat(opstr, "\t$rs, $rt, $offset"), + [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, + FrmI> { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; let Defs = [AT]; } -class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, - RegisterClass RC>: - BranchBase { - let rt = _rt; +class CBranchZero : + InstSE<(outs), (ins RC:$rs, brtarget:$offset), + !strconcat(opstr, "\t$rs, $offset"), + [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; @@ -577,548 +497,544 @@ class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, } // SetCC -class SetCC_R op, bits<6> func, string instr_asm, PatFrag cond_op, - RegisterClass RC>: - FR { - let shamt = 0; -} +class SetCC_R : + InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; -class SetCC_I op, string instr_asm, PatFrag cond_op, Operand Od, - PatLeaf imm_type, RegisterClass RC>: - FI; +class SetCC_I: + InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), + !strconcat(opstr, "\t$rt, $rs, $imm16"), + [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; // Jump -class JumpFJ op, string instr_asm>: - FJ { - let isBranch=1; +class JumpFJ : + InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), + [(operator targetoperator:$target)], IIBranch, FrmJ> { let isTerminator=1; let isBarrier=1; let hasDelaySlot = 1; - let Predicates = [RelocStatic, HasStandardEncoding]; let DecoderMethod = "DecodeJumpTarget"; let Defs = [AT]; } // Unconditional branch -class UncondBranch op, string instr_asm>: - BranchBase { - let rs = 0; - let rt = 0; +class UncondBranch : + InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), + [(br bb:$offset)], IIBranch, FrmI> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; let hasDelaySlot = 1; - let Predicates = [RelocPIC, HasStandardEncoding]; + let Predicates = [RelocPIC, HasStdEnc]; let Defs = [AT]; } -let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1, - isIndirectBranch = 1 in -class JumpFR op, bits<6> func, string instr_asm, RegisterClass RC>: - FR { - let rt = 0; - let rd = 0; - let shamt = 0; +// Base class for indirect branch and return instruction classes. +let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in +class JumpFR: + InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; + +// Indirect branch +class IndirectBranch: JumpFR { + let isBranch = 1; + let isIndirectBranch = 1; +} + +// Return instruction +class RetBase: JumpFR { + let isReturn = 1; + let isCodeGenOnly = 1; + let hasCtrlDep = 1; + let hasExtraSrcRegAllocReq = 1; } // Jump and Link (Call) -let isCall=1, hasDelaySlot=1 in { - class JumpLink op, string instr_asm>: - FJ { - let DecoderMethod = "DecodeJumpTarget"; - } - - class JumpLinkReg op, bits<6> func, string instr_asm, - RegisterClass RC>: - FR { - let rt = 0; - let rd = 31; - let shamt = 0; +let isCall=1, hasDelaySlot=1, Defs = [RA] in { + class JumpLink : + InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), + [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { + let DecoderMethod = "DecodeJumpTarget"; } - class BranchLink _rt, RegisterClass RC>: - FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops), - !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { - let rt = _rt; - } + class JumpLinkReg: + InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), + [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; + + class BGEZAL_FT : + InstSE<(outs), (ins RC:$rs, brtarget:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; + +} + +class BAL_FT : + InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { + let isBranch = 1; + let isTerminator = 1; + let isBarrier = 1; + let hasDelaySlot = 1; + let Defs = [RA]; } +// Sync +let hasSideEffects = 1 in +class SYNC_FT : + InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], + NoItinerary, FrmOther>; + // Mul, Div -class Mult func, string instr_asm, InstrItinClass itin, - RegisterClass RC, list DefRegs>: - FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), - !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { - let rd = 0; - let shamt = 0; +class Mult DefRegs> : + InstSE<(outs), (ins RC:$rs, RC:$rt), !strconcat(opstr, "\t$rs, $rt"), [], + itin, FrmR> { let isCommutable = 1; let Defs = DefRegs; let neverHasSideEffects = 1; } -class Mult32 func, string instr_asm, InstrItinClass itin>: - Mult; - -class Div func, string instr_asm, InstrItinClass itin, - RegisterClass RC, list DefRegs>: - FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), - !strconcat(instr_asm, "\t$$zero, $rs, $rt"), - [(op RC:$rs, RC:$rt)], itin> { - let rd = 0; - let shamt = 0; +class Div DefRegs> : + InstSE<(outs), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin, + FrmR> { let Defs = DefRegs; } -class Div32 func, string instr_asm, InstrItinClass itin>: - Div; - // Move from Hi/Lo -class MoveFromLOHI func, string instr_asm, RegisterClass RC, - list UseRegs>: - FR<0x00, func, (outs RC:$rd), (ins), - !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { - let rs = 0; - let rt = 0; - let shamt = 0; +class MoveFromLOHI UseRegs>: + InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { let Uses = UseRegs; let neverHasSideEffects = 1; } -class MoveToLOHI func, string instr_asm, RegisterClass RC, - list DefRegs>: - FR<0x00, func, (outs), (ins RC:$rs), - !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { - let rt = 0; - let rd = 0; - let shamt = 0; +class MoveToLOHI DefRegs>: + InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { let Defs = DefRegs; let neverHasSideEffects = 1; } -class EffectiveAddress : - FMem<0x09, (outs RC:$rt), (ins Mem:$addr), - instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>; +class EffectiveAddress : + InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { + let isCodeGenOnly = 1; + let DecoderMethod = "DecodeMem"; +} // Count Leading Ones/Zeros in Word -class CountLeading0 func, string instr_asm, RegisterClass RC>: - FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), - !strconcat(instr_asm, "\t$rd, $rs"), - [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, - Requires<[HasBitCount, HasStandardEncoding]> { - let shamt = 0; - let rt = rd; -} +class CountLeading0: + InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), + [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, + Requires<[HasBitCount, HasStdEnc]>; + +class CountLeading1: + InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), + [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, + Requires<[HasBitCount, HasStdEnc]>; -class CountLeading1 func, string instr_asm, RegisterClass RC>: - FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), - !strconcat(instr_asm, "\t$rd, $rs"), - [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, - Requires<[HasBitCount, HasStandardEncoding]> { - let shamt = 0; - let rt = rd; -} // Sign Extend in Register. -class SignExtInReg sa, string instr_asm, ValueType vt, - RegisterClass RC>: - FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), - !strconcat(instr_asm, "\t$rd, $rt"), - [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { - let rs = 0; - let shamt = sa; - let Predicates = [HasSEInReg, HasStandardEncoding]; +class SignExtInReg : + InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), + [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { + let Predicates = [HasSEInReg, HasStdEnc]; } // Subword Swap -class SubwordSwap func, bits<5> sa, string instr_asm, RegisterClass RC>: - FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), - !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { - let rs = 0; - let shamt = sa; - let Predicates = [HasSwap, HasStandardEncoding]; +class SubwordSwap: + InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), [], + NoItinerary, FrmR> { + let Predicates = [HasSwap, HasStdEnc]; let neverHasSideEffects = 1; } // Read Hardware -class ReadHardware - : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), - "rdhwr\t$rt, $rd", [], IIAlu> { - let rs = 0; - let shamt = 0; -} +class ReadHardware : + InstSE<(outs CPURegClass:$rt), (ins HWRegClass:$rd), "rdhwr\t$rt, $rd", [], + IIAlu, FrmR>; // Ext and Ins -class ExtBase _funct, string instr_asm, RegisterClass RC>: - FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), - !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), - [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { - bits<5> pos; - bits<5> sz; - let rd = sz; - let shamt = pos; - let Predicates = [HasMips32r2, HasStandardEncoding]; -} - -class InsBase _funct, string instr_asm, RegisterClass RC>: - FR<0x1f, _funct, (outs RC:$rt), - (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), - !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), - [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], - NoItinerary> { - bits<5> pos; - bits<5> sz; - let rd = sz; - let shamt = pos; - let Predicates = [HasMips32r2, HasStandardEncoding]; +class ExtBase: + InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$size), + !strconcat(opstr, " $rt, $rs, $pos, $size"), + [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$size))], NoItinerary, + FrmR> { + let Predicates = [HasMips32r2, HasStdEnc]; +} + +class InsBase: + InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ins:$size, RC:$src), + !strconcat(opstr, " $rt, $rs, $pos, $size"), + [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$size, RC:$src))], + NoItinerary, FrmR> { + let Predicates = [HasMips32r2, HasStdEnc]; let Constraints = "$src = $rt"; } // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). -class Atomic2Ops : - MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), - !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), - [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; - -multiclass Atomic2Ops32 { - def #NAME# : Atomic2Ops, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : Atomic2Ops, - Requires<[IsN64, HasStandardEncoding]> { +class Atomic2Ops : + PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), + [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; + +multiclass Atomic2Ops32 { + def #NAME# : Atomic2Ops, Requires<[NotN64, HasStdEnc]>; + def _P8 : Atomic2Ops, + Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } } // Atomic Compare & Swap. -class AtomicCmpSwap : - MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), - !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), - [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; - -multiclass AtomicCmpSwap32 { - def #NAME# : AtomicCmpSwap, - Requires<[NotN64, HasStandardEncoding]>; - def _P8 : AtomicCmpSwap, - Requires<[IsN64, HasStandardEncoding]> { +class AtomicCmpSwap : + PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), + [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; + +multiclass AtomicCmpSwap32 { + def #NAME# : AtomicCmpSwap, + Requires<[NotN64, HasStdEnc]>; + def _P8 : AtomicCmpSwap, + Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } } -class LLBase Opc, string opstring, RegisterClass RC, Operand Mem> : - FMem { +class LLBase : + InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; let mayLoad = 1; } -class SCBase Opc, string opstring, RegisterClass RC, Operand Mem> : - FMem { +class SCBase : + InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; let mayStore = 1; let Constraints = "$rt = $dst"; } +class MFC3OP : + InstSE; + //===----------------------------------------------------------------------===// // Pseudo instructions //===----------------------------------------------------------------------===// -// As stack alignment is always done with addiu, we need a 16-bit immediate -let Defs = [SP], Uses = [SP] in { -def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt), - "!ADJCALLSTACKDOWN $amt", +// Return RA. +let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in +def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; + +let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { +def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), [(callseq_start timm:$amt)]>; -def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2), - "!ADJCALLSTACKUP $amt1", +def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(callseq_end timm:$amt1, timm:$amt2)]>; } -// When handling PIC code the assembler needs .cpload and .cprestore -// directives. If the real instructions corresponding these directives -// are used, we have the same behavior, but get also a bunch of warnings -// from the assembler. -let neverHasSideEffects = 1 in -def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp), - ".cprestore\t$loc", []>; - let usesCustomInserter = 1 in { - defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32; - defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32; - defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32; - defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32; - defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32; - defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32; - defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32; - defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32; - - defm ATOMIC_SWAP_I8 : Atomic2Ops32; - defm ATOMIC_SWAP_I16 : Atomic2Ops32; - defm ATOMIC_SWAP_I32 : Atomic2Ops32; - - defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32; - defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32; - defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32; + defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32; + defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32; + defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32; + defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32; + defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32; + defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32; + defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32; + defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32; + + defm ATOMIC_SWAP_I8 : Atomic2Ops32; + defm ATOMIC_SWAP_I16 : Atomic2Ops32; + defm ATOMIC_SWAP_I32 : Atomic2Ops32; + + defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32; + defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32; + defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32; } //===----------------------------------------------------------------------===// // Instruction definition //===----------------------------------------------------------------------===// - //===----------------------------------------------------------------------===// // MipsI Instructions //===----------------------------------------------------------------------===// /// Arithmetic Instructions (ALU Immediate) -def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; -def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; -def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; -def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; -def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; -def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; -def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; -def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; +def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, + ADDI_FM<0x9>, IsAsCheapAsAMove; +def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; +def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; +def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; +def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; +def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; +def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; +def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; /// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; -def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; -def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; -def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; -def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; -def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; -def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; -def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; -def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; -def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; +def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; +def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; +def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; +def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; +def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; +def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; +def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; +def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; +def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; +def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; +def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; /// Shift Instructions -def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; -def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; -def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; -def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; -def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; -def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; +def SLL : shift_rotate_imm<"sll", shamt, CPURegs, shl, immZExt5>, SRA_FM<0, 0>; +def SRL : shift_rotate_imm<"srl", shamt, CPURegs, srl, immZExt5>, SRA_FM<2, 0>; +def SRA : shift_rotate_imm<"sra", shamt, CPURegs, sra, immZExt5>, SRA_FM<3, 0>; +def SLLV : shift_rotate_reg<"sllv", CPURegs, shl>, SRLV_FM<4, 0>; +def SRLV : shift_rotate_reg<"srlv", CPURegs, srl>, SRLV_FM<6, 0>; +def SRAV : shift_rotate_reg<"srav", CPURegs, sra>, SRLV_FM<7, 0>; // Rotate Instructions -let Predicates = [HasMips32r2, HasStandardEncoding] in { - def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; - def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; +let Predicates = [HasMips32r2, HasStdEnc] in { + def ROTR : shift_rotate_imm<"rotr", shamt, CPURegs, rotr, immZExt5>, + SRA_FM<2, 1>; + def ROTRV : shift_rotate_reg<"rotrv", CPURegs, rotr>, SRLV_FM<6, 1>; } /// Load and Store Instructions /// aligned -defm LB : LoadM32<0x20, "lb", sextloadi8>; -defm LBu : LoadM32<0x24, "lbu", zextloadi8>; -defm LH : LoadM32<0x21, "lh", sextloadi16_a>; -defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>; -defm LW : LoadM32<0x23, "lw", load_a>; -defm SB : StoreM32<0x28, "sb", truncstorei8>; -defm SH : StoreM32<0x29, "sh", truncstorei16_a>; -defm SW : StoreM32<0x2b, "sw", store_a>; - -/// unaligned -defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>; -defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>; -defm ULW : LoadM32<0x23, "ulw", load_u, 1>; -defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>; -defm USW : StoreM32<0x2b, "usw", store_u, 1>; +defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; +defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; +defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; +defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; +defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; +defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; +defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; +defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; /// load/store left/right -defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; -defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; -defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; -defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; +defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; +defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; +defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; +defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; -let hasSideEffects = 1 in -def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", - [(MipsSync imm:$stype)], NoItinerary, FrmOther> -{ - bits<5> stype; - let Opcode = 0; - let Inst{25-11} = 0; - let Inst{10-6} = stype; - let Inst{5-0} = 15; -} +def SYNC : SYNC_FT, SYNC_FM; /// Load-linked, Store-conditional -def LL : LLBase<0x30, "ll", CPURegs, mem>, - Requires<[NotN64, HasStandardEncoding]>; -def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; +let Predicates = [NotN64, HasStdEnc] in { + def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>; + def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>; } -def SC : SCBase<0x38, "sc", CPURegs, mem>, - Requires<[NotN64, HasStandardEncoding]>; -def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, - Requires<[IsN64, HasStandardEncoding]> { - let DecoderNamespace = "Mips64"; +let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { + def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>; + def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>; } /// Jump and Branch Instructions -def J : JumpFJ<0x02, "j">; -def JR : JumpFR<0x00, 0x08, "jr", CPURegs>; -def B : UncondBranch<0x04, "b">; -def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; -def BNE : CBranch<0x05, "bne", setne, CPURegs>; -def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; -def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; -def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; -def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; - -def JAL : JumpLink<0x03, "jal">; -def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; -def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; -def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; - -let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1, - isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in - def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target), - "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>; +def J : JumpFJ, FJ<2>, + Requires<[RelocStatic, HasStdEnc]>, IsBranch; +def JR : IndirectBranch, MTLO_FM<8>; +def B : UncondBranch<"b">, B_FM; +def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; +def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; +def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; +def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; +def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; +def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; + +def BAL_BR: BAL_FT, BAL_FM; + +def JAL : JumpLink<"jal">, FJ<3>; +def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; +def BGEZAL : BGEZAL_FT<"bgezal", CPURegs>, BGEZAL_FM<0x11>; +def BLTZAL : BGEZAL_FT<"bltzal", CPURegs>, BGEZAL_FM<0x10>; +def TAILCALL : JumpFJ, FJ<2>, IsTailCall; +def TAILCALL_R : JumpFR, MTLO_FM<8>, IsTailCall; + +def RET : RetBase, MTLO_FM<8>; /// Multiply and Divide Instructions. -def MULT : Mult32<0x18, "mult", IIImul>; -def MULTu : Mult32<0x19, "multu", IIImul>; -def SDIV : Div32; -def UDIV : Div32; +def MULT : Mult<"mult", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x18>; +def MULTu : Mult<"multu", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x19>; +def SDIV : Div, MULT_FM<0, 0x1a>; +def UDIV : Div, + MULT_FM<0, 0x1b>; -def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; -def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; -def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; -def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; +def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; +def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; +def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; +def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; /// Sign Ext In Register Instructions. -def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; -def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; +def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; +def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; /// Count Leading -def CLZ : CountLeading0<0x20, "clz", CPURegs>; -def CLO : CountLeading1<0x21, "clo", CPURegs>; +def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; +def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; /// Word Swap Bytes Within Halfwords -def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; +def WSBH : SubwordSwap<"wsbh", CPURegs>, SEB_FM<2, 0x20>; -/// No operation -let addr=0 in - def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; +/// No operation. +/// FIXME: NOP should be an alias of "sll $0, $0, 0". +def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM; // FrameIndexes are legalized when they are operands from load/store // instructions. The same not happens for stack address copies, so an // add op with mem ComplexPattern is used and the stack address copy // can be matched. It's similar to Sparc LEA_ADDRi -def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> { - let isCodeGenOnly = 1; -} - -// DynAlloc node points to dynamically allocated stack space. -// $sp is added to the list of implicitly used registers to prevent dead code -// elimination from removing instructions that modify $sp. -let Uses = [SP] in -def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> { - let isCodeGenOnly = 1; -} +def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; // MADD*/MSUB* -def MADD : MArithR<0, "madd", MipsMAdd, 1>; -def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; -def MSUB : MArithR<4, "msub", MipsMSub>; -def MSUBU : MArithR<5, "msubu", MipsMSubu>; +def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; +def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; +def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; +def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; + +def RDHWR : ReadHardware, RDHWR_FM; + +def EXT : ExtBase<"ext", CPURegs>, EXT_FM<0>; +def INS : InsBase<"ins", CPURegs>, EXT_FM<4>; + +/// Move Control Registers From/To CPU Registers +def MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), + "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; -// MUL is a assembly macro in the current used ISAs. In recent ISA's -// it is a real instruction. -def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, - Requires<[HasMips32, HasStandardEncoding]>; +def MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), + "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; + +def MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), + "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; + +def MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), + "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; + +//===----------------------------------------------------------------------===// +// Instruction aliases +//===----------------------------------------------------------------------===// +def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; +def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; +def : InstAlias<"addu $rs,$rt,$imm", + (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; +def : InstAlias<"add $rs,$rt,$imm", + (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; +def : InstAlias<"and $rs,$rt,$imm", + (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; +def : InstAlias<"j $rs", (JR CPURegs:$rs)>; +def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; +def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; +def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; +def : InstAlias<"slt $rs,$rt,$imm", + (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; +def : InstAlias<"xor $rs,$rt,$imm", + (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; +def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; +def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; +def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; +def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; + +//===----------------------------------------------------------------------===// +// Assembler Pseudo Instructions +//===----------------------------------------------------------------------===// + +class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : + MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), + !strconcat(instr_asm, "\t$rt, $imm32")> ; +def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; + +class LoadAddress : + MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), + !strconcat(instr_asm, "\t$rt, $addr")> ; +def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; + +class LoadAddressImm : + MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), + !strconcat(instr_asm, "\t$rt, $imm32")> ; +def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; -def RDHWR : ReadHardware; -def EXT : ExtBase<0, "ext", CPURegs>; -def INS : InsBase<4, "ins", CPURegs>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// // Small immediates -def : Pat<(i32 immSExt16:$in), - (ADDiu ZERO, imm:$in)>; -def : Pat<(i32 immZExt16:$in), - (ORi ZERO, imm:$in)>; -def : Pat<(i32 immLow16Zero:$in), - (LUi (HI16 imm:$in))>; +def : MipsPat<(i32 immSExt16:$in), + (ADDiu ZERO, imm:$in)>; +def : MipsPat<(i32 immZExt16:$in), + (ORi ZERO, imm:$in)>; +def : MipsPat<(i32 immLow16Zero:$in), + (LUi (HI16 imm:$in))>; // Arbitrary immediates -def : Pat<(i32 imm:$imm), +def : MipsPat<(i32 imm:$imm), (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; -// Carry patterns -def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs), - (SUBu CPURegs:$lhs, CPURegs:$rhs)>; -def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs), - (ADDu CPURegs:$lhs, CPURegs:$rhs)>; -def : Pat<(addc CPURegs:$src, immSExt16:$imm), - (ADDiu CPURegs:$src, imm:$imm)>; +// Carry MipsPatterns +def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), + (SUBu CPURegs:$lhs, CPURegs:$rhs)>; +def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), + (ADDu CPURegs:$lhs, CPURegs:$rhs)>; +def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), + (ADDiu CPURegs:$src, imm:$imm)>; // Call -def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), - (JAL tglobaladdr:$dst)>; -def : Pat<(MipsJmpLink (i32 texternalsym:$dst)), - (JAL texternalsym:$dst)>; -//def : Pat<(MipsJmpLink CPURegs:$dst), -// (JALR CPURegs:$dst)>; - +def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), + (JAL tglobaladdr:$dst)>; +def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), + (JAL texternalsym:$dst)>; +//def : MipsPat<(MipsJmpLink CPURegs:$dst), +// (JALR CPURegs:$dst)>; + +// Tail call +def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), + (TAILCALL tglobaladdr:$dst)>; +def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), + (TAILCALL texternalsym:$dst)>; // hi/lo relocs -def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; -def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; -def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; -def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; -def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; - -def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; -def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; -def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; -def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; -def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; - -def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), - (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; -def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), - (ADDiu CPURegs:$hi, tblockaddress:$lo)>; -def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), - (ADDiu CPURegs:$hi, tjumptable:$lo)>; -def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), - (ADDiu CPURegs:$hi, tconstpool:$lo)>; -def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), - (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; +def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; +def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; +def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; +def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; +def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; +def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; + +def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; +def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; +def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; +def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; +def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; +def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; + +def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), + (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; +def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), + (ADDiu CPURegs:$hi, tblockaddress:$lo)>; +def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), + (ADDiu CPURegs:$hi, tjumptable:$lo)>; +def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), + (ADDiu CPURegs:$hi, tconstpool:$lo)>; +def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), + (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; // gp_rel relocs -def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), - (ADDiu CPURegs:$gp, tglobaladdr:$in)>; -def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), - (ADDiu CPURegs:$gp, tconstpool:$in)>; +def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), + (ADDiu CPURegs:$gp, tglobaladdr:$in)>; +def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), + (ADDiu CPURegs:$gp, tconstpool:$in)>; // wrapper_pic class WrapperPat: - Pat<(MipsWrapper RC:$gp, node:$in), - (ADDiuOp RC:$gp, node:$in)>; + MipsPat<(MipsWrapper RC:$gp, node:$in), + (ADDiuOp RC:$gp, node:$in)>; def : WrapperPat; def : WrapperPat; @@ -1128,58 +1044,54 @@ def : WrapperPat; def : WrapperPat; // Mips does not have "not", so we expand our way -def : Pat<(not CPURegs:$in), - (NOR CPURegs:$in, ZERO)>; +def : MipsPat<(not CPURegs:$in), + (NOR CPURegs:$in, ZERO)>; // extended loads -let Predicates = [NotN64, HasStandardEncoding] in { - def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; - def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; - def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>; - def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>; +let Predicates = [NotN64, HasStdEnc] in { + def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; + def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; + def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; } -let Predicates = [IsN64, HasStandardEncoding] in { - def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; - def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; - def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>; - def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>; +let Predicates = [IsN64, HasStdEnc] in { + def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; + def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; + def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; } // peepholes -let Predicates = [NotN64, HasStandardEncoding] in { - def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; - def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; +let Predicates = [NotN64, HasStdEnc] in { + def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; } -let Predicates = [IsN64, HasStandardEncoding] in { - def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; - def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; +let Predicates = [IsN64, HasStdEnc] in { + def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; } // brcond patterns multiclass BrcondPats { -def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), - (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; -def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), - (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; +def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), + (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; +def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), + (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; -def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), + (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; -def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; -def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; +def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), + (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; -def : Pat<(brcond RC:$cond, bb:$dst), - (BNEOp RC:$cond, ZEROReg, bb:$dst)>; +def : MipsPat<(brcond RC:$cond, bb:$dst), + (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } defm : BrcondPats; @@ -1187,39 +1099,39 @@ defm : BrcondPats; // setcc patterns multiclass SeteqPats { - def : Pat<(seteq RC:$lhs, RC:$rhs), - (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; - def : Pat<(setne RC:$lhs, RC:$rhs), - (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; + def : MipsPat<(seteq RC:$lhs, RC:$rhs), + (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; + def : MipsPat<(setne RC:$lhs, RC:$rhs), + (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; } multiclass SetlePats { - def : Pat<(setle RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; - def : Pat<(setule RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; + def : MipsPat<(setle RC:$lhs, RC:$rhs), + (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; + def : MipsPat<(setule RC:$lhs, RC:$rhs), + (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; } multiclass SetgtPats { - def : Pat<(setgt RC:$lhs, RC:$rhs), - (SLTOp RC:$rhs, RC:$lhs)>; - def : Pat<(setugt RC:$lhs, RC:$rhs), - (SLTuOp RC:$rhs, RC:$lhs)>; + def : MipsPat<(setgt RC:$lhs, RC:$rhs), + (SLTOp RC:$rhs, RC:$lhs)>; + def : MipsPat<(setugt RC:$lhs, RC:$rhs), + (SLTuOp RC:$rhs, RC:$lhs)>; } multiclass SetgePats { - def : Pat<(setge RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; - def : Pat<(setuge RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; + def : MipsPat<(setge RC:$lhs, RC:$rhs), + (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; + def : MipsPat<(setuge RC:$lhs, RC:$rhs), + (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; } multiclass SetgeImmPats { - def : Pat<(setge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; - def : Pat<(setuge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; + def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), + (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; + def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), + (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } defm : SeteqPats; @@ -1228,11 +1140,8 @@ defm : SetgtPats; defm : SetgePats; defm : SetgeImmPats; -// select MipsDynAlloc -def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; - // bswap pattern -def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; +def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; //===----------------------------------------------------------------------===// // Floating Point Support @@ -1247,3 +1156,8 @@ include "MipsCondMov.td" include "Mips16InstrFormats.td" include "Mips16InstrInfo.td" + +// DSP +include "MipsDSPInstrFormats.td" +include "MipsDSPInstrInfo.td" +