X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsMSAInstrFormats.td;h=579e6e3ad1789e05f67ef576570de83ba89fe74d;hb=45ecbfc8e58923131068dced0cf89348ac61208f;hp=35082c2912f30ee204f94c3af5d8901ad9ef1ada;hpb=c149fbbe279ef623e6067304fd08dc1a62d74f7d;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 35082c2912f..579e6e3ad17 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -45,27 +45,67 @@ class MSA_BIT_D_FMT major, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_2R_FILL_FMT major, bits<2> df, bits<6> minor>: MSAInst { + bits<5> rs; + bits<5> wd; + + let Inst{25-18} = major; + let Inst{17-16} = df; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_2R_FMT major, bits<2> df, bits<6> minor>: MSAInst { + bits<5> ws; + bits<5> wd; + let Inst{25-18} = major; let Inst{17-16} = df; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } class MSA_2RF_FMT major, bits<1> df, bits<6> minor>: MSAInst { + bits<5> ws; + bits<5> wd; + let Inst{25-17} = major; let Inst{16} = df; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } class MSA_3R_FMT major, bits<2> df, bits<6> minor>: MSAInst { + bits<5> wt; + bits<5> ws; + bits<5> wd; + let Inst{25-23} = major; let Inst{22-21} = df; + let Inst{20-16} = wt; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } class MSA_3RF_FMT major, bits<1> df, bits<6> minor>: MSAInst { + bits<5> wt; + bits<5> ws; + bits<5> wd; + let Inst{25-22} = major; let Inst{21} = df; + let Inst{20-16} = wt; + let Inst{15-11} = ws; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + +class MSA_ELM_FMT major, bits<6> minor>: MSAInst { + let Inst{25-16} = major; let Inst{5-0} = minor; } @@ -93,14 +133,67 @@ class MSA_ELM_D_FMT major, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_ELM_INSERT_B_FMT major, bits<6> minor>: MSAInst { + bits<6> n; + bits<5> rs; + bits<5> wd; + + let Inst{25-22} = major; + let Inst{21-20} = 0b00; + let Inst{19-16} = n{3-0}; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + +class MSA_ELM_INSERT_H_FMT major, bits<6> minor>: MSAInst { + bits<6> n; + bits<5> rs; + bits<5> wd; + + let Inst{25-22} = major; + let Inst{21-19} = 0b100; + let Inst{18-16} = n{2-0}; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + +class MSA_ELM_INSERT_W_FMT major, bits<6> minor>: MSAInst { + bits<6> n; + bits<5> rs; + bits<5> wd; + + let Inst{25-22} = major; + let Inst{21-18} = 0b1100; + let Inst{17-16} = n{1-0}; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_I5_FMT major, bits<2> df, bits<6> minor>: MSAInst { + bits<5> imm; + bits<5> ws; + bits<5> wd; + let Inst{25-23} = major; let Inst{22-21} = df; + let Inst{20-16} = imm; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } class MSA_I8_FMT major, bits<6> minor>: MSAInst { + bits<8> u8; + bits<5> ws; + bits<5> wd; + let Inst{25-24} = major; + let Inst{23-16} = u8; + let Inst{15-11} = ws; + let Inst{10-6} = wd; let Inst{5-0} = minor; } @@ -114,3 +207,8 @@ class MSA_VEC_FMT major, bits<6> minor>: MSAInst { let Inst{25-21} = major; let Inst{5-0} = minor; } + +class MSA_VECS10_FMT major, bits<6> minor>: MSAInst { + let Inst{25-21} = major; + let Inst{5-0} = minor; +}