X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsRegisterInfo.td;h=74dfa4fe7d9cd5cd51e08c0c6ceb46a4de3cd887;hb=cb43f81fc54572b1dddec2370b2583e3f69a1bfc;hp=62a594f4c566ee0b6f48e5a320143d9e9c92ce36;hpb=7d6355226c60cd5ac7e1c916b17fee1a2b30a871;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 62a594f4c56..74dfa4fe7d9 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -11,8 +11,6 @@ // Declarations that describe the MIPS register file //===----------------------------------------------------------------------===// let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex<32>; -def sub_fpodd : SubRegIndex<32, 32>; def sub_32 : SubRegIndex<32>; def sub_64 : SubRegIndex<64>; def sub_lo : SubRegIndex<32>; @@ -55,13 +53,14 @@ class FPR Enc, string n> : MipsReg; // Mips 64-bit (aliased) FPU Registers class AFPR Enc, string n, list subregs> : MipsRegWithSubRegs { - let SubRegIndices = [sub_fpeven, sub_fpodd]; + let SubRegIndices = [sub_lo, sub_hi]; let CoveredBySubRegs = 1; } class AFPR64 Enc, string n, list subregs> : MipsRegWithSubRegs { - let SubRegIndices = [sub_32]; + let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; } // Mips 128-bit (aliased) MSA Registers @@ -157,6 +156,10 @@ let Namespace = "Mips" in { foreach I = 0-31 in def F#I : FPR, DwarfRegNum<[!add(I, 32)]>; + // Higher half of 64-bit FP registers. + foreach I = 0-31 in + def F_HI#I : FPR, DwarfRegNum<[!add(I, 32)]>; + /// Mips Double point precision FPU Registers (aliased /// with the single precision to hold 64 bit values) foreach I = 0-15 in @@ -166,53 +169,24 @@ let Namespace = "Mips" in { /// Mips Double point precision FPU Registers in MFP64 mode. foreach I = 0-31 in - def D#I#_64 : AFPR64("F"#I)]>, + def D#I#_64 : AFPR64("F"#I), !cast("F_HI"#I)]>, DwarfRegNum<[!add(I, 32)]>; /// Mips MSA registers /// MSA and FPU cannot both be present unless the FPU has 64-bit registers - def W0 : AFPR128<0, "w0", [D0_64]>, DwarfRegNum<[32]>; - def W1 : AFPR128<1, "w1", [D1_64]>, DwarfRegNum<[33]>; - def W2 : AFPR128<2, "w2", [D2_64]>, DwarfRegNum<[34]>; - def W3 : AFPR128<3, "w3", [D3_64]>, DwarfRegNum<[35]>; - def W4 : AFPR128<4, "w4", [D4_64]>, DwarfRegNum<[36]>; - def W5 : AFPR128<5, "w5", [D5_64]>, DwarfRegNum<[37]>; - def W6 : AFPR128<6, "w6", [D6_64]>, DwarfRegNum<[38]>; - def W7 : AFPR128<7, "w7", [D7_64]>, DwarfRegNum<[39]>; - def W8 : AFPR128<8, "w8", [D8_64]>, DwarfRegNum<[40]>; - def W9 : AFPR128<9, "w9", [D9_64]>, DwarfRegNum<[41]>; - def W10 : AFPR128<10, "w10", [D10_64]>, DwarfRegNum<[42]>; - def W11 : AFPR128<11, "w11", [D11_64]>, DwarfRegNum<[43]>; - def W12 : AFPR128<12, "w12", [D12_64]>, DwarfRegNum<[44]>; - def W13 : AFPR128<13, "w13", [D13_64]>, DwarfRegNum<[45]>; - def W14 : AFPR128<14, "w14", [D14_64]>, DwarfRegNum<[46]>; - def W15 : AFPR128<15, "w15", [D15_64]>, DwarfRegNum<[47]>; - def W16 : AFPR128<16, "w16", [D16_64]>, DwarfRegNum<[48]>; - def W17 : AFPR128<17, "w17", [D17_64]>, DwarfRegNum<[49]>; - def W18 : AFPR128<18, "w18", [D18_64]>, DwarfRegNum<[50]>; - def W19 : AFPR128<19, "w19", [D19_64]>, DwarfRegNum<[51]>; - def W20 : AFPR128<20, "w20", [D20_64]>, DwarfRegNum<[52]>; - def W21 : AFPR128<21, "w21", [D21_64]>, DwarfRegNum<[53]>; - def W22 : AFPR128<22, "w22", [D22_64]>, DwarfRegNum<[54]>; - def W23 : AFPR128<23, "w23", [D23_64]>, DwarfRegNum<[55]>; - def W24 : AFPR128<24, "w24", [D24_64]>, DwarfRegNum<[56]>; - def W25 : AFPR128<25, "w25", [D25_64]>, DwarfRegNum<[57]>; - def W26 : AFPR128<26, "w26", [D26_64]>, DwarfRegNum<[58]>; - def W27 : AFPR128<27, "w27", [D27_64]>, DwarfRegNum<[59]>; - def W28 : AFPR128<28, "w28", [D28_64]>, DwarfRegNum<[60]>; - def W29 : AFPR128<29, "w29", [D29_64]>, DwarfRegNum<[61]>; - def W30 : AFPR128<30, "w30", [D30_64]>, DwarfRegNum<[62]>; - def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>; + foreach I = 0-31 in + def W#I : AFPR128("D"#I#"_64")]>, + DwarfRegNum<[!add(I, 32)]>; // Hi/Lo registers - def HI0 : Register<"ac0">, DwarfRegNum<[64]>; - def HI1 : Register<"ac1">, DwarfRegNum<[176]>; - def HI2 : Register<"ac2">, DwarfRegNum<[178]>; - def HI3 : Register<"ac3">, DwarfRegNum<[180]>; - def LO0 : Register<"ac0">, DwarfRegNum<[65]>; - def LO1 : Register<"ac1">, DwarfRegNum<[177]>; - def LO2 : Register<"ac2">, DwarfRegNum<[179]>; - def LO3 : Register<"ac3">, DwarfRegNum<[181]>; + def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; + def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; + def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; + def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; + def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; + def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; + def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; + def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; let SubRegIndices = [sub_32] in { def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; @@ -227,11 +201,20 @@ let Namespace = "Mips" in { foreach I = 0-7 in def FCC#I : MipsReg<#I, "fcc"#I>; + // COP2 registers. + foreach I = 0-31 in + def COP2#I : MipsReg<#I, ""#I>; + + // COP3 registers. + foreach I = 0-31 in + def COP3#I : MipsReg<#I, ""#I>; + // PC register def PC : Register<"pc">; // Hardware register $29 - def HWR29 : MipsReg<29, "29">; + foreach I = 0-31 in + def HWR#I : MipsReg<#I, ""#I>; // Accum registers foreach I = 0-3 in @@ -257,6 +240,25 @@ let Namespace = "Mips" in { def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, DSPOutFlag21, DSPOutFlag22, DSPOutFlag23]>; + + // MSA-ASE control registers. + def MSAIR : MipsReg<0, "0">; + def MSACSR : MipsReg<1, "1">; + def MSAAccess : MipsReg<2, "2">; + def MSASave : MipsReg<3, "3">; + def MSAModify : MipsReg<4, "4">; + def MSARequest : MipsReg<5, "5">; + def MSAMap : MipsReg<6, "6">; + def MSAUnmap : MipsReg<7, "7">; + + // Octeon multiplier and product registers + def MPL0 : MipsReg<0, "mpl0">; + def MPL1 : MipsReg<1, "mpl1">; + def MPL2 : MipsReg<2, "mpl2">; + def P0 : MipsReg<0, "p0">; + def P1 : MipsReg<1, "p1">; + def P2 : MipsReg<2, "p2">; + } //===----------------------------------------------------------------------===// @@ -321,6 +323,9 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // * FGR32 - 32 32-bit registers (single float only mode) def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; +def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, + Unallocatable; + def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments D0, D1, @@ -335,6 +340,15 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; +// Used to reserve odd registers when given -mattr=+nooddspreg +// FIXME: Remove double precision registers from this set. +def OddSP : RegisterClass<"Mips", [f32], 32, + (add (decimate (sequence "F%u", 1, 31), 2), + (decimate (sequence "F_HI%u", 1, 31), 2), + (decimate (sequence "D%u", 1, 15), 2), + (decimate (sequence "D%u_64", 1, 31), 2))>, + Unallocatable; + // FP control registers. def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, Unallocatable; @@ -343,8 +357,21 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, Unallocatable; -def MSA128: RegisterClass<"Mips", [v16i8, v8i16, v4i32, v2i64], 128, - (sequence "W%u", 0, 31)>; +// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. +// This class allows us to represent this in codegen patterns. +def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; + +def MSA128B: RegisterClass<"Mips", [v16i8], 128, + (sequence "W%u", 0, 31)>; +def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, + (sequence "W%u", 0, 31)>; +def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, + (sequence "W%u", 0, 31)>; +def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, + (sequence "W%u", 0, 31)>; + +def MSACtrl: RegisterClass<"Mips", [i32], 32, (add + MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; // Hi/Lo Registers def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; @@ -355,7 +382,8 @@ def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; // Hardware registers -def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; +def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>, + Unallocatable; // Accumulator Registers def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { @@ -372,49 +400,85 @@ def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; +// Coprocessor 2 registers. +def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, + Unallocatable; + +// Coprocessor 3 registers. +def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, + Unallocatable; + +// Octeon multiplier and product registers +def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, + Unallocatable; +def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, + Unallocatable; + // Register Operands. class MipsAsmRegOperand : AsmOperandClass { - let RenderMethod = "addRegAsmOperands"; -} -def GPR32AsmOperand : MipsAsmRegOperand { - let Name = "GPR32Asm"; - let ParserMethod = "parseGPR32"; + let ParserMethod = "ParseAnyRegister"; } def GPR64AsmOperand : MipsAsmRegOperand { - let Name = "GPR64Asm"; - let ParserMethod = "parseGPR64"; + let Name = "GPR64AsmReg"; + let PredicateMethod = "isGPRAsmReg"; +} + +def GPR32AsmOperand : MipsAsmRegOperand { + let Name = "GPR32AsmReg"; + let PredicateMethod = "isGPRAsmReg"; } def ACC64DSPAsmOperand : MipsAsmRegOperand { - let Name = "ACC64DSPAsm"; - let ParserMethod = "parseACC64DSP"; + let Name = "ACC64DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def HI32DSPAsmOperand : MipsAsmRegOperand { + let Name = "HI32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def LO32DSPAsmOperand : MipsAsmRegOperand { + let Name = "LO32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; } def CCRAsmOperand : MipsAsmRegOperand { - let Name = "CCRAsm"; - let ParserMethod = "parseCCRRegs"; + let Name = "CCRAsmReg"; } def AFGR64AsmOperand : MipsAsmRegOperand { - let Name = "AFGR64Asm"; - let ParserMethod = "parseAFGR64Regs"; + let Name = "AFGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FGR64AsmOperand : MipsAsmRegOperand { - let Name = "FGR64Asm"; - let ParserMethod = "parseFGR64Regs"; + let Name = "FGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FGR32AsmOperand : MipsAsmRegOperand { - let Name = "FGR32Asm"; - let ParserMethod = "parseFGR32Regs"; + let Name = "FGR32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FGRH32AsmOperand : MipsAsmRegOperand { + let Name = "FGRH32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FCCRegsAsmOperand : MipsAsmRegOperand { - let Name = "FCCRegsAsm"; - let ParserMethod = "parseFCCRegs"; + let Name = "FCCAsmReg"; +} + +def MSA128AsmOperand : MipsAsmRegOperand { + let Name = "MSA128AsmReg"; +} + +def MSACtrlAsmOperand : MipsAsmRegOperand { + let Name = "MSACtrlAsmReg"; } def GPR32Opnd : RegisterOperand { @@ -434,8 +498,15 @@ def CCROpnd : RegisterOperand { } def HWRegsAsmOperand : MipsAsmRegOperand { - let Name = "HWRegsAsm"; - let ParserMethod = "parseHWRegs"; + let Name = "HWRegsAsmReg"; +} + +def COP2AsmOperand : MipsAsmRegOperand { + let Name = "COP2AsmReg"; +} + +def COP3AsmOperand : MipsAsmRegOperand { + let Name = "COP3AsmReg"; } def HWRegsOpnd : RegisterOperand { @@ -454,10 +525,57 @@ def FGR32Opnd : RegisterOperand { let ParserMatchClass = FGR32AsmOperand; } +def FGRCCOpnd : RegisterOperand { + // The assembler doesn't use register classes so we can re-use + // FGR32AsmOperand. + let ParserMatchClass = FGR32AsmOperand; +} + +def FGRH32Opnd : RegisterOperand { + let ParserMatchClass = FGRH32AsmOperand; +} + def FCCRegsOpnd : RegisterOperand { let ParserMatchClass = FCCRegsAsmOperand; } +def LO32DSPOpnd : RegisterOperand { + let ParserMatchClass = LO32DSPAsmOperand; +} + +def HI32DSPOpnd : RegisterOperand { + let ParserMatchClass = HI32DSPAsmOperand; +} + def ACC64DSPOpnd : RegisterOperand { let ParserMatchClass = ACC64DSPAsmOperand; } + +def COP2Opnd : RegisterOperand { + let ParserMatchClass = COP2AsmOperand; +} + +def COP3Opnd : RegisterOperand { + let ParserMatchClass = COP3AsmOperand; +} + +def MSA128BOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128HOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128WOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128DOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128CROpnd : RegisterOperand { + let ParserMatchClass = MSACtrlAsmOperand; +} +