X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsRegisterInfo.td;h=74dfa4fe7d9cd5cd51e08c0c6ceb46a4de3cd887;hb=cb43f81fc54572b1dddec2370b2583e3f69a1bfc;hp=6323da3788507e1d81aec283dfa64eb5f7402266;hpb=24a071b8c5565c9bdf7f92af487dd70b3026c4f9;p=oota-llvm.git

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 6323da37885..74dfa4fe7d9 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -341,9 +341,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
 
 // Used to reserve odd registers when given -mattr=+nooddspreg
+// FIXME: Remove double precision registers from this set.
 def OddSP : RegisterClass<"Mips", [f32], 32,
                           (add (decimate (sequence "F%u", 1, 31), 2),
-                               (decimate (sequence "F_HI%u", 1, 31), 2))>,
+                               (decimate (sequence "F_HI%u", 1, 31), 2),
+                               (decimate (sequence "D%u", 1, 15), 2),
+                               (decimate (sequence "D%u_64", 1, 31), 2))>,
             Unallocatable;
 
 // FP control registers.