X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsRegisterInfo.td;h=875a596eb4aadd7a644a6f32583e42431c4c114d;hb=805a83c0419aa453b78b2a062f46dc7f72137f79;hp=377f1aa1c21782540562fa1f62a6df2722244607;hpb=94a88c49b0e87ee8c911669ff6c6bbd31b912542;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 377f1aa1c21..875a596eb4a 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -11,9 +11,8 @@ // Declarations that describe the MIPS register file //===----------------------------------------------------------------------===// let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex<32>; -def sub_fpodd : SubRegIndex<32, 32>; def sub_32 : SubRegIndex<32>; +def sub_64 : SubRegIndex<64>; def sub_lo : SubRegIndex<32>; def sub_hi : SubRegIndex<32, 32>; def sub_dsp16_19 : SubRegIndex<4, 16>; @@ -54,17 +53,24 @@ class FPR Enc, string n> : MipsReg; // Mips 64-bit (aliased) FPU Registers class AFPR Enc, string n, list subregs> : MipsRegWithSubRegs { - let SubRegIndices = [sub_fpeven, sub_fpodd]; + let SubRegIndices = [sub_lo, sub_hi]; let CoveredBySubRegs = 1; } class AFPR64 Enc, string n, list subregs> : MipsRegWithSubRegs { - let SubRegIndices = [sub_32]; + let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; +} + +// Mips 128-bit (aliased) MSA Registers +class AFPR128 Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_64]; } // Accumulator Registers -class ACC Enc, string n, list subregs> +class ACCReg Enc, string n, list subregs> : MipsRegWithSubRegs { let SubRegIndices = [sub_lo, sub_hi]; let CoveredBySubRegs = 1; @@ -150,6 +156,10 @@ let Namespace = "Mips" in { foreach I = 0-31 in def F#I : FPR, DwarfRegNum<[!add(I, 32)]>; + // Higher half of 64-bit FP registers. + foreach I = 0-31 in + def F_HI#I : FPR, DwarfRegNum<[!add(I, 32)]>; + /// Mips Double point precision FPU Registers (aliased /// with the single precision to hold 64 bit values) foreach I = 0-15 in @@ -159,22 +169,28 @@ let Namespace = "Mips" in { /// Mips Double point precision FPU Registers in MFP64 mode. foreach I = 0-31 in - def D#I#_64 : AFPR64("F"#I)]>, + def D#I#_64 : AFPR64("F"#I), !cast("F_HI"#I)]>, DwarfRegNum<[!add(I, 32)]>; + /// Mips MSA registers + /// MSA and FPU cannot both be present unless the FPU has 64-bit registers + foreach I = 0-31 in + def W#I : AFPR128("D"#I#"_64")]>, + DwarfRegNum<[!add(I, 32)]>; + // Hi/Lo registers - def HI : Register<"ac0">, DwarfRegNum<[64]>; - def HI1 : Register<"ac1">, DwarfRegNum<[176]>; - def HI2 : Register<"ac2">, DwarfRegNum<[178]>; - def HI3 : Register<"ac3">, DwarfRegNum<[180]>; - def LO : Register<"ac0">, DwarfRegNum<[65]>; - def LO1 : Register<"ac1">, DwarfRegNum<[177]>; - def LO2 : Register<"ac2">, DwarfRegNum<[179]>; - def LO3 : Register<"ac3">, DwarfRegNum<[181]>; + def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; + def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; + def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; + def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; + def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; + def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; + def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; + def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; let SubRegIndices = [sub_32] in { - def HI64 : RegisterWithSubRegs<"hi", [HI]>; - def LO64 : RegisterWithSubRegs<"lo", [LO]>; + def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; + def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; } // FP control registers. @@ -185,19 +201,27 @@ let Namespace = "Mips" in { foreach I = 0-7 in def FCC#I : MipsReg<#I, "fcc"#I>; + // COP2 registers. + foreach I = 0-31 in + def COP2#I : MipsReg<#I, ""#I>; + + // COP3 registers. + foreach I = 0-31 in + def COP3#I : MipsReg<#I, ""#I>; + // PC register def PC : Register<"pc">; // Hardware register $29 - def HWR29 : MipsReg<29, "29">; + foreach I = 0-31 in + def HWR#I : MipsReg<#I, ""#I>; // Accum registers - def AC0 : ACC<0, "ac0", [LO, HI]>; - def AC1 : ACC<1, "ac1", [LO1, HI1]>; - def AC2 : ACC<2, "ac2", [LO2, HI2]>; - def AC3 : ACC<3, "ac3", [LO3, HI3]>; + foreach I = 0-3 in + def AC#I : ACCReg<#I, "ac"#I, + [!cast("LO"#I), !cast("HI"#I)]>; - def AC0_64 : ACC<0, "ac0", [LO64, HI64]>; + def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; // DSP-ASE control register fields. def DSPPos : Register<"">; @@ -216,6 +240,25 @@ let Namespace = "Mips" in { def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, DSPOutFlag21, DSPOutFlag22, DSPOutFlag23]>; + + // MSA-ASE control registers. + def MSAIR : MipsReg<0, "0">; + def MSACSR : MipsReg<1, "1">; + def MSAAccess : MipsReg<2, "2">; + def MSASave : MipsReg<3, "3">; + def MSAModify : MipsReg<4, "4">; + def MSARequest : MipsReg<5, "5">; + def MSAMap : MipsReg<6, "6">; + def MSAUnmap : MipsReg<7, "7">; + + // Octeon multiplier and product registers + def MPL0 : MipsReg<0, "mpl0">; + def MPL1 : MipsReg<1, "mpl1">; + def MPL2 : MipsReg<2, "mpl2">; + def P0 : MipsReg<0, "p0">; + def P1 : MipsReg<1, "p1">; + def P2 : MipsReg<2, "p2">; + } //===----------------------------------------------------------------------===// @@ -238,7 +281,7 @@ class GPR32Class regTypes> : K0, K1, GP, SP, FP, RA)>; def GPR32 : GPR32Class<[i32]>; -def DSPRegs : GPR32Class<[v4i8, v2i16]>; +def DSPR : GPR32Class<[v4i8, v2i16]>; def GPR64 : RegisterClass<"Mips", [i64], 64, (add // Reserved @@ -280,6 +323,9 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // * FGR32 - 32 32-bit registers (single float only mode) def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; +def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, + Unallocatable; + def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments D0, D1, @@ -302,75 +348,124 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, Unallocatable; +def MSA128B: RegisterClass<"Mips", [v16i8], 128, + (sequence "W%u", 0, 31)>; +def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, + (sequence "W%u", 0, 31)>; +def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, + (sequence "W%u", 0, 31)>; +def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, + (sequence "W%u", 0, 31)>; + +def MSACtrl: RegisterClass<"Mips", [i32], 32, (add + MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; + // Hi/Lo Registers -def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; -def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>; -def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>; -def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>; -def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>; -def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; +def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; +def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; +def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; +def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; +def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; +def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; // Hardware registers -def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; +def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>, + Unallocatable; // Accumulator Registers -def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> { +def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { let Size = 64; } -def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { +def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { let Size = 128; } -def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { +def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { let Size = 64; } def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; +// Coprocessor 2 registers. +def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, + Unallocatable; + +// Coprocessor 3 registers. +def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, + Unallocatable; + +// Octeon multiplier and product registers +def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, + Unallocatable; +def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, + Unallocatable; + // Register Operands. class MipsAsmRegOperand : AsmOperandClass { - let RenderMethod = "addRegAsmOperands"; + let ParserMethod = "ParseAnyRegister"; +} + +def GPR64AsmOperand : MipsAsmRegOperand { + let Name = "GPR64AsmReg"; + let PredicateMethod = "isGPRAsmReg"; } + def GPR32AsmOperand : MipsAsmRegOperand { - let Name = "GPR32Asm"; - let ParserMethod = "parseGPR32"; + let Name = "GPR32AsmReg"; + let PredicateMethod = "isGPRAsmReg"; } -def GPR64AsmOperand : MipsAsmRegOperand { - let Name = "GPR64Asm"; - let ParserMethod = "parseGPR64"; +def ACC64DSPAsmOperand : MipsAsmRegOperand { + let Name = "ACC64DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; } -def ACRegsDSPAsmOperand : MipsAsmRegOperand { - let Name = "ACRegsDSPAsm"; - let ParserMethod = "parseACRegsDSP"; +def HI32DSPAsmOperand : MipsAsmRegOperand { + let Name = "HI32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def LO32DSPAsmOperand : MipsAsmRegOperand { + let Name = "LO32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; } def CCRAsmOperand : MipsAsmRegOperand { - let Name = "CCRAsm"; - let ParserMethod = "parseCCRRegs"; + let Name = "CCRAsmReg"; } def AFGR64AsmOperand : MipsAsmRegOperand { - let Name = "AFGR64Asm"; - let ParserMethod = "parseAFGR64Regs"; + let Name = "AFGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FGR64AsmOperand : MipsAsmRegOperand { - let Name = "FGR64Asm"; - let ParserMethod = "parseFGR64Regs"; + let Name = "FGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FGR32AsmOperand : MipsAsmRegOperand { - let Name = "FGR32Asm"; - let ParserMethod = "parseFGR32Regs"; + let Name = "FGR32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FGRH32AsmOperand : MipsAsmRegOperand { + let Name = "FGRH32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; } def FCCRegsAsmOperand : MipsAsmRegOperand { - let Name = "FCCRegsAsm"; - let ParserMethod = "parseFCCRegs"; + let Name = "FCCAsmReg"; +} + +def MSA128AsmOperand : MipsAsmRegOperand { + let Name = "MSA128AsmReg"; +} + +def MSACtrlAsmOperand : MipsAsmRegOperand { + let Name = "MSACtrlAsmReg"; } def GPR32Opnd : RegisterOperand { @@ -381,35 +476,87 @@ def GPR64Opnd : RegisterOperand { let ParserMatchClass = GPR64AsmOperand; } +def DSPROpnd : RegisterOperand { + let ParserMatchClass = GPR32AsmOperand; +} + def CCROpnd : RegisterOperand { let ParserMatchClass = CCRAsmOperand; } def HWRegsAsmOperand : MipsAsmRegOperand { - let Name = "HWRegsAsm"; - let ParserMethod = "parseHWRegs"; + let Name = "HWRegsAsmReg"; +} + +def COP2AsmOperand : MipsAsmRegOperand { + let Name = "COP2AsmReg"; +} + +def COP3AsmOperand : MipsAsmRegOperand { + let Name = "COP3AsmReg"; } def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def AFGR64RegsOpnd : RegisterOperand { +def AFGR64Opnd : RegisterOperand { let ParserMatchClass = AFGR64AsmOperand; } -def FGR64RegsOpnd : RegisterOperand { +def FGR64Opnd : RegisterOperand { let ParserMatchClass = FGR64AsmOperand; } -def FGR32RegsOpnd : RegisterOperand { +def FGR32Opnd : RegisterOperand { let ParserMatchClass = FGR32AsmOperand; } +def FGRH32Opnd : RegisterOperand { + let ParserMatchClass = FGRH32AsmOperand; +} + def FCCRegsOpnd : RegisterOperand { let ParserMatchClass = FCCRegsAsmOperand; } -def ACRegsDSPOpnd : RegisterOperand { - let ParserMatchClass = ACRegsDSPAsmOperand; +def LO32DSPOpnd : RegisterOperand { + let ParserMatchClass = LO32DSPAsmOperand; +} + +def HI32DSPOpnd : RegisterOperand { + let ParserMatchClass = HI32DSPAsmOperand; +} + +def ACC64DSPOpnd : RegisterOperand { + let ParserMatchClass = ACC64DSPAsmOperand; +} + +def COP2Opnd : RegisterOperand { + let ParserMatchClass = COP2AsmOperand; +} + +def COP3Opnd : RegisterOperand { + let ParserMatchClass = COP3AsmOperand; +} + +def MSA128BOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128HOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128WOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128DOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128CROpnd : RegisterOperand { + let ParserMatchClass = MSACtrlAsmOperand; } +