X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSubtarget.cpp;h=af83d61f091941261dcfa6939d54726902fabca6;hb=f6679de299c8a73a77ee5e145b04b3394b44354e;hp=9c69e0459d3444bec1ca43b8f4c1ee07d8036954;hpb=94214703d97d8d9dfca88174ffc7e94820a85e62;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 9c69e0459d3..af83d61f091 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -1,4 +1,4 @@ -//===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===// +//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// // // The LLVM Compiler Infrastructure // @@ -7,56 +7,196 @@ // //===----------------------------------------------------------------------===// // -// This file implements the Mips specific subclass of TargetSubtarget. +// This file implements the Mips specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// -#include "MipsSubtarget.h" +#define DEBUG_TYPE "mips-subtarget" + +#include "MipsMachineFunction.h" #include "Mips.h" +#include "MipsRegisterInfo.h" +#include "MipsSubtarget.h" +#include "MipsTargetMachine.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/Function.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" -#define GET_SUBTARGETINFO_CTOR -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC -#include "MipsGenSubtarget.inc" +#define GET_SUBTARGETINFO_CTOR +#include "MipsGenSubtargetInfo.inc" + using namespace llvm; +// FIXME: Maybe this should be on by default when Mips16 is specified +// +static cl::opt Mixed16_32( + "mips-mixed-16-32", + cl::init(false), + cl::desc("Allow for a mixture of Mips16 " + "and Mips32 code in a single source file"), + cl::Hidden); + +static cl::opt Mips_Os16( + "mips-os16", + cl::init(false), + cl::desc("Compile all functions that don' use " + "floating point as Mips 16"), + cl::Hidden); + +static cl::opt +Mips16HardFloat("mips16-hard-float", cl::NotHidden, + cl::desc("MIPS: mips16 hard float enable."), + cl::init(false)); + +static cl::opt +Mips16ConstantIslands( + "mips16-constant-islands", cl::NotHidden, + cl::desc("MIPS: mips16 constant islands enable."), + cl::init(true)); + +/// Select the Mips CPU for the given triple and cpu name. +/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp +static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { + if (CPU.empty() || CPU == "generic") { + Triple TheTriple(TT); + if (TheTriple.getArch() == Triple::mips || + TheTriple.getArch() == Triple::mipsel) + CPU = "mips32"; + else + CPU = "mips64"; + } + return CPU; +} + +void MipsSubtarget::anchor() { } + MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool little) : - MipsGenSubtargetInfo(), - MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), - IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true), - HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false), - HasSwap(false), HasBitCount(false) + const std::string &FS, bool little, + Reloc::Model _RM, MipsTargetMachine *_TM) : + MipsGenSubtargetInfo(TT, CPU, FS), + MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little), + IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), + IsLinux(true), HasSEInReg(false), HasCondMov(false), HasSwap(false), + HasBitCount(false), HasFPIdx(false), + InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), + InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), + AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), + RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) { std::string CPUName = CPU; - if (CPUName.empty()) - CPUName = "mips1"; - MipsArchVersion = Mips1; + CPUName = selectMipsCPU(TT, CPUName); // Parse features string. - ParseSubtargetFeatures(FS, CPUName); + ParseSubtargetFeatures(CPUName, FS); + + if (InMips16Mode && !TM->Options.UseSoftFloat) { + // Hard float for mips16 means essentially to compile as soft float + // but to use a runtime library for soft float that is written with + // native mips32 floating point instructions (those runtime routines + // run in mips32 hard float mode). + TM->Options.UseSoftFloat = true; + TM->Options.FloatABIType = FloatABI::Soft; + InMips16HardFloat = true; + } + + PreviousInMips16Mode = InMips16Mode; // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); + // Assert exactly one ABI was chosen. + assert(MipsABI != UnknownABI); + assert((((getFeatureBits() & Mips::FeatureO32) != 0) + + ((getFeatureBits() & Mips::FeatureEABI) != 0) + + ((getFeatureBits() & Mips::FeatureN32) != 0) + + ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); + + // Check if Architecture and ABI are compatible. + assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) || + (hasMips64() && (isABI_N32() || isABI_N64()))) && + "Invalid Arch & ABI pair."); + + if (hasMSA() && !isFP64bit()) + report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " + "See -mattr=+fp64.", + false); + // Is the target system Linux ? if (TT.find("linux") == std::string::npos) IsLinux = false; - // When only the target triple is specified and is - // a allegrex target, set the features. We also match - // big and little endian allegrex cores (dont really - // know if a big one exists) - if (TT.find("mipsallegrex") != std::string::npos || - TT.find("psp") != std::string::npos) { - MipsABI = EABI; - IsSingleFloat = true; - MipsArchVersion = Mips2; - HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet) - HasSEInReg = true; - HasBitCount = true; - HasSwap = true; - HasCondMov = true; + // Set UseSmallSection. + UseSmallSection = !IsLinux && (RM == Reloc::Static); + // set some subtarget specific features + if (inMips16Mode()) + HasBitCount=false; +} + +bool +MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, + TargetSubtargetInfo::AntiDepBreakMode &Mode, + RegClassVector &CriticalPathRCs) const { + Mode = TargetSubtargetInfo::ANTIDEP_NONE; + CriticalPathRCs.clear(); + CriticalPathRCs.push_back(hasMips64() ? + &Mips::GPR64RegClass : &Mips::GPR32RegClass); + return OptLevel >= CodeGenOpt::Aggressive; +} + +//FIXME: This logic for reseting the subtarget along with +// the helper classes can probably be simplified but there are a lot of +// cases so we will defer rewriting this to later. +// +void MipsSubtarget::resetSubtarget(MachineFunction *MF) { + bool ChangeToMips16 = false, ChangeToNoMips16 = false; + DEBUG(dbgs() << "resetSubtargetFeatures" << "\n"); + AttributeSet FnAttrs = MF->getFunction()->getAttributes(); + ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, + "mips16"); + ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, + "nomips16"); + assert (!(ChangeToMips16 & ChangeToNoMips16) && + "mips16 and nomips16 specified on the same function"); + if (ChangeToMips16) { + if (PreviousInMips16Mode) + return; + OverrideMode = Mips16Override; + PreviousInMips16Mode = true; + TM->setHelperClassesMips16(); + return; + } else if (ChangeToNoMips16) { + if (!PreviousInMips16Mode) + return; + OverrideMode = NoMips16Override; + PreviousInMips16Mode = false; + TM->setHelperClassesMipsSE(); + return; + } else { + if (OverrideMode == NoOverride) + return; + OverrideMode = NoOverride; + DEBUG(dbgs() << "back to default" << "\n"); + if (inMips16Mode() && !PreviousInMips16Mode) { + TM->setHelperClassesMips16(); + PreviousInMips16Mode = true; + } else if (!inMips16Mode() && PreviousInMips16Mode) { + TM->setHelperClassesMipsSE(); + PreviousInMips16Mode = false; + } + return; } } + +bool MipsSubtarget::mipsSEUsesSoftFloat() const { + return TM->Options.UseSoftFloat && !InMips16HardFloat; +} + +bool MipsSubtarget::useConstantIslands() { + DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); + return Mips16ConstantIslands; +}