X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsTargetMachine.h;h=a5aa39bc9f4d37d22631c549c0ccce776bc2b13b;hb=7ef85447c950ef801414251a2ce49d2564cbf5da;hp=bba9111a064c6e4bb35fba2c2e4e4097993141c2;hpb=c4cc40c001e23dbeb6cb9953715177ccb314fbf1;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index bba9111a064..a5aa39bc9f4 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -1,4 +1,4 @@ -//===-- MipsTargetMachine.h - Define TargetMachine for Mips -00--*- C++ -*-===// +//===-- MipsTargetMachine.h - Define TargetMachine for Mips -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -14,79 +14,108 @@ #ifndef MIPSTARGETMACHINE_H #define MIPSTARGETMACHINE_H -#include "MipsSubtarget.h" -#include "MipsInstrInfo.h" -#include "MipsISelLowering.h" #include "MipsFrameLowering.h" +#include "MipsISelLowering.h" +#include "MipsInstrInfo.h" +#include "MipsJITInfo.h" #include "MipsSelectionDAGInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetData.h" +#include "MipsSubtarget.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetFrameLowering.h" -#include "MipsJITInfo.h" +#include "llvm/Target/TargetMachine.h" namespace llvm { - class formatted_raw_ostream; - - class MipsTargetMachine : public LLVMTargetMachine { - MipsSubtarget Subtarget; - const TargetData DataLayout; // Calculates type size & alignment - MipsInstrInfo InstrInfo; - MipsFrameLowering FrameLowering; - MipsTargetLowering TLInfo; - MipsSelectionDAGInfo TSInfo; - MipsJITInfo JITInfo; - - public: - MipsTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, +class formatted_raw_ostream; +class MipsRegisterInfo; + +class MipsTargetMachine : public LLVMTargetMachine { + MipsSubtarget Subtarget; + const DataLayout DL; // Calculates type size & alignment + std::unique_ptr InstrInfo; + std::unique_ptr FrameLowering; + std::unique_ptr TLInfo; + std::unique_ptr InstrInfo16; + std::unique_ptr FrameLowering16; + std::unique_ptr TLInfo16; + std::unique_ptr InstrInfoSE; + std::unique_ptr FrameLoweringSE; + std::unique_ptr TLInfoSE; + MipsSelectionDAGInfo TSInfo; + const InstrItineraryData &InstrItins; + MipsJITInfo JITInfo; + +public: + MipsTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, + bool isLittle); + + virtual ~MipsTargetMachine() {} + + void addAnalysisPasses(PassManagerBase &PM) override; + + const MipsInstrInfo *getInstrInfo() const override + { return InstrInfo.get(); } + const TargetFrameLowering *getFrameLowering() const override + { return FrameLowering.get(); } + const MipsSubtarget *getSubtargetImpl() const override + { return &Subtarget; } + const DataLayout *getDataLayout() const override + { return &DL;} + + const InstrItineraryData *getInstrItineraryData() const override { + return Subtarget.inMips16Mode() ? nullptr : &InstrItins; + } + + MipsJITInfo *getJITInfo() override { return &JITInfo; } + + const MipsRegisterInfo *getRegisterInfo() const override { + return &InstrInfo->getRegisterInfo(); + } + + const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); + } + + const MipsSelectionDAGInfo* getSelectionDAGInfo() const override { + return &TSInfo; + } + + // Pass Pipeline Configuration + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override; + + // Set helper classes + void setHelperClassesMips16(); + + void setHelperClassesMipsSE(); + + +}; + +/// MipsebTargetMachine - Mips32/64 big endian target machine. +/// +class MipsebTargetMachine : public MipsTargetMachine { + virtual void anchor(); +public: + MipsebTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - bool isLittle); - - virtual const MipsInstrInfo *getInstrInfo() const - { return &InstrInfo; } - virtual const TargetFrameLowering *getFrameLowering() const - { return &FrameLowering; } - virtual const MipsSubtarget *getSubtargetImpl() const - { return &Subtarget; } - virtual const TargetData *getTargetData() const - { return &DataLayout;} - virtual MipsJITInfo *getJITInfo() - { return &JITInfo; } - - - virtual const MipsRegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); - } - - virtual const MipsTargetLowering *getTargetLowering() const { - return &TLInfo; - } - - virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const { - return &TSInfo; - } - - // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, - CodeGenOpt::Level OptLevel); - virtual bool addPreRegAlloc(PassManagerBase &PM, - CodeGenOpt::Level OptLevel); - virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level); - virtual bool addCodeEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - JITCodeEmitter &JCE); - - }; - -/// MipselTargetMachine - Mipsel target machine. + CodeGenOpt::Level OL); +}; + +/// MipselTargetMachine - Mips32/64 little endian target machine. /// class MipselTargetMachine : public MipsTargetMachine { + virtual void anchor(); public: MipselTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); }; } // End llvm namespace