X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPTX%2FPTXISelLowering.cpp;h=3307d91a618803749a7e0a69dcced775d1e2aee3;hb=10820d9a9754987533fd7a8b50b03831781cbd65;hp=c439d4c17313f5791b859dac1508066c24a04665;hpb=ca9215970d3a7fb9450d4ad1c22a2418f686a1a4;p=oota-llvm.git diff --git a/lib/Target/PTX/PTXISelLowering.cpp b/lib/Target/PTX/PTXISelLowering.cpp index c439d4c1731..3307d91a618 100644 --- a/lib/Target/PTX/PTXISelLowering.cpp +++ b/lib/Target/PTX/PTXISelLowering.cpp @@ -236,37 +236,7 @@ SDValue PTXTargetLowering:: else { for (unsigned i = 0, e = Ins.size(); i != e; ++i) { EVT RegVT = Ins[i].VT; - TargetRegisterClass* TRC = 0; - int OpCode; - - // Determine which register class we need - if (RegVT == MVT::i1) { - TRC = PTX::RegPredRegisterClass; - OpCode = PTX::READPARAMPRED; - } - else if (RegVT == MVT::i16) { - TRC = PTX::RegI16RegisterClass; - OpCode = PTX::READPARAMI16; - } - else if (RegVT == MVT::i32) { - TRC = PTX::RegI32RegisterClass; - OpCode = PTX::READPARAMI32; - } - else if (RegVT == MVT::i64) { - TRC = PTX::RegI64RegisterClass; - OpCode = PTX::READPARAMI64; - } - else if (RegVT == MVT::f32) { - TRC = PTX::RegF32RegisterClass; - OpCode = PTX::READPARAMF32; - } - else if (RegVT == MVT::f64) { - TRC = PTX::RegF64RegisterClass; - OpCode = PTX::READPARAMF64; - } - else { - llvm_unreachable("Unknown parameter type"); - } + TargetRegisterClass* TRC = getRegClassFor(RegVT); // Use a unique index in the instruction to prevent instruction folding. // Yes, this is a hack. @@ -275,10 +245,6 @@ SDValue PTXTargetLowering:: SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain, Index); - SDValue Flag = ArgValue.getValue(1); - - SDValue Copy = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); - SDValue RegValue = DAG.getRegister(Reg, RegVT); InVals.push_back(ArgValue); MFI->addArgReg(Reg); @@ -393,8 +359,8 @@ PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee, "Calls are not handled for the target device"); std::vector Ops; - // The layout of the ops will be [Chain, Ins, Callee, Outs] - Ops.resize(Outs.size() + Ins.size() + 2); + // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs] + Ops.resize(Outs.size() + Ins.size() + 4); Ops[0] = Chain; @@ -403,11 +369,12 @@ PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee, assert(cast(GV)->getCallingConv() == CallingConv::PTX_Device && "PTX function calls must be to PTX device functions"); Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); - Ops[Ins.size()+1] = Callee; + Ops[Ins.size()+2] = Callee; // Generate STORE_PARAM nodes for each function argument. In PTX, function // arguments are explicitly stored into .param variables and passed as // arguments. There is no register/stack-based calling convention in PTX. + Ops[Ins.size()+3] = DAG.getTargetConstant(OutVals.size(), MVT::i32); for (unsigned i = 0; i != OutVals.size(); ++i) { unsigned Size = OutVals[i].getValueType().getSizeInBits(); unsigned Param = PM.addLocalParam(Size); @@ -416,19 +383,20 @@ PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee, MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, ParamValue, OutVals[i]); - Ops[i+Ins.size()+2] = ParamValue; + Ops[i+Ins.size()+4] = ParamValue; } std::vector InParams; // Generate list of .param variables to hold the return value(s). + Ops[1] = DAG.getTargetConstant(Ins.size(), MVT::i32); for (unsigned i = 0; i < Ins.size(); ++i) { unsigned Size = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addLocalParam(Size); const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); - Ops[i+1] = ParamValue; + Ops[i+2] = ParamValue; InParams.push_back(ParamValue); } @@ -446,3 +414,9 @@ PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee, return Chain; } + +unsigned PTXTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT) { + // All arguments consist of one "register," regardless of the type. + return 1; +} +