X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPC.td;h=d3bcbaec030429a7aa35a6acec709a1ff5ce0ece;hb=5bb16fdbb363abee2b9495116ff1a97568460cae;hp=8b9e3a7ac140176e1a00f11fec728085d1b1b0bb;hpb=19c95507443ebd4f1cee80917d540c8bd27f8fe1;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 8b9e3a7ac14..d3bcbaec030 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -1,10 +1,10 @@ -//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===// -// +//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// // // This is the top level entry point for the PowerPC target. @@ -13,22 +13,53 @@ // Get the target-independent interfaces which we are implementing. // -include "../Target.td" +include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // PowerPC Subtarget features. // -def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true", +//===----------------------------------------------------------------------===// +// CPU Directives // +//===----------------------------------------------------------------------===// + +def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; +def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; +def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; +def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; +def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; +def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; +def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; +def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; +def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; +def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; +def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; +def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; +def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", + "PPC::DIR_E500mc", "">; +def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", + "PPC::DIR_E5500", "">; +def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; +def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; + +def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; -def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true", - "Enable 64-bit registers [beta]">; +def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", + "Enable 64-bit registers usage for ppc32 [beta]">; def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", "Enable Altivec instructions">; -def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", - "Enable GPUL instructions">; +def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", + "Enable the MFOCRF instruction">; def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", - "Enable the fsqrt instruction">; + "Enable the fsqrt instruction">; +def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", + "Enable the stfiwx instruction">; +def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", + "Enable the isel instruction">; +def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", + "Enable Book E instructions">; +def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", + "Enable QPX instructions">; //===----------------------------------------------------------------------===// // Register File Description @@ -42,40 +73,82 @@ include "PPCInstrInfo.td" // PowerPC processors supported. // -def : Processor<"generic", G3Itineraries, []>; -def : Processor<"601", G3Itineraries, []>; -def : Processor<"602", G3Itineraries, []>; -def : Processor<"603", G3Itineraries, []>; -def : Processor<"603e", G3Itineraries, []>; -def : Processor<"603ev", G3Itineraries, []>; -def : Processor<"604", G3Itineraries, []>; -def : Processor<"604e", G3Itineraries, []>; -def : Processor<"620", G3Itineraries, []>; -def : Processor<"g3", G3Itineraries, []>; -def : Processor<"7400", G4Itineraries, [FeatureAltivec]>; -def : Processor<"g4", G4Itineraries, [FeatureAltivec]>; -def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>; -def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>; -def : Processor<"750", G3Itineraries, []>; +def : Processor<"generic", G3Itineraries, [Directive32]>; +def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL, + FeatureBookE]>; +def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL, + FeatureBookE]>; +def : Processor<"601", G3Itineraries, [Directive601]>; +def : Processor<"602", G3Itineraries, [Directive602]>; +def : Processor<"603", G3Itineraries, [Directive603]>; +def : Processor<"603e", G3Itineraries, [Directive603]>; +def : Processor<"603ev", G3Itineraries, [Directive603]>; +def : Processor<"604", G3Itineraries, [Directive604]>; +def : Processor<"604e", G3Itineraries, [Directive604]>; +def : Processor<"620", G3Itineraries, [Directive620]>; +def : Processor<"750", G4Itineraries, [Directive750]>; +def : Processor<"g3", G3Itineraries, [Directive750]>; +def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>; +def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>; +def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>; def : Processor<"970", G5Itineraries, - [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + [Directive970, FeatureAltivec, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"g5", G5Itineraries, - [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + [Directive970, FeatureAltivec, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, + Feature64Bit /*, Feature64BitRegs */]>; +def : ProcessorModel<"e500mc", PPCE500mcModel, + [DirectiveE500mc, FeatureMFOCRF, + FeatureSTFIWX, FeatureBookE, FeatureISEL]>; +def : ProcessorModel<"e5500", PPCE5500Model, + [DirectiveE5500, FeatureMFOCRF, Feature64Bit, + FeatureSTFIWX, FeatureBookE, FeatureISEL]>; +def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, + FeatureMFOCRF, FeatureFSqrt, + FeatureSTFIWX, FeatureISEL, + Feature64Bit + /*, Feature64BitRegs */]>; +def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE, + FeatureMFOCRF, FeatureFSqrt, + FeatureSTFIWX, FeatureISEL, + Feature64Bit /*, Feature64BitRegs */, + FeatureQPX]>; +def : Processor<"pwr6", G5Itineraries, + [DirectivePwr6, FeatureAltivec, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, + Feature64Bit /*, Feature64BitRegs */]>; +def : Processor<"pwr7", G5Itineraries, + [DirectivePwr7, FeatureAltivec, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, + FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>; +def : Processor<"ppc", G3Itineraries, [Directive32]>; +def : Processor<"ppc64", G5Itineraries, + [Directive64, FeatureAltivec, + FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; -def PPC : Target { - // Pointers on PPC are 32-bits in size. - let PointerType = i32; +//===----------------------------------------------------------------------===// +// Calling Conventions +//===----------------------------------------------------------------------===// + +include "PPCCallingConv.td" - // According to the Mach-O Runtime ABI, these regs are nonvolatile across - // calls - let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, - R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, - F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, - F30, F31, CR2, CR3, CR4, LR]; +def PPCInstrInfo : InstrInfo { + let isLittleEndianEncoding = 1; +} + +def PPCAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + bit isMCAsmWriter = 1; +} - // Pull in Instruction Info: - let InstructionSet = PowerPCInstrInfo; +def PPC : Target { + // Information about the instructions. + let InstructionSet = PPCInstrInfo; + + let AssemblyWriters = [PPCAsmWriter]; }