X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCCodeEmitter.cpp;h=f80442ffc67114b64f3095d74f11a610cf97ece3;hb=97357614b5957cc167c261d3be54713802715d9a;hp=acca7a30ebc0312212efaf8489fc45736ed5fc49;hpb=794fd75c67a2cdc128d67342c6d88a504d186896;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index acca7a30ebc..f80442ffc67 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -2,13 +2,13 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to -// JIT-compile bytecode to native PowerPC. +// JIT-compile bitcode to native PowerPC. // //===----------------------------------------------------------------------===// @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineCodeEmitter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" @@ -37,12 +38,17 @@ namespace { /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr /// - int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO); + + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } public: - static const int ID; + static char ID; PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M) - : MachineFunctionPass((intptr_t)&ID), TM(T), MCE(M) {} + : MachineFunctionPass(&ID), TM(T), MCE(M) {} const char *getPassName() const { return "PowerPC Machine Code Emitter"; } @@ -62,9 +68,9 @@ namespace { /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. /// - unsigned getBinaryCodeForInstr(MachineInstr &MI); + unsigned getBinaryCodeForInstr(const MachineInstr &MI); }; - const int PPCCodeEmitter::ID = 0; + char PPCCodeEmitter::ID = 0; } /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code @@ -74,14 +80,12 @@ FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM, return new PPCCodeEmitter(TM, MCE); } -#ifdef __APPLE__ -extern "C" void sys_icache_invalidate(const void *Addr, size_t len); -#endif - bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); + + MCE.setModuleInfo(&getAnalysis()); do { MovePCtoLROffset = 0; MCE.startFunction(MF); @@ -96,16 +100,16 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ - MachineInstr &MI = *I; + const MachineInstr &MI = *I; switch (MI.getOpcode()) { default: - MCE.emitWordBE(getBinaryCodeForInstr(*I)); + MCE.emitWordBE(getBinaryCodeForInstr(MI)); + break; + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: + MCE.emitLabel(MI.getOperand(0).getImm()); break; - case PPC::IMPLICIT_DEF_GPRC: - case PPC::IMPLICIT_DEF_G8RC: - case PPC::IMPLICIT_DEF_F8: - case PPC::IMPLICIT_DEF_F4: - case PPC::IMPLICIT_DEF_VRRC: + case TargetInstrInfo::IMPLICIT_DEF: break; // pseudo opcode, no side effects case PPC::MovePCtoLR: case PPC::MovePCtoLR8: @@ -117,11 +121,12 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { } } -int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { +unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO) { - intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases + unsigned rv = 0; // Return value; defaults to 0 for unhandled cases // or things that get fixed up later by the JIT. - if (MO.isRegister()) { + if (MO.isReg()) { rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg()); // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the @@ -130,13 +135,14 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) { rv = 0x80 >> rv; } - } else if (MO.isImmediate()) { - rv = MO.getImmedValue(); - } else if (MO.isGlobalAddress() || MO.isExternalSymbol() || - MO.isConstantPoolIndex() || MO.isJumpTableIndex()) { + } else if (MO.isImm()) { + rv = MO.getImm(); + } else if (MO.isGlobal() || MO.isSymbol() || + MO.isCPI() || MO.isJTI()) { unsigned Reloc = 0; if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho || - MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF) + MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF || + MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8) Reloc = PPC::reloc_pcrel_bx; else { if (TM.getRelocationModel() == Reloc::PIC_) { @@ -187,19 +193,20 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { } MachineRelocation R; - if (MO.isGlobalAddress()) { + if (MO.isGlobal()) { R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, - MO.getGlobal(), 0); - } else if (MO.isExternalSymbol()) { + MO.getGlobal(), 0, + isa(MO.getGlobal())); + } else if (MO.isSymbol()) { R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, MO.getSymbolName(), 0); - } else if (MO.isConstantPoolIndex()) { + } else if (MO.isCPI()) { R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), - Reloc, MO.getConstantPoolIndex(), 0); + Reloc, MO.getIndex(), 0); } else { - assert(MO.isJumpTableIndex()); + assert(MO.isJTI()); R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), - Reloc, MO.getJumpTableIndex(), 0); + Reloc, MO.getIndex(), 0); } // If in PIC mode, we need to encode the negated address of the @@ -213,7 +220,7 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { } MCE.addRelocation(R); - } else if (MO.isMachineBasicBlock()) { + } else if (MO.isMBB()) { unsigned Reloc = 0; unsigned Opcode = MI.getOpcode(); if (Opcode == PPC::B || Opcode == PPC::BL_Macho || @@ -223,8 +230,7 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { else // BCC instruction Reloc = PPC::reloc_pcrel_bcx; MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), - Reloc, - MO.getMachineBasicBlock())); + Reloc, MO.getMBB())); } else { cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; abort();